JPH0645600A - Semiconductor integrted circuit device - Google Patents

Abstract

PURPOSE:To reduce the junction capacitances between the sources and drains of a MOS transistor and a substrate and to make possible the high-speed operation of the transistor. CONSTITUTION:A one conductivity type (P-type) high-concentration impurity layer 7 arranged in a self-alignment with a gate electrode 5 is formed in a semiconductor substrate directly under the gate electrode 5 of a MOS transistor formed in the one conductivity type (P-type) semiconductor substrate 1. Punch throughs between sources 3 and drains 4 are prevented from being generated by this P<+> impurity layer 7, while as the layer 7 does not exist directly under the sources 3 and the drains 4, the junction capacitances between the sources and drains 3 and 4 and the substrate 1 are reduced and the high-speed operation of a MOS transistor is made possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a MOS type semiconductor device integrated circuit device having a MOS transistor.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuit devices have been in the area of half-micron devices for higher density and higher performance. Furthermore, technological development aimed at quarter micron devices is required. MO like this
In the S-type semiconductor integrated circuit device, how to shorten the gate length by controlling punch-through between the source and drain of a MOS transistor is an important point. In general, to control punchthrough,
It suffices to increase the concentration of the substrate on which the MOS transistor is formed and the well formed on the substrate. However, this measure increases the impurity concentration on the substrate where the channel of the transistor is formed or on the surface of the well, so that a sufficient on-current is obtained. Cannot be ensured, and reliability is deteriorated due to an increase in hot carriers.

In order to solve this, there is a technique described in Nikkei Microdevice, page 67 (June 1991). As shown in FIG. 3, after forming the field oxide film 2 and the gate oxide film 6 on the P-type semiconductor substrate 1, high energy ion implantation is used to deeply implant the entire element at a deep position from the substrate surface. P ⁺ impurity layer 7 is formed. Then, the gate electrode 5 and the N ⁻ impurity layer 4 of the LDD are formed.
And N ⁺ impurity layer 3 are formed to form a MOS transistor.

Since such a buried P ⁺ impurity layer 7 prevents punch-through in a short channel and is buried from the substrate surface where the channel is formed,
The transistor has a sufficient on-current and exhibits excellent element characteristics in which reliability is less likely to deteriorate due to hot carriers. In addition, this technique is applied to a CMO forming a well.
N channel MOS transistor of S and P channel MO
The principle of the S-transistor is also the same as the above example.

[0005]

In this conventional MOS transistor, since the P ⁺ impurity layer 7 is formed over the region including the impurity layers 3 and 4 constituting the source / drain, the P ⁺ impurity layer between the source / drain and the substrate is formed. There is a problem that the junction capacitance becomes large and high-speed operation becomes difficult. An object of the present invention is to provide a semiconductor integrated circuit device capable of reducing the junction capacitance between the source / drain and the substrate and enabling high speed operation.

[0006]

According to the present invention, a high conductivity type of one conductivity type self-aligned with a gate electrode is formed in a semiconductor layer immediately below a gate electrode of a MOS transistor formed in a semiconductor layer of one conductivity type. An impurity layer is formed.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 is a sectional view of a MOS transistor according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the MOS transistor in the order of manufacturing steps. First, as shown in FIG. 2A, after forming the P ⁺ guard ring impurity layer 8 and the field oxide film 2 on the P-type semiconductor substrate 1, a pad oxide film 9 is formed on the entire surface by 400 Å,
Nitride film 10 of mask material is 1000Å, and CVD oxide film 11
To grow up to 3000Å. Then, a photoresist 12 is applied, the photoresist 12 in the region where the gate electrode is to be arranged is opened by using the photolithography technique, and the CVD oxide film 11 and the nitride film 10 are made reactive by using the photoresist 12. Etch using an ion etching technique. Further, by using this as a mask material and using an ion implantation technique, the buried P ⁺ impurity layer 7 for punch-through prevention is set to 150K.
It is formed by eV.

Next, as shown in FIG. 2B, the photoresist 12 is removed, the exposed pad oxide film 9 is removed, and a new gate oxide film 6 of 70 Å is formed. A film thickness of ½ or more of the opening width is grown so that the crystalline silicon 5 is completely filled at least in the opening portion.
Further, as shown in FIG. 2C, the gate electrode material is left only in the opening using the etching back technique to form the gate electrode 5 self-aligned with the buried impurity layer 7. Then, as shown in FIG. 1, the CVD oxide film 11 and the nitride film 10 of the mask material are sequentially removed, and the N ^- impurity layer 4 of the LDD and the etching back side wall of the CVD oxide film 11 are used to form the source and drain. The N ⁺ impurity layer 3 is formed to complete the MOS transistor.

In the MOS transistor configured as described above, the P ⁺ impurity layer 7 is self-aligned with the gate electrode 5, so that the N ⁻ impurity layer 4 and the N ⁺ impurity layer 3 of the LDD are formed.
It doesn't exist directly under. Therefore, the P ⁺ impurity layer 7 prevents punch-through between the source and drain, while preventing an increase in the junction capacitance between the source and drain and the substrate, and enables the MOS transistor to operate at high speed. still,
Although the above-mentioned embodiment shows the example of the N-type MOS transistor formed on the P-type semiconductor substrate, the same can be applied to the P-type MOS transistor and the CMOS structure formed on the well.

[0010]

As described above, according to the present invention, since the high-concentration impurity layer is formed immediately below the gate electrode, punch-through between the source and drain is prevented, while the source and drain are bonded to the substrate. There is an effect that it is possible to realize a high-speed compatible short-channel MOS transistor without an increase in capacity.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of a MOS transistor according to the present invention.

FIG. 2 is a cross-sectional view showing an embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view showing an example of a conventional MOS transistor.

[Explanation of symbols]

1 P-type semiconductor substrate 3 N ^- impurity layer 4 N ⁺ impurity layer 5 gate electrode 7 P ⁺ impurity layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7377-4M H01L 29/78 301 L

Claims (1)

[Claims] 1. A semiconductor integrated circuit device comprising a MOS transistor having a source / drain region of opposite conductivity type provided in a semiconductor layer of one conductivity type and a gate electrode provided on the surface of the semiconductor layer. A semiconductor integrated circuit device, wherein a high-concentration impurity layer of one conductivity type self-aligned with the gate electrode is formed in the semiconductor layer directly below the semiconductor layer.