TW274600B - Method and apparatus for improving system performance in a data processing system - Google Patents

Method and apparatus for improving system performance in a data processing system

Info

Publication number
TW274600B
TW274600B TW084110576A TW84110576A TW274600B TW 274600 B TW274600 B TW 274600B TW 084110576 A TW084110576 A TW 084110576A TW 84110576 A TW84110576 A TW 84110576A TW 274600 B TW274600 B TW 274600B
Authority
TW
Taiwan
Prior art keywords
instruction
dib
instructions
executed
ldis
Prior art date
Application number
TW084110576A
Other languages
English (en)
Inventor
Hopkins Martine
Nair Ravindrak
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW274600B publication Critical patent/TW274600B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30061—Multi-way branch instructions, e.g. CASE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Hardware Redundancy (AREA)
  • Communication Control (AREA)
TW084110576A 1995-04-13 1995-10-07 Method and apparatus for improving system performance in a data processing system TW274600B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/421,272 US5699536A (en) 1995-04-13 1995-04-13 Computer processing system employing dynamic instruction formatting

Publications (1)

Publication Number Publication Date
TW274600B true TW274600B (en) 1996-04-21

Family

ID=23669880

Family Applications (1)

Application Number Title Priority Date Filing Date
TW084110576A TW274600B (en) 1995-04-13 1995-10-07 Method and apparatus for improving system performance in a data processing system

Country Status (10)

Country Link
US (1) US5699536A (zh)
EP (1) EP0737915B1 (zh)
JP (1) JP3093629B2 (zh)
KR (1) KR100230552B1 (zh)
CN (1) CN1122227C (zh)
AT (1) ATE210851T1 (zh)
CA (1) CA2168896A1 (zh)
DE (1) DE69524570T2 (zh)
ES (1) ES2168329T3 (zh)
TW (1) TW274600B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8035600B2 (en) 2006-06-05 2011-10-11 Chunghwa Picture Tubes, Ltd. Image contrast correction system and method thereof

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6105124A (en) * 1996-01-26 2000-08-15 Intel Corporation Method and apparatus for merging binary translated basic blocks of instructions
JP3623840B2 (ja) * 1996-01-31 2005-02-23 株式会社ルネサステクノロジ データ処理装置及びマイクロプロセッサ
JPH09265397A (ja) * 1996-03-29 1997-10-07 Hitachi Ltd Ｖｌｉｗ命令用プロセッサ
US5913054A (en) * 1996-12-16 1999-06-15 International Business Machines Corporation Method and system for processing a multiple-register instruction that permit multiple data words to be written in a single processor cycle
US5923862A (en) * 1997-01-28 1999-07-13 Samsung Electronics Co., Ltd. Processor that decodes a multi-cycle instruction into single-cycle micro-instructions and schedules execution of the micro-instructions
US6009263A (en) * 1997-07-28 1999-12-28 Institute For The Development Of Emerging Architectures, L.L.C. Emulating agent and method for reformatting computer instructions into a standard uniform format
US6237077B1 (en) * 1997-10-13 2001-05-22 Idea Corporation Instruction template for efficient processing clustered branch instructions
US5913047A (en) * 1997-10-29 1999-06-15 Advanced Micro Devices, Inc. Pairing floating point exchange instruction with another floating point instruction to reduce dispatch latency
US6249855B1 (en) * 1998-06-02 2001-06-19 Compaq Computer Corporation Arbiter system for central processing unit having dual dominoed encoders for four instruction issue per machine cycle
US6240510B1 (en) 1998-08-06 2001-05-29 Intel Corporation System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions
US6304960B1 (en) 1998-08-06 2001-10-16 Intel Corporation Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions
US6385708B1 (en) * 1998-11-16 2002-05-07 Infineon Technologies Ag Using a timing-look-up-table and page timers to determine the time between two consecutive memory accesses
US6247097B1 (en) 1999-01-22 2001-06-12 International Business Machines Corporation Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions
JP2001005675A (ja) * 1999-06-21 2001-01-12 Matsushita Electric Ind Co Ltd プログラム変換装置及びプロセッサ
US6708267B1 (en) * 2000-02-04 2004-03-16 International Business Machines Corporation System and method in a pipelined processor for generating a single cycle pipeline stall
WO2001065362A1 (en) * 2000-02-28 2001-09-07 Koninklijke Philips Electronics N.V. Data processor with multi-command instruction words
GB2367653B (en) 2000-10-05 2004-10-20 Advanced Risc Mach Ltd Restarting translated instructions
US6622269B1 (en) * 2000-11-27 2003-09-16 Intel Corporation Memory fault isolation apparatus and methods
US6877089B2 (en) 2000-12-27 2005-04-05 International Business Machines Corporation Branch prediction apparatus and process for restoring replaced branch history for use in future branch predictions for an executing program
US7072347B2 (en) * 2001-02-23 2006-07-04 International Business Machines Corporation Assignment of packet descriptor field positions in a network processor
US7356673B2 (en) * 2001-04-30 2008-04-08 International Business Machines Corporation System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form
US7114058B1 (en) * 2001-12-31 2006-09-26 Apple Computer, Inc. Method and apparatus for forming and dispatching instruction groups based on priority comparisons
US7761852B2 (en) * 2003-11-26 2010-07-20 International Business Machines Corporation Fast detection of the origins of memory leaks when using pooled resources
US7665070B2 (en) * 2004-04-23 2010-02-16 International Business Machines Corporation Method and apparatus for a computing system using meta program representation
US7730470B2 (en) * 2006-02-27 2010-06-01 Oracle America, Inc. Binary code instrumentation to reduce effective memory latency
US8301870B2 (en) * 2006-07-27 2012-10-30 International Business Machines Corporation Method and apparatus for fast synchronization and out-of-order execution of instructions in a meta-program based computing system
JP4996945B2 (ja) * 2007-02-28 2012-08-08 公立大学法人広島市立大学 データ処理装置、データ処理方法
US8281109B2 (en) 2007-12-27 2012-10-02 Intel Corporation Compressed instruction format
CN101290589B (zh) * 2007-12-27 2010-06-16 华为技术有限公司 一种并发指令操作方法和装置
CN102063330B (zh) * 2011-01-05 2013-04-24 北京航空航天大学 一种大规模并行程序性能数据采集方法
US9395988B2 (en) * 2013-03-08 2016-07-19 Samsung Electronics Co., Ltd. Micro-ops including packed source and destination fields
GB2514618B (en) * 2013-05-31 2020-11-11 Advanced Risc Mach Ltd Data processing systems
US20150220343A1 (en) * 2014-02-05 2015-08-06 Mill Computing, Inc. Computer Processor Employing Phases of Operations Contained in Wide Instructions
GB2539411B (en) * 2015-06-15 2017-06-28 Bluwireless Tech Ltd Data processing
US11829187B2 (en) 2022-01-30 2023-11-28 Simplex Micro, Inc. Microprocessor with time counter for statically dispatching instructions
US11829762B2 (en) 2022-01-30 2023-11-28 Simplex Micro, Inc. Time-resource matrix for a microprocessor with time counter for statically dispatching instructions
US11829767B2 (en) 2022-01-30 2023-11-28 Simplex Micro, Inc. Register scoreboard for a microprocessor with a time counter for statically dispatching instructions
US11954491B2 (en) 2022-01-30 2024-04-09 Simplex Micro, Inc. Multi-threading microprocessor with a time counter for statically dispatching instructions
US20230315474A1 (en) * 2022-04-05 2023-10-05 Simplex Micro, Inc. Microprocessor with apparatus and method for replaying instructions

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4295193A (en) * 1979-06-29 1981-10-13 International Business Machines Corporation Machine for multiple instruction execution
US4466061A (en) * 1982-06-08 1984-08-14 Burroughs Corporation Concurrent processing elements for using dependency free code
US4484272A (en) * 1982-07-14 1984-11-20 Burroughs Corporation Digital computer for executing multiple instruction sets in a simultaneous-interleaved fashion
JPS5932045A (ja) * 1982-08-16 1984-02-21 Hitachi Ltd 情報処理装置
US4679141A (en) * 1985-04-29 1987-07-07 International Business Machines Corporation Pageable branch history table
GB8521672D0 (en) * 1985-08-30 1985-10-02 Univ Southampton Data processing device
US5021945A (en) * 1985-10-31 1991-06-04 Mcc Development, Ltd. Parallel processor system for processing natural concurrencies and method therefor
US4903196A (en) * 1986-05-02 1990-02-20 International Business Machines Corporation Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor
US4825360A (en) * 1986-07-30 1989-04-25 Symbolics, Inc. System and method for parallel processing with mostly functional languages
US4811214A (en) * 1986-11-14 1989-03-07 Princeton University Multinode reconfigurable pipeline computer
US5127104A (en) * 1986-12-29 1992-06-30 Dataflow Computer Corporation Method and product involving translation and execution of programs by automatic partitioning and data structure allocation
US4992938A (en) * 1987-07-01 1991-02-12 International Business Machines Corporation Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers
DE69030931T2 (de) * 1989-04-24 1998-01-15 Ibm Mehrfachsequenzprozessorsystem
US5197137A (en) * 1989-07-28 1993-03-23 International Business Machines Corporation Computer architecture for the concurrent execution of sequential programs
EP0454985B1 (en) * 1990-05-04 1996-12-18 International Business Machines Corporation Scalable compound instruction set machine architecture
EP0474297B1 (en) * 1990-09-05 1998-06-10 Koninklijke Philips Electronics N.V. Very long instruction word machine for efficient execution of programs with conditional branches
US5299321A (en) * 1990-12-18 1994-03-29 Oki Electric Industry Co., Ltd. Parallel processing device to operate with parallel execute instructions
CA2109799A1 (en) * 1991-05-24 1992-12-10 Daniel Mark Nosenchuck Optimizing compiler for computers
US5347639A (en) * 1991-07-15 1994-09-13 International Business Machines Corporation Self-parallelizing computer system and method
US5408658A (en) * 1991-07-15 1995-04-18 International Business Machines Corporation Self-scheduling parallel computer system and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8035600B2 (en) 2006-06-05 2011-10-11 Chunghwa Picture Tubes, Ltd. Image contrast correction system and method thereof

Also Published As

Publication number Publication date
ES2168329T3 (es) 2002-06-16
JP3093629B2 (ja) 2000-10-03
CA2168896A1 (en) 1996-10-14
CN1136184A (zh) 1996-11-20
CN1122227C (zh) 2003-09-24
ATE210851T1 (de) 2001-12-15
JPH0922354A (ja) 1997-01-21
KR960038600A (ko) 1996-11-21
DE69524570D1 (de) 2002-01-24
EP0737915B1 (en) 2001-12-12
KR100230552B1 (ko) 1999-11-15
EP0737915A1 (en) 1996-10-16
US5699536A (en) 1997-12-16
DE69524570T2 (de) 2002-08-22

Similar Documents

Publication Publication Date Title
TW274600B (en) Method and apparatus for improving system performance in a data processing system
US3787673A (en) Pipelined high speed arithmetic unit
TW325536B (en) Method and apparatus for accessing a register in a data processing system
JPS6436336A (en) Calculator system
KR900012155A (ko) 데이타 처리 시스템
WO1993009492A3 (en) Out of order job processing method and apparatus
US20120011404A1 (en) Method and system of a processor-agnostic encoded debug-architecture in a pipelined environment
EP0378415A3 (en) Multiple instruction dispatch mechanism
CN111813670A (zh) 一种非侵入式mc/dc覆盖率统计分析方法
EP0196964B1 (en) System for adjusting performance of information processing apparatus
EP0331191A3 (en) Information processing system capable of carrying out advanced execution
CA2005907A1 (en) Production line method and apparatus for high performance instruction execution
JPH07253888A (ja) データ処理装置
US6115807A (en) Static instruction decoder utilizing a circular queue to decode instructions and select instructions to be issued
US7324112B1 (en) System and method for processing divergent samples in a programmable graphics processing unit
US6912647B1 (en) Apparatus and method for creating instruction bundles in an explicitly parallel architecture
EP0234785A1 (en) Improvements relating to control flow in computers
JP2636136B2 (ja) 演算処理装置及び演算処理方法
JPS56114051A (en) Data process system
JPS5556235A (en) Initializing method of terminal controller on decentralized control system
US20030033552A1 (en) Apparatus and method for wait state analysis in a digital signal processing system
Dannenberg Real Time Control For Interactive Computer Music and Animation
JP2895892B2 (ja) データ処理装置
JPS60146339A (ja) スキヤンイン・アウト方式
EP1235139A3 (en) System and method for supporting precise exceptions in a data processor having a clustered architecture