TW239203B - Encoding/decoding device - Google Patents
Encoding/decoding deviceInfo
- Publication number
- TW239203B TW239203B TW83107421A TW83107421A TW239203B TW 239203 B TW239203 B TW 239203B TW 83107421 A TW83107421 A TW 83107421A TW 83107421 A TW83107421 A TW 83107421A TW 239203 B TW239203 B TW 239203B
- Authority
- TW
- Taiwan
- Prior art keywords
- output
- input
- cpu
- outputting
- computer system
- Prior art date
Links
Landscapes
- Executing Machine-Instructions (AREA)
Abstract
A programmable encoding/decoding device in computer system whose structure consists of one CPU and one memory for storing the logic mapping code, includes: 1. one decoder for receiving the address output of CPU and outputting one decoding enable signal under the preset programmable state; 2. one register comprised of flip-flops, whose output is connected to the data bus of the CPU and outputting the input signal triggered by the received decoding enable signal; 3. one encoder with two set of inputs and one set of output in which the first set of input is connected to the memory output, the second set of input is connected to the register output, and conducting the preset logic operation to the two sets of input and output the result to the data bus of the computer system.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW83107421A TW239203B (en) | 1994-08-13 | 1994-08-13 | Encoding/decoding device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW83107421A TW239203B (en) | 1994-08-13 | 1994-08-13 | Encoding/decoding device |
Publications (1)
Publication Number | Publication Date |
---|---|
TW239203B true TW239203B (en) | 1995-01-21 |
Family
ID=51400779
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW83107421A TW239203B (en) | 1994-08-13 | 1994-08-13 | Encoding/decoding device |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW239203B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI698743B (en) * | 2015-06-26 | 2020-07-11 | 美商英特爾公司 | Apparatus with embedded programmable data checking components, computing system and method for performing application data checking |
-
1994
- 1994-08-13 TW TW83107421A patent/TW239203B/en active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI698743B (en) * | 2015-06-26 | 2020-07-11 | 美商英特爾公司 | Apparatus with embedded programmable data checking components, computing system and method for performing application data checking |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR880004380A (en) | Bus master with burst transfer mode | |
DE3375611D1 (en) | Bus interface device for a data processing system | |
KR860700300A (en) | Input memory circuit means and its distribution method | |
TW239203B (en) | Encoding/decoding device | |
KR840001410A (en) | Programmable Logic Units | |
KR970031616A (en) | Communication system for selectively using multiple communication transmission methods | |
KR910001545A (en) | CPU core | |
SU1564633A1 (en) | Device for addressing immediate-access memory | |
KR860004360A (en) | Microprocessor Interface Device for Telecommunication System | |
KR930004862A (en) | Redundant interface device using dual port memory | |
KR960016271B1 (en) | Exchange riset -out circuit | |
JPS5730060A (en) | Address space expansion system | |
JPS5745657A (en) | Storage device | |
KR930020843A (en) | Clock signal selection circuit | |
KR880013336A (en) | Bus system for selective communication of data | |
KR890017617A (en) | DMA counter circuit | |
KR970012074A (en) | Register set method and circuit | |
KR880008174A (en) | Interrupt processing control circuit that processes multiple interrupt signals with one interrupt terminal | |
JPS6120295A (en) | Integrated circuit for address control | |
KR970029828A (en) | Memory access devices | |
TW370639B (en) | Device and method of a write-protected basic input output system memory | |
KR920010447A (en) | Data loss prevention circuit between CPUs using dual port RAM | |
KR930010754A (en) | Shared resource access request control device | |
JPS5717062A (en) | Parity checking system | |
DE3270119D1 (en) | Cpu of a digital multibit computer system |