TW210402B - A semiconductor device with a memory cell array region - Google Patents

A semiconductor device with a memory cell array region Download PDF

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Publication number
TW210402B
TW210402B TW082100028A TW82100028A TW210402B TW 210402 B TW210402 B TW 210402B TW 082100028 A TW082100028 A TW 082100028A TW 82100028 A TW82100028 A TW 82100028A TW 210402 B TW210402 B TW 210402B
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conductivity
bias
conductivity type
voltage
type
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TW082100028A
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Chinese (zh)
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Dong-Jae Lee
Dong-Soo Jun
Dong-Sun Min
Yong-Sik Seok
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device with a memory cell array region and peripheral circuit region integrated in a first-conductivity-type substrate comprises a first group of power supply pads for only supplying the memory cell array region, a second group of power supply pads for only supplying the peripheral circuit region, a third group of power supply pads for only supplying the plurality of word lines and TTL input buffers, a third group of power supply pads for only supplying the data output drivers, first second-conductivity-type wells with at least first first- conductivity-type wells formed in the memory cell array region and connected with the first group of power supply pads, second second-conductivity-type wells with at least first first-conductivity-type wells formed in the peripheral circuit region and connected with the second group of power supply pads, a first plurality of second-conductivity-type MOS transistors formed in the first first-conductivity-type wells and connected with the third group of power supply pads, and a second plurality of second-conductivity-type MOS transistors formed in the second first-conductivity-type wells and connected with the fourth group of power supply pads.

Description

Λ 6 BG 210402 五、發明説明（1.) f 靖ϋ?Λ-·'1ν而之;.t.t^-Jii再填寫本頁} 本發明係有關於一半導體裝置，特別有關於一具有三 重井結構之記憶裝置。 因爲半導體記憶裝置的容量和密度大量增加，半導體 記憶裝置的結構和處理技術是需要改變的。特別是爲了要 在有限的面積内達到高複雜性，三維的結構已被使用在具 有超過四百萬位元容量的半導體記憶裝置中。另外，因爲 用在半導體記憶體中之矽氧化金屬電晶體（M0S)的大小已 經縮小’所以使用一較低之内部電壓源。再者，由於高複 雜性，雜訊的問題便產生了。當然，爲了減少能量的消耗 ’記憶裝置應有最小的資料出入時間。 訂 第1A圖顯示一六千四百萬位元的動随機記憶器（ DRAM)，此DRAM由四個記憶電池陣列區塊（m〇m〇ry cell array bl〇ck)100，110，120，130,和周邊線路區域（Per- lperal circuit region)所形成。第ID和 1E囷顯示 經濟部中央標準局员工消費合作社印製 分別安置在記憶電池陣列區域1 〇〇和周邊電路區域4〇〇中的 典型電路。第1B囷顯示一位元線路之電路，包含位元線路 之等效電路50和60、記憶電池S1和61，N和P型感應放大 器52和62 ’隔離閘53和63，行閘55，字線路WL1和WL2，及 位元線路BL和/BL。同樣的，第1C圖的時鐘脈衝產生器用 來產生時鐘脈衝，以驅動一列解碼器/字線路，包含第1£) 圖的TTL輸入緩衝器丽，第1E圖的資料輸出緩衝器/驅動 機等等，都明白的示於圖中。然而値得注意的是圖中電晶 禮86、87、88應用一逆閘級(backgate)電壓v BB和本發明 有關。 本紙張尺度適用中國國家標準（CNS>甲4規格（210 X 297公釐） Λ6 B6 210402 五、發明説明（2·) 如第1A囷所示，當用一p型基質製造一半導體記憶裝 置時，一具有PMOS電晶體之N#(N-well)於基質中形成， 且一NMOS電晶體在基質中形成。在此例中，基質是應用一 已知位準的基質偏壓"(Substrate bias vottage);通常是 接地電恩（ground voltage)，及一具有逆閘級電麼之N井 ，或有時依”井偏麼>(well bais voltage)”而定，由此 來設定電晶體的臨界電壓（threshad voltage)。相反的， 假如基質是一具有P型#2N型基質，則P#應用在逆閘 級電壓，以調節一在卩井中形成的NM0S電晶體之臨界電壓 。有關逆閘級電壓的技術，如揭露於韓國專利申請字號86 -6557，施加一具有單元電晶體之P#，以防止因字線路 驅動電晶體的臨界電壓和單元電晶體間之差異所產生的資 料流失。事實上，一至少超過一千六百萬位元的高複雜性 記憶裝置有數百萬的#在基質中形成，這些井被施加一# 偏壓或逆閘極電屡，電壓値由元件的慣例來設定。Λ 6 BG 210402 V. Description of the invention (1.) f Jing ϋ? Λ- · '1ν and; tt ^ -Jii then fill out this page} The present invention relates to a semiconductor device, in particular to a triple well Structured memory device. Because the capacity and density of semiconductor memory devices have greatly increased, the structure and processing technology of semiconductor memory devices need to be changed. Especially in order to achieve high complexity in a limited area, a three-dimensional structure has been used in semiconductor memory devices having a capacity of more than four million bits. In addition, because the size of the silicon oxide metal transistor (MOS) used in semiconductor memory has been reduced, a lower internal voltage source is used. Furthermore, due to the high complexity, noise problems arise. Of course, in order to reduce energy consumption, the memory device should have a minimum data access time. Figure 1A shows a 16-megabit dynamic random access memory (DRAM), which consists of four memory cell array blocks (m〇m〇ry cell array bl〇ck) 100, 110, 120 , 130, and the peripheral circuit region (Per-lperal circuit region) formed. ID and 1E show typical circuits printed in the Memory Consumer Array Area 100 and the Peripheral Circuit Area 400 by the Employees Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Section 1B shows the circuit of the one-bit line, including the equivalent circuits 50 and 60 of the bit line, memory batteries S1 and 61, N and P-type sense amplifiers 52 and 62 'isolation gates 53 and 63, line gate 55, Lines WL1 and WL2, and bit lines BL and / BL. Similarly, the clock generator in Figure 1C is used to generate clock pulses to drive a column of decoders / word lines, including the TTL input buffer in Figure 1), the data output buffer in Figure 1E / driver, etc. Etc. are clearly shown in the figure. However, it should be noted that the application of a backgate voltage v BB to the transistors 86, 87, 88 in the figure is related to the present invention. This paper scale is applicable to the Chinese national standard (CNS> A4 specifications (210 X 297 mm) Λ6 B6 210402 V. Description of the invention (2 ·) As shown in 1A, when a p-type substrate is used to manufacture a semiconductor memory device , An N # (N-well) with PMOS transistors is formed in the matrix, and an NMOS transistor is formed in the matrix. In this example, the matrix is applied with a known level of substrate bias " (Substrate bias vottage); usually ground voltage, and an N-well with reverse gate level, or sometimes depending on "well bias" (well bais voltage) ", to set the voltage The threshold voltage (threshad voltage) of the crystal. Conversely, if the substrate is a P-type # 2N-type substrate, P # is applied to the reverse gate voltage to adjust the critical voltage of a NMOS transistor formed in the well. The technology of reverse gate voltage, such as disclosed in Korean Patent Application No. 86-6557, applies a P # with a unit transistor to prevent data generated by the difference between the critical voltage of the word line driving transistor and the unit transistor Loss. In fact, one at least exceeds One thousand six million yuan high complexity of millions of memory device formed in a matrix #, # wells are applied a reverse gate bias power or repeatedly, Zhi voltage set by convention element.

第二圖顯示#偏壓在記憶電池陣列區域和周邊電路區 域的應用。如第二圖所顯示，由N+/P/N組成的三重#結構 ，揭露於IEEE JSSC ;第24册，第5號，1989年10月PP. 1170-1174)。記憶單元陣列區域100有一個具p #23的N #22。很快的可以了解，一形成於P #23中的剛0S電晶體 31和一形成於N #22中的PM0S電晶體32，分別在記憶單元 陣列區域100中構成N形和P形感應放大器。同時，在一 周邊電路區域400中，一形成於P#24中的NM0S電晶體33 和一形成於N #25中的PM0S電晶體34分別提供一 TTL輸入 $纸張尺度適用中國國家標準（CNS)甲4規格（210 X 297公釐) — -------------------r(------^------1T------^ f (•"屯閲--背而之^-麥^再場寫本頁) 經濟部中央標準居8工消费合作社印製 210402 B6 五、發明説明（3.) (^先間"背而之注-?項再塡.^本頁) 緩衝器和資料輸出驅動機。在記憶單元陣列區域100中， •I宰· 一 P #23的#偏電極26 (或NM0S電晶體31的逆閘極電極） 施加一接地電歷"Vss或負電廢Vbb，以及具一電恩源Vcc 之N # 22的#偏電極27 (或PM0S電晶體32的逆閘極電極） 。在周邊電路區域400中，？#24的#偏電極28 (或NMOS 電晶禮33的逆閘級電極）施加一接地電恩Vss或逆閘極電 壓VBB，及具電恩源Vcc之25的#偏電極29 (或PM0S電 晶髏34的逆閘極電極）。卩型基質21的電極30接地。形成 於記憶單元陣列區域100中的Ν'井22以電的方式隔離d井 23和Ρ型基質21，並且阻止#的#偏壓間的干擾。這是三 重#使用在高複雜性之記憶裝置的優點。 " 經濟部中央標华局貝工消費合作社印製 然而，如果Ρ #23和24的#偏電極26和28施加一接地 電IVSS或逆閘極電壓Vbb，則以下的問題就發生了。第 一，在接地電壓爲Vss時，因爲大多數的位元線路都形成 於記憶單元陣列區域内的P#區域，所以它們的靜電容增 加，一位元線路電容Cb和一記憶單元儲存電容cs的比CB /Cs也不利的增加。一位元線和一N+擴散區域相接；此 區域爲N0MS電晶體31的汲極，構成一電流鏡型的n型感應 放大器，此放大器形成於記憶陣列的ρ井23中，如第1B 囷所示之N型感應放大器52。如果位元線路電容較儲存電 容大，則記憶單元的資料出入時間會延遲。這可在此技術 中明白知道。再者，因爲記憶電池陣列區域的ρ并和周邊 電路區通常接地，由周邊線路中之接地電磨引起的雜訊， 干擾了在記憶單元陣列區域中的接地電廢。此對記憶電池 各紙張尺度適用中國®家標準（CNS)甲4規格（21〇 X 297公釐） 經濟部中央標準局KT工消費合作社印製 2XMS12l 五、發明説明（4.) 的運作特性有不利的影響。 第二，如果#偏電極26和28施加一負電壓Vbb，並且 具一短頻道（short-channet)的電晶體用在周邊電路區中 ，此短頻道會在負電壓產生器產生負電壓Vbb到達所希望 電壓位準之前，引起臨界電壓的下降，所以閂上（LAT CH_ UP)的現象會發生。負電壓不像電壓源和接地電壓會維持 在一固定位準，所以需要以連績回饋（feedback)運作來適 當的補償（compensation)，以維持正常的電壓位準。一振 盘器’及電荷栗源（charge pump)等，是用來使負電歷維 持在希望的正常電壓位準的。閂上現象是因負電壓偏差影 響在基質中寄生接面（parasitic junctions)所形成的寄 生元件而引起的，因此造成半導體記憶裝置的錯誤作用。 本發明的目的是提供一装置，防止一半導體記憶裝置 的錯誤作用，此錯誤作用是由一在記憶單元陣列區域和周 邊電路區域間的電壓源雜訊所產生。 本發明的另一目的是提供一裝置以提供穩定之電的絕 緣於基質和高複雜性半導體裝置的井之間。 根據本發明，提供一具有記憶電池陣列區域和周邊電 路區域的半導體裝置，此裝置聚積於第一傳導係數型（ f i rst-conduct i v i ty-type)之基質上，其中記憶單元陣列 區域有複數的字線路、位元線路，記憶電池，感應放大器 、列解碼器、以及字線路驅動機，並且周邊電路區域有複 數之TTL輸入緩衝器和資料輸出驅動機，此装置包括：第 一群電源供應器緩衝襯墊，此僅供應記憶電池陣列區域； 本紙張尺度適用中酉酉家標準（CNS)甲4規格（210 X 297公釐） (^先閲-..:-11.|-)而之：;11.&户*.0再塡寫本頁) -裝. --4· 210402 Λ6 B6 五、發明説明（5.) <靖先間4背而之;t.4麥咁再填寫表頁> 第二群電源供應器緩衝概塾，此僅供應周邊電路區域；第 三群電源供應器緩衝概#，此僅供應複數的字線路及TTL 輸入緩衝器；第二群電源供應器緩衝襯勢，此僅供應資料 輸出驅動機；具有至少第一傳導係數型井的第一個第二傳 導係數型井，形成於記憶電池陣列區域中並和第一群電源 供應器緩衝襯墊連接；具至少第一個第一傳導係數型井的 第二群個第二傳導低數型，形成於周邊電路區域，並且和 第二群電源供應器緩衝襯餐連接；第一個複數之第二傳導 係數型MOS電晶體形成於第一個第一傳導係數型井之中， 並且和第三群電源供應器緩衝襯墊連接；第二個複數之第 二傳導係數型MOS電晶體形成於第二個第一傳導係數型井 之内，並且和第四群電源供應器緩衝襯墊連接。 現在將僅以舉例的方式，並參考附圖來描述本發明。 第1A圖説明一六千四百萬位元位數的drAM，第1B囷和 第1C圖顯示位元線路之電路及列解碼器/字線路驅動時鐘 脈衝產生器，分別形成於記憶單元陣列區域内。而第1DS 和第1E囷顯示一TTL輸入緩衝器和資料輸出緩衝器/驅動 器，分別形成於周邊電路區域内； 烴濟部中央標準居8工消费合作社印製 第2圖是一概要圖，用來説明一應用#偏壓在第一圖 中記憶單元陣列區域和周邊電路區域的傳統方法。 第3A囷，第3B圖和第3C圖説明本發明的一實施例。 第4A圖和第4B圖説明本發明的另一實施例，分別應用 在記憶單元陣列區域和周邊電路區域；The second figure shows the application of #bias in the memory battery array area and the peripheral circuit area. As shown in the second figure, the triple # structure composed of N + / P / N is disclosed in IEEE JSSC; Volume 24, No. 5, October 1989 PP. 1170-1174). The memory cell array area 100 has an N # 22 with p # 23. It will soon be understood that a rigid OS transistor 31 formed in P # 23 and a PMOS transistor 32 formed in N # 22 form N-type and P-type sense amplifiers in the memory cell array area 100, respectively. At the same time, in a peripheral circuit area 400, an NMOS transistor 33 formed in P # 24 and a PMOS transistor 34 formed in N # 25 provide a TTL input $ paper size, respectively. China National Standard (CNS ) A 4 specifications (210 X 297 mm) — ------------------- r (------ ^ ------ 1T --- --- ^ f (• " Tunyue--Contrary ^ -Mai ^ write this page again) Printed by the Ministry of Economic Affairs Central Standard Home 8 Industrial and Consumer Cooperatives 210402 B6 V. Description of invention (3.) (^ First Time " Contrary note-? Item again. ^ This page) Buffer and data output driver. In the memory cell array area 100, • I Slave • One P # 23 # Polar electrode 26 (or NMOS The reverse gate electrode of the crystal 31) is applied with a grounding calendar " Vss or negative power waste Vbb, and the # bias electrode 27 (or the reverse gate electrode of the PMOS transistor 32) of N # 22 with an electrical source Vcc. In the peripheral circuit area 400, # 24 # bias electrode 28 (or the reverse gate electrode of NMOS transistor 33) is applied with a ground current Vss or reverse gate voltage VBB, and a power source with Vcc 25 #Bias electrode 29 (or the reverse gate electrode of PMOS transistor 34). The electrode 30 of the matrix 21 is connected to The N 'well 22 formed in the memory cell array area 100 electrically isolates the d well 23 and the p-type matrix 21, and prevents interference between # 的 bias. This is the triple # used in highly complex memories Advantages of the device. &Quot; Printed by the Beigong Consumer Cooperative of the Central Standardization Bureau of the Ministry of Economic Affairs. However, if the # bias electrodes 26 and 28 of the # 23 and 24 apply a grounding voltage IVSS or reverse gate voltage Vbb, the following problems It happened. First, when the ground voltage is Vss, because most of the bit lines are formed in the P # area in the memory cell array area, their static capacitance increases, and the bit line capacitance Cb and a memory cell The storage capacitor cs ratio CB / Cs is also unfavorably increased. One bit line is connected to an N + diffusion area; this area is the drain of the NOMS transistor 31, forming a current mirror type n-type sense amplifier, which is formed In the ρ well 23 of the memory array, an N-type sense amplifier 52 as shown in Fig. 1B. If the bit line capacitance is larger than the storage capacitance, the data access time of the memory cell will be delayed. This can be clearly known in this technology . Furthermore, because The ρ of the battery array area and the surrounding circuit area are usually grounded. The noise caused by the grounding electric grinder in the peripheral circuit interferes with the grounding electrical waste in the memory cell array area. This applies to all paper sizes of the memory battery China® National Standard (CNS) A 4 specifications (21〇X 297 mm) 2XMS12l printed by the KT Industrial and Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy 5. The operating characteristics of the invention description (4.) have an adverse effect. Second, if a negative voltage Vbb is applied to the #bias electrodes 26 and 28, and a transistor with a short-channel (short-channet) is used in the peripheral circuit area, this short-channel will generate a negative voltage Vbb at the negative voltage generator to reach Before the desired voltage level, the threshold voltage drops, so the phenomenon of latching (LAT CH_UP) will occur. Negative voltage is not maintained at a fixed level like the voltage source and ground voltage, so it is necessary to use continuous feedback operation to properly compensate to maintain the normal voltage level. A vibrator, charge pump, etc. are used to maintain the negative electrical calendar at the desired normal voltage level. The latch-up phenomenon is caused by the negative voltage deviation affecting the parasitic junctions formed in the matrix (parasitic junctions) parasitic junctions (parasitic junctions) caused by the parasitic junctions, thus causing the erroneous function of the semiconductor memory device. An object of the present invention is to provide a device to prevent an erroneous effect of a semiconductor memory device, which is caused by a voltage source noise between the memory cell array area and the peripheral circuit area. Another object of the present invention is to provide a device to provide stable electricity isolated between the substrate and the well of a highly complex semiconductor device. According to the present invention, a semiconductor device having a memory cell array area and a peripheral circuit area is provided. The device is accumulated on a substrate of a first conductivity type (first-conductivity type), wherein the memory cell array area has a plurality of Word line, bit line, memory battery, sense amplifier, column decoder, and word line driver, and the peripheral circuit area has multiple TTL input buffers and data output drivers. This device includes: the first group of power supplies Cushion pad, this only supplies the memory battery array area; the paper size is applicable to the Chinese unitary unit standard (CNS) A 4 specification (210 X 297 mm) (^ 先 读-..:-11. |-) and ：; 11. &Amp; household * .0 then write this page)-installed. --4 · 210402 Λ6 B6 Fifth, the invention description (5.) < Jingxianjian 4 back to it; t.4Mai Zai Zai Fill in the form page> The second group power supply buffer overview, this only supplies the peripheral circuit area; the third group power supply buffer overview #, this only supplies the plural word lines and the TTL input buffer; the second group power supply Buffer buffer, this only supplies the data output driver; A first second conductivity type well having at least a first conductivity type well formed in the memory cell array area and connected to the first group of power supply buffer pads; having at least a first first conductivity type well The second group of second conductive low-number types is formed in the peripheral circuit area and is connected to the second group of power supply buffer liners; the first complex second conductivity-type MOS transistors are formed on the first In a conductivity-type well, and connected to the third group of power supply buffer pads; the second complex second conductivity-type MOS transistor is formed in the second first conductivity-type well, and The fourth group of power supply buffer pads are connected. The invention will now be described by way of example only, with reference to the drawings. Figure 1A illustrates a drAM of 16 million bits. Figures 1B and 1C show the circuit of the bit line and the column decoder / word line drive clock generator, which are formed in the memory cell array area. Inside. The 1DS and 1E displays a TTL input buffer and a data output buffer / driver, which are formed in the peripheral circuit area respectively; The Ministry of Economy, Economy, Central Standards, Jugong, Gonggong Consumer Cooperative Printed the second picture is a schematic diagram, with To illustrate a traditional method of applying #bias to the memory cell array area and the peripheral circuit area in the first figure. Figures 3A, 3B, and 3C illustrate an embodiment of the present invention. FIGS. 4A and 4B illustrate another embodiment of the present invention, which are respectively applied to the memory cell array area and the peripheral circuit area;

第5圈説明根據本發明電源供應緩衝觀整應用在第3A $紙張/5¾用中國®家棣準(CNS)甲4規格（210 X 297公釐） Λ6 B6 210402 五、發明説明（6.：> ，38,3(：，4人和48圖的實施例； 第6圖是本發明的較佳實施例，此圖是依據第3A，3B, 3C，4A和4B圖，以及第5圖； 第7圖根據本發明説明了M0S電容器的構造； 第8圖説明在本實驗中使用之三重井形成的進行步驟 :以及 第9、10、11圖分別説明負電壓產生器的輸出特性， 電壓泵（VELTAGE PUMP)電路及内部電壓產生器。 第3圖顯示根據本發明#偏壓（或逆閘極電壓）如何 應用到第2圖的裝置上。參照第3A圖，施加於記憶陣列區 域100之卩#23的#偏壓是一負電壓VBB〇再者，一接地 電壓Vss被施加在一周邊電路區域400的P #24上。施加 在N#22和25的#偏壓是電壓源Vcc，而N#22和25形成 在記憶陣列和周邊電路區域。爲了使P#*N+擴散區域 間的接面逆向偏壓，記憶陣列區域提供P #23使用負電壓 ，而此N+擴散區域是NMOS電晶體31的汲極，因此降低一 位元線路之電容，也因此降低了一位元線路電容CB和記 憶單元儲存電容Cs的比’例C b/ C S。另外，施加於記 憶單元陣列和周邊電路區域之P#上的#偏壓分別是負電 廢和接地電恩’用來防止雜訊干擾。再者，周邊電路區域 提供接地電壓給p#24,因此短頻道引起的閂上現象和習 知技術比較是相當低的。 參照第3B囷，在周邊電路區域4〇〇中，一n#25施加 一電歷·源Vcc及具有接地電歷《vss或逆閘極電恩Vbb的p (請 t!y-:'l«·而 >/;.t.6p'切再填寫本> --° -4 經濟部中央標準局员工消费合作社印製 -9 - Λ6 B6 210402 i、發明説明（7.) #24,當在記憶單元陣列區域1⑽中時，N#22使用一比 電壓源及具接地電壓或負電壓的P并23還高的電壓Vpp， 以下簡稱”系電麼·”（pumping voltage)。此系電恩Vpp 是由配置在半導體装置中的高電壓產生器所產生。在此例 中，由周邊電路區域的電磨源所引起的維訊，不應對記憶 單元陣列區域有不利的影響。 參照第3C圖，在一周邊電路區域400中，N#25施加 一比電壓源Vcc及具接地電壓或負電壓的P #24還低的電 壓源VCC^VINT，以下簡稱”内部電壓’’（internal volltage)。當在一記憶單元陣列區域1〇〇中時，N#22施 加一内部電壓VINt及有接地電壓Vss或負電壓VBB,。此 和第3B圖所示有相同的結果。 參照第4A囷，在P型基質70中，形成二獨立之N#71 和N并72。Ν#Ή有一 P#73,此P#73具有一NM0S電晶 體74,此電晶體74在記憶單元陣列區域中，構成一N型感 應放大器。由上述可知，一酬0S在N#72中形成的PM0S電 晶體75,構成一 P型感應放大器於記憶單元睁列區域之 中。P井73施加一負電屋*Vbb ’如一井偏壓·（或一逆閘極 電壓），包圍P#37之Ν#Ή施加一泵電壓VPP或内部電 ,VINT且由N#71獨立出來的N#72施加一電壓源Vcc 。因此由電壓源產生的雜訊不會干擾卩#73的#偏壓，因 此安定了一半導體元件的運作。 參照第4B«，周邊電路區域的應用，N#81包固—具 有NM0S電晶體86的P # 83且# 81包困具有NM0S電晶體87和 表紙張尺度適用中國囷家標準（CNS>甲4規格（210 X 297公釐〉 —10 — _ ------------------------装------.iT^ (^t!y-.K·'而之;t4声,r,再填寫本 K > 經濟部中央標準局员工消費合作社印製 210402 Λ6 B6 經濟部中央標準局员工消费合作社印製 五、發明説明（8.) 88的P #84,此電晶體87和88是由N#81分離出來的。可 知電晶體86是一TTL輸入緩衝器的NMOS電晶體，而且電晶 體87和88形成於一資料輸入緩衝器/輸出驅動機（見第1E 圖）°NMOS電晶體的逆閘極電壓（或P#偏壓）都是負電 壓VBB。P#83和84由基質70中分離出來的，分別藉由N 并81和82施加一電壓源Vcc作用，此電壓源是由單獨的電 源供應緩衝襯墊提供。 通常，因爲一半導體裝置的電源供應緩衝概塾由單電 壓源緩衝襯墊和接地電壓緩衝禊墊所組成，在電壓源發生 的雜訊影響一記憶陣列區域，而此電壓源是施加於周邊電 路區域中的。爲了解決此問題，如第5囷所示，本發明利 用複數電源供應緩衝襯墊VCCLA、VCCRA、VSSLa、 VSSRA當作記憶陣列，及電源供應緩衝襯墊Vcc^p、 V CCRP 、VsSLP、VsSLP當作周邊電路。在此例中， 電源供應緩衝襯墊VCCLA、VCCLP、VSSLP用在左邊，同 時電源供應應緩衝襯墊VCCRA、VCCRP、VSSRA、vSSRP 用在右邊，再者左右接地電壓緩衝襯墊 供一字線/TTL輸入緩衝器。再者附加電壓源緩衝襯墊 VCCRD和接地電壓緩衝襯墊VSSRp被用來當作資料輸出驅 動機。因此在其中一個緩衝概墊中發生的雜訊，不會傳到 另一緩衝襯墊。 本發明電路的運作，現在將參照第6圖描述之。在p 型半導體基質70中，一記憶單元陣陣列區域100已經區分 了第一和第二N#22和91，並且周邊電路區域400區分第 (-:.ΐΓ^^-:.·!1'νώ >/;t.ftpJf!再塡寫本頁) 丨乂 -装. 訂. 本纸張尺度適用中國國家標华（CNS)甲4規格（21〇 X 297公梦） —11 — 9.10402 i 一 Λ6 B6 經濟部中央標箏局B工消费合作社印製 五、發明説明（9.) 三、第四、第五N#25，81和82及第一 P#24。第一N# 22具有第二P #23和第一PMOS電晶體32。第二P #23具有 第一NMOS電晶體31，此電晶體31用在記憶單元、N型感應 放大器，輸入/輸出閘，列解碼器/字線路驅動機和等效 電路。第一NMOS電晶體31 (或第二P#23的偏壓）是一負 電IVbb。第一PMOS電晶體32，用作P頻道(P _Cha nnel )感應放大器而且此電晶體32的逆閘極電壓是一個陣列電 麼源VcCA(VcCLA或VcCRA)。第二PMOS電晶體92形成於 第二N#91之中，用作一字線路驅動時鐘脈衝產生器（見 第1C圖），並且此電晶體92的逆閘極電壓（或第二N井的 #偏壓）是一泵電壓VPP。周邊電路區域400的第三N# 25具有一PM0S電晶體34,此電晶體34的逆閘極電壓是一周 邊電恩源Vccp(Vcclp或Bccrp)。在第一 P井24中形 成一NM0S電晶體33，此電晶體33的逆閘極電壓（或第一 p #的偏壓）是一周邊接地電蜃Vssp ( VSSLP或VSSRP )。在第四N#81中，形成第三P#83，P#83具一NMOS 電晶體86,此電晶體86的逆閘極電壓是負電壓VBB。一 施加於電晶體86源極的接地電壓，是一字線和ttl輸入緩 衝器的接地電恩VsSQ( VsSLQ或VsSRQ )。在第五N井82 中，形成具有NM0S電晶體87和88當作第1E圖輸出的第四p #84°電晶體88的源極是由一驅動器接地電壓vSSD和一 具有驅動機電歷·源VCCD之電晶體87的汲級所提供。電晶 禮87和88的後閘電恩（或第四p#的偏恩）是負電恩vBB 0第五N"井82是由周邊電恩源"\^(：〇?('\^0：0；1^)所提供〇 本紙張尺度適用中困國家標準（CNS>甲4規格（210 X 297公货） —12 - (請tr-i.l-;TK'而之;t.ftpJij再塡寫本頁) 丨裝. 訂. 210402 Λ 6 Β6 _ 五、發明説明（〗0·> 熟於此項技藝者很容易可以知道，偏壓（或電晶體的 逆閘極電恩）施加在#上可能有不同的設定。當然，第六 圖的實施例可適用於一N型基質。 參照第7圖，三重#結構的發明可被用來構成一MOS 電容。如第7A囷所示，施加一電壓源Vcc的第一共同電.極 (first common electrode)是由一NMOS電晶艘，P+擴散 區域107、108和形成於N#102内之N+擴散區域109連接 而成。再者，施加一接地電麼Vss的第二共同電極是由形 成於P #103内之擴散區域104和105、提供一後閘電壓的 P+擴散區域106、形成於基質1〇1内之P+擴散區域11〇 , 以及一PM0S電晶體的閘極112連接而成，然後產生並聯之 NMOS和PM0S電容的電容結構。參照第7B囷，PM0S和NM0S 電容是串聯的’其閘極施加一時鐘脈衝。在此例中，所有 形成P #内的擴散區域通常是接地的，並且所有形成於N 井内的擴散區域都和電恩源連接。除此之外，更多的實施 例可被完成。 第8圖説明了本發明三重#的製造進行步驟。很容易 可以知道，一P型矽單一晶體基質1被用來當作基質。基 質1由氧化物層2和氮化物層3連續覆蓋，如第8A圖所示 。一光阻體囷型4形成於氮化物層3、此光阻體選擇性的 刻蚀氮化物層3和氧化物層2，這是爲了要形成視窗（win dow) 5，透過此視窗，注入第五元素群的不純離子，如砷 和鱗，藉以形成一Ν'井如第8B圖所示。參照第％圖，一基 質的曝露表面很容易濕氧化（coat oxidati〇n),並且注入 本紙張认賴中@S家標準（CNS)甲4規格（21G X 297公ϋ — —13 —* f請"閲-、^而之注-麥项再堵寫本頁) 丨裝. '11. 經濟部中央標準居S工消费合作社印製 210402_ 五、發明説明（11.) 的不純雜質擴散形成一N#7。基質的曝露表面是由一厚 氧化物層6所覆蓋。在第8D圖的步驟中，移開厚氧化物層 6之後，剩下氧化物和氮化物層2和3，一薄緩衝襯墊氧 化物層8，被置於基質上。第二光阻體囷型9形成薄緩衝 襯墊氧化物層8，並且注入第三元素群的不純雜子，如硼 。然後，如第8E圖所示，在N# 7的内部、外部形成了 p #10和11。其後，形成了 #所需要的電晶體及逆閘極電恩 (或#偏壓）的通信接觸擴散區。 丨裝.The fifth circle illustrates the application of the power supply buffer observation according to the present invention in the 3A $ paper / 5¾ China® Jiadi Standard (CNS) A 4 specifications (210 X 297 mm) Λ6 B6 210402 V. Description of the invention (6 .: >, 38,3 (:, 4 people and the embodiment of Figure 48; Figure 6 is the preferred embodiment of the present invention, this figure is based on Figures 3A, 3B, 3C, 4A and 4B, and Figure 5 FIG. 7 illustrates the structure of the MOS capacitor according to the present invention; FIG. 8 illustrates the steps of forming the triple well used in this experiment: and FIGS. 9, 10, and 11 illustrate the output characteristics of the negative voltage generator, respectively Pump (VELTAGE PUMP) circuit and internal voltage generator. FIG. 3 shows how #bias (or reverse gate voltage) is applied to the device of FIG. 2 according to the present invention. Referring to FIG. 3A, it is applied to the memory array area 100 The # bias of # 23 is a negative voltage VBB. Furthermore, a ground voltage Vss is applied to P # 24 of a peripheral circuit area 400. The # bias applied to N # 22 and 25 is a voltage source Vcc , And N # 22 and 25 are formed in the memory array and the peripheral circuit area. In order to reverse bias the junction between P # * N + diffusion area , The memory array area provides P # 23 using a negative voltage, and this N + diffusion area is the drain of the NMOS transistor 31, thus reducing the capacitance of the bit line, and thus reducing the bit line capacitance CB and the memory cell storage capacitance The ratio of Cs' example C b / CS. In addition, the # bias applied to P # of the memory cell array and the peripheral circuit area are negative electrical waste and ground electrical energy respectively to prevent noise interference. Furthermore, the peripheral circuit The area provides a ground voltage to p # 24, so the latch-up phenomenon caused by the short channel is relatively low compared with the conventional technology. Referring to the third 3B, in the peripheral circuit area 400, an n # 25 applies an electrical calendar. Source Vcc and p with grounding calendar "vss or reverse gate current Vbb" (please t! Y-: 'l «· >/;. t.6p' cut and fill in this book>-° -4 Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs -9-Λ6 B6 210402 i. Description of invention (7.) # 24, when in the memory cell array area 1⑽, N # 22 uses a voltage source with a grounding voltage or The negative voltage P23 is also a high voltage Vpp, hereinafter referred to as "pumping voltage" (pumping voltage). This is the electrical Vpp is Generated by a high-voltage generator arranged in a semiconductor device. In this example, the dimension information caused by the electric grinder source in the peripheral circuit area should not adversely affect the memory cell array area. Refer to FIG. 3C In the peripheral circuit area 400, a voltage source VCC ^ VINT lower than the voltage source Vcc and P # 24 having a ground voltage or a negative voltage is applied to N # 25, hereinafter referred to as "internal voltage" (internal voltage). When in a memory cell array area 100, N # 22 applies an internal voltage VINt and a ground voltage Vss or a negative voltage VBB. This has the same result as shown in Figure 3B. Referring to No. 4A, in the P-type matrix 70, two independent N # 71 and N # 72 are formed. Ν # Ή has a P # 73, and this P # 73 has a NMOS transistor 74, which forms an N-type sense amplifier in the memory cell array area. As can be seen from the above, the PMOS transistor 75 formed in N # 72 by a single OSS constitutes a P-type sense amplifier in the open area of the memory cell. P-well 73 applies a negative electricity house * Vbb 'such as a well bias voltage (or a reverse gate voltage), surrounding P # 37 of Ν # Ή applies a pump voltage VPP or internal electricity, VINT and is independent from N # 71 N # 72 applies a voltage source Vcc. Therefore, the noise generated by the voltage source does not interfere with the # bias of # 73, so the operation of a semiconductor device is stabilized. Refer to Section 4B «, Application of Peripheral Circuit Area, N # 81 Packed—P # 83 with NMOS Transistor 86 and # 81 Packed with NMOS Transistor 87 and Sheet Paper Scale Applicable to China's Standards of Home (CNS> A Specifications (210 X 297 mm> —10 — _ --------------------------------------------. IT ^ (^ t! y-.K · 'and; t4 sound, r, then fill in this K > printed by the Ministry of Economic Affairs Bureau of Central Standards employee consumption cooperative printed 210402 Λ6 B6 printed by the Ministry of Economic Affairs Central Bureau of Standards employee consumption cooperative printed five, description of invention (8. ) P # 84 of 88, the transistors 87 and 88 are separated by N # 81. It can be seen that the transistor 86 is an NMOS transistor of a TTL input buffer, and the transistors 87 and 88 are formed in a data input buffer / Output driver (see Figure 1E) ° The reverse gate voltage (or P # bias) of the NMOS transistor is a negative voltage VBB. P # 83 and 84 are separated from the matrix 70, respectively by N and 81 and 82 apply a voltage source Vcc, which is provided by a separate power supply buffer pad. Generally, because the power supply buffer of a semiconductor device is composed of a single voltage source buffer pad and a ground voltage buffer As a result, the noise generated at the voltage source affects a memory array area, and this voltage source is applied to the peripheral circuit area. To solve this problem, as shown in Figure 5, the present invention uses a plurality of power supply buffer pads VCCLA, VCCRA, VSSLa, VSSRA are used as memory arrays, and power supply buffer pads Vcc ^ p, V CCRP, VsSLP, VsSLP are used as peripheral circuits. In this example, power supply buffer pads VCCLA, VCCLP, VSSLP are used in On the left, the power supply should use buffer pads VCCRA, VCCRP, VSSRA, and vSSRP on the right, and the left and right ground voltage buffer pads provide a word line / TTL input buffer. Furthermore, additional voltage source buffer pads VCCRD and ground voltage The buffer pad VSSRp is used as a data output driver. Therefore, the noise generated in one of the buffer pads will not be transmitted to the other buffer pad. The operation of the circuit of the present invention will now be described with reference to FIG. 6 In the p-type semiconductor matrix 70, a memory cell array area 100 has distinguished the first and second N # 22 and 91, and the peripheral circuit area 400 distinguishes the (-:. lΓ ^^-: ..! 1'νώ >/; t.ftpJf! and then write this page) 丨 乂-装. Ordered. This paper standard applies to China National Standard (CNS) A 4 specifications (21〇X 297 Gongmeng) — 11 — 9.10402 i one Λ6 B6 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, B Industry and Consumer Cooperative Fifth, Invention Instructions (9.) Third, Fourth, and Fifth N # 25, 81 and 82, and the first P # 24. The first N # 22 has a second P # 23 and a first PMOS transistor 32. The second P # 23 has a first NMOS transistor 31, which is used in a memory cell, an N-type sense amplifier, an input / output gate, a column decoder / word line driver, and an equivalent circuit. The first NMOS transistor 31 (or the bias of the second P # 23) is a negative IVbb. The first PMOS transistor 32 is used as a P-channel (P_Chanel) sense amplifier and the reverse gate voltage of this transistor 32 is an array source VcCA (VcCLA or VcCRA). The second PMOS transistor 92 is formed in the second N # 91 and used as a word line driving clock pulse generator (see FIG. 1C), and the reverse gate voltage of this transistor 92 (or the second N well) #Bias) is a pump voltage VPP. The third N # 25 of the peripheral circuit area 400 has a PMOS transistor 34, and the reverse gate voltage of this transistor 34 is a peripheral electrical source Vccp (Vcclp or Bccrp). An NMOS transistor 33 is formed in the first P well 24, and the reverse gate voltage of the transistor 33 (or the bias voltage of the first p #) is a peripheral grounding phantom Vssp (VSSLP or VSSRP). In the fourth N # 81, a third P # 83 is formed. The P # 83 has an NMOS transistor 86 whose reverse gate voltage is a negative voltage VBB. A ground voltage applied to the source of the transistor 86 is the ground current VsSQ (VsSLQ or VsSRQ) of a word line and ttl input buffer. In the fifth N-well 82, the source of the fourth p # 84 ° transistor 88 having NMOS transistors 87 and 88 as the output of FIG. 1E is formed by a driver ground voltage vSSD and a source Provided by the Ji stage of the transistor 87 of the VCCD. The rear gate of the Jingjing Li 87 and 88 (or the bias of the fourth p #) is the negative electrical vBB 0 fifth N " well 82 is by the surrounding electrical en source " \ ^ (： 〇? ('\ ^ 0: 0; 1 ^) The paper standard provided is applicable to the national standard in the middle of trouble (CNS> A 4 specifications (210 X 297 public goods) — 12-(please tr-il-; TK 'and; t.ftpJij again (Write this page) 丨 Installed. Ordered. 210402 Λ 6 Β6 _ V. Description of the invention (〗 0 ·> It is easy for those skilled in this art to know that the bias voltage (or the reverse gate of the transistor) is applied There may be different settings on #. Of course, the embodiment of the sixth figure can be applied to an N-type substrate. Referring to FIG. 7, the invention of the triple # structure can be used to form a MOS capacitor. As shown in FIG. 7A The first common electrode of a voltage source Vcc is connected by an NMOS transistor, P + diffusion regions 107, 108 and N + diffusion region 109 formed in N # 102. , The second common electrode applying a ground current Vss is formed by diffusion regions 104 and 105 formed in P # 103, a P + diffusion region 106 providing a back gate voltage, and a P + diffusion region formed in the substrate 101 11〇, and a PM0S transistor gate 112 is connected, and then generate a parallel NMOS and PMOS capacitor capacitance structure. Referring to the 7th B, PM0S and NMOS capacitors are connected in series' the gate applies a clock pulse. In this example, all the diffusion regions formed in P # are usually grounded, and all the diffusion regions formed in Well N are connected to the power source. In addition, more embodiments can be completed. Figure 8 It illustrates the manufacturing steps of the triple # of the present invention. It is easy to know that a P-type silicon single crystal substrate 1 is used as the substrate. The substrate 1 is continuously covered by the oxide layer 2 and the nitride layer 3, as shown in FIG. 8A As shown, a photoresist body type 4 is formed on the nitride layer 3, and the photoresist body selectively etches the nitride layer 3 and the oxide layer 2 in order to form a window (win dow) 5 through which In the window, impure ions of the fifth element group, such as arsenic and scales, are implanted to form a N ′ well as shown in Figure 8B. Referring to Figure%, the exposed surface of a substrate is easily wet oxidized (coat oxidation), And inject this paper to recognize Laizhong @ S 家 标准 （CNS) A4 rule (21G X 297 Gong ϋ — —13 — * f Please " Read-, ^ And the note-Wheel and then write this page) 丨 installed. '11. Central Standards of the Ministry of Economic Affairs Printed by S S & C Cooperative Cooperative 210402_ 2. Description of the invention (11.) Impure impurities diffuse to form an N # 7. The exposed surface of the substrate is covered by a thick oxide layer 6. In the step of FIG. 8D, after removing the thick oxide layer 6, the remaining The lower oxide and nitride layers 2 and 3, a thin buffer liner oxide layer 8, are placed on the substrate. The second photoresist body type 9 forms a thin buffer pad oxide layer 8, and implants impure impurities of the third element group, such as boron. Then, as shown in FIG. 8E, p # 10 and 11 are formed inside and outside N # 7. After that, the communication contact diffusion area of #required transistor and reverse gate electrode (or #bias) is formed.丨 Install.

、1T 第9、10和11®分別顯示本發明中負電壓（vBB)產 生器、泵電壓（Vpp)產生器和内部電壓（VINT)產生 器的輸入特性。負電屋·產生器和内部電壓產生器通常用在 DRAM中。泵電壓產生器的特性明白的揭露於iEEE jSSC， Aug,1991,PP117)。 雖然以上實施例是用於P型基質，事實上也可用於N 型基質。另外，本發明可運用在所有裝置，這些裝置是由 具有DRAM的C0MS所構成。 1. 經濟部中央櫺準局员工消费合作社印製 本紙張尺度適用中國固家標準（CNS)甲4規格（210 X 297公i ) -14 -, 1T, 9, 10, and 11® show the input characteristics of the negative voltage (vBB) generator, pump voltage (Vpp) generator, and internal voltage (VINT) generator in the present invention, respectively. The negative electricity house generator and internal voltage generator are usually used in DRAM. The characteristics of the pump voltage generator are clearly disclosed in iEEE jSSC, Aug, 1991, PP117). Although the above embodiments are for P-type substrates, they can also be used for N-type substrates. In addition, the present invention can be applied to all devices which are composed of CMOS with DRAM. 1. Printed by the Employee Consumer Cooperative of the Central Bureau of Trade and Industry of the Ministry of Economic Affairs. This paper is compliant with China Gujia Standard (CNS) Grade 4 (210 X 297 g) -14-

Claims (1)

A7 經濟部中央標準局8工消費合作社印製 >40^ B7 C7 ___D7 六、 申請專利範困 1· 一半導體裝置，該装置包括： 一第一第二傳導係數型#，此井形成於第一傳導係數 型半導體基質上，並且施加第一偏壓； 一第一傳導係數型#，此#形成於該第—第二傳導係 數型#，並且施加第二偏恩；以及 一第二第二傳導係數型井，此#形成於該第一傳導係 數型#，並且和該第二偏壓連接。 2·如申請專利範園第1項之半導體裝置，其中該第一傳 導係數型半導體基質施加第三偏壓。 3. 如申請專利範園第2項之半導體裝置，其中該第一傳 導係數型井包括一第二傳導係數型M0S電晶體的活性 區域。 4. 如申請專利範園第3項之半導體裝置，其中至少一該 第二傳導係數型井包括一第一傳導係數型M〇s電晶體 Ο 5·如申請專利範園第1項之半導體裝置，更包括另一第 二傳導係數形#，此#具—第—傳導錄獅純晶 體，此電晶體由該第二傳導係數型井隔離，並且施加 第四偏壓。 6. 如申請專利細第5項之半導嫌裝置，其中對-已知 電位而言，該第一偏壓較電壓源高，該第二偏壓是負 値，該第三偏壓是接地電壓，並且該第四偏壓是該電 壓源。 7. 如申料5項之半物裝置，其中對一已知 (請先閲讀背面之注意事項再塡寫本頁) --裝=- 訂‘ .丨民A7 Printed by the Ministry of Economic Affairs, Central Bureau of Standards, 8 Industrial and Consumer Cooperatives > 40 ^ B7 C7 ___D7 Sixth, apply for patents 1. A semiconductor device, the device includes: a first second conductivity coefficient type #, this well is formed in the A conductivity type semiconductor substrate, and a first bias voltage is applied; a first conductivity type #, this # is formed in the first-second conductivity type #, and a second bias is applied; and a second second Conductivity type well, this # is formed in the first conductivity type #, and is connected to the second bias. 2. A semiconductor device as claimed in item 1 of the patent application park, wherein the first conductivity-type semiconductor substrate is applied with a third bias voltage. 3. The semiconductor device according to item 2 of the patent application park, wherein the first conductivity-type well includes an active region of a second conductivity-type MOS transistor. 4. The semiconductor device according to item 3 of the patent application park, wherein at least one of the second conductivity-type wells includes a first conductivity type M〇s transistor. , And further includes another second conductivity coefficient shape #, this # 具 — 第 — 导 录 录 纯 晶, this transistor is isolated by the second conductivity type well, and a fourth bias voltage is applied. 6. A semiconducting device as described in item 5 of the patent application, where for a known potential, the first bias voltage is higher than the voltage source, the second bias voltage is negative, and the third bias voltage is ground Voltage, and the fourth bias is the voltage source. 7. If you apply for the half-item device of item 5, one of them is known (please read the notes on the back before writing this page) --install == order ‘. 丨 Min ~~ 15 ~ 經濟部中央標準局貝工消费合作社印製 A7 B7 210402 C7 六、申請專利範团 電位而言，第一偏壓較電壓源低，該第二偏壓是負値 ，該第三偏歷是接地電恩，並且該第四偏壓是該電壓 源0 8. —半導體裝置，此裝置具有一記憶單元陣列區域，以 及聚積在第一傳導係數型基質内的周邊電路區域，包 括： /一第一個第二傳導係數型#，此#具有一第一傳導係 數型MOS電晶體，此電晶體形成於記憶單元陣列區域 之内，並且施加第一偏壓； 一第一個第一傳導係數型#，此#具有一第二傳導係 數型MOS電晶體，此電晶體形成於該第一個第二傳導 係數型#，並且施加第二偏壓； 一第二第一傳導係數型#，此#具有一第二傳導係數 型MOS電晶體，此電晶體形成於該周邊電路區域之内 ，並且施加第三偏廢；以及 7第二個第二傳導係數型井，此#具一第一傳導係數 型MOS電晶體，此電晶體形成於該周邊線路區域，此 電晶體由該第二個第一傳導係數型#中隔離，並且施 加第一偏壓。 、/7 9.如申請專利範圍第8項之半導體裝置，其中該第一傳 導係數型基質包括一高濃度的第一傳導係數型擴散區 域，此區域和該第三偏壓連接。 10.如申請專利範園第9項之半導體裝置者，其中該第一 偏壓是一電壓源，該第二偏壓是一負電壓，並且該第 本紙張尺度適用中國國家標準（CNS)甲4規格（210 X 297公釐） 一 16 — (請先閲讀背面之注意事項再塡寫本頁) .裝Γ 、ΤΓ. 經濟部中央標準局R工消費合作杜印製 A7 210402 g D7 六、申請專利範团 三偏恩是接地電恩。 11. 如申請專利範園第10項之半導體裝置，更包括一負電 壓產生器，用來產生該負電壓。 12. —半導體裝置，此装置‘具有一記憶單元陣列區域及周 邊電路區域，此區域聚積在第一傳導係數型基質内， 包括： 一第一第二傳導係數型#，此#具有一第一傳導係數 型M0S電晶體，此電晶髏形成於該記憶單元陣列區域 ，並且施加第一偏壓； 一第一個第一傳導係數型井，此井具有一第二傳導係 數型M0S電晶體，此電晶禮形成於該周邊電路，並且 施加該第二偏壓，以及 一第二個第二傳導係數型中，此井具有一第一傳導係 數型M0S電晶體，此電晶體形成於該周邊電路區域， 其且由該第二第一傳導係數型#隔離，並且施加第三 偏壓。 13. 如申請專利範園第12項之半導體裝置，其中該第一傳 導係數型基質包括一高濃度第一傳導係數型擴散區域 ，此區域是由該井隔離，並且與該第二偏壓連接。 14. 如申請專利範圍第13項之半導體裝置，其中對一已知 電位而言，該第一偏壓較電壓源高。該第二偏壓是接 地電恩，並且該第三偏壓是該電屡源。 15. 如申請專利範園第13項之半導體裝置，其中對一已知 電位而言，該第一偏壓·較電麼·源高，該第二偏壓是負 狀錢种® ⑽）甲嶋⑵0 X 297讀)--— -17 - (請先聞讀背面之注意事項再塡寫本頁) 丨裝- 訂· 經浒部屮央標準局貝工消费合作社印製 210402 A7 —lm__ 六、申請專利範園 電塵，韃第三偏壓是t饜源0 Ιβ·如申請專利範面第ls項之半導髖裝藏，其中韃第一傳 導係數型基質包括一高濃度第一傳導係數型姨牧區埃 •此區滅典該接地電靨連接。 I7·如申請專利範面第W或第1S項之半導《裝襞，更包括 一電麝泵電路，此電路是對一巳知電位而言，產生一 較該電I源高之電廛。 I8.如申請專利範面第1Z項之半導體裝置，其中對一已知 電位而言，該第一偏壓較電蘑源低，該第二偏壓是负 電塵，並且第三偏屡是該電I源。 I9·如申請專利範腾第1δ項之半導饉裝藏，其中對一已知 電位而言，第一偏屨較電屦源低，該第二偏屦是負電 饜，並且對一已知電位而言，該第三偏蘑較電屦源低 〇 2〇·如申請專利範面第is項之半導饉裝置，更包括一内部 電I產生器，此電雇產生器在一已知電位下，產生一 較隸電廛源低的電壓。 21* —半導體裝置，此裝藏具有一聚集在第一傳導係數到 基貧内的記憶單元陣列區墩及周逢電路區域，該記億 單元陣列區域有琴數之字線路、字元線路、記憶電池 、感應教大器、列解碼器和字線路槳動器，該用邊線 路區填有複數之TTL输入緩衝器和資料输出摩動機， 包括： 第一尊贫源供應緩衝襯鏊，僅用象供應該記憶單元陣 本纸》尺度適用中國a家標準(CNS)甲4規格(210x297公釐） Λ 一 η一 f請先閔讀背面va意事項再¾寫本頁j ·/ .訂. A7 ^ B7 2i〇4〇^ 〇7~~ 15 ~ A7 B7 210402 C7 printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 6. For patent application potential, the first bias voltage is lower than the voltage source, the second bias voltage is negative, the third The bias is grounded, and the fourth bias is the voltage source. 8. Semiconductor device, this device has a memory cell array area and a peripheral circuit area accumulated in the first conductivity type matrix, including: / A first second conductivity coefficient type #, this # has a first conductivity type MOS transistor, the transistor is formed in the memory cell array area, and a first bias is applied; a first first Conductivity type #, this # has a second conductivity type MOS transistor, the transistor is formed in the first second conductivity type #, and a second bias is applied; a second first conductivity type # , This # has a second conductivity type MOS transistor, the transistor is formed in the peripheral circuit area, and the third bias is applied; and 7 the second second conductivity type well, ## has a first Conductivity type MOS transistor In the body, the transistor is formed in the peripheral circuit area, the transistor is isolated by the second first conductivity type #, and a first bias is applied. / 7. 9. The semiconductor device of claim 8, wherein the first conductivity-type matrix includes a high-concentration first conductivity-type diffusion region, which is connected to the third bias voltage. 10. If applying for a semiconductor device in the 9th category of the Patent Fan Garden, wherein the first bias voltage is a voltage source, the second bias voltage is a negative voltage, and the first paper standard is applicable to the Chinese National Standard 4 Specifications (210 X 297 mm) One 16 — (Please read the precautions on the back before writing this page). Install Γ, ΤΓ. Ministry of Economic Affairs Central Standards Bureau R Industrial and Consumer Cooperation Du Printed A7 210402 g D7 VI. The patent application group San Pian En is a grounded electric en. 11. The semiconductor device as claimed in item 10 of the patent application park further includes a negative voltage generator for generating the negative voltage. 12. —Semiconductor device, this device has a memory cell array area and a peripheral circuit area, this area is accumulated in the first conductivity type matrix, including: a first second conductivity type #, this # has a first Conductivity type MOS transistor, the transistor is formed in the memory cell array area, and a first bias is applied; a first first conductivity type well, this well has a second conductivity type MOS transistor, The transistor is formed in the peripheral circuit, and the second bias is applied, and in a second second conductivity type, the well has a first conductivity type MOS transistor, the transistor is formed in the periphery The circuit area, which is isolated by the second first conductivity type #, and a third bias voltage is applied. 13. The semiconductor device according to item 12 of the patent application park, wherein the first conductivity type matrix includes a high concentration first conductivity type diffusion region, which is isolated by the well and connected to the second bias . 14. A semiconductor device as claimed in item 13 of the patent application, wherein the first bias voltage is higher than the voltage source for a known potential. The second bias voltage is grounded, and the third bias voltage is the electrical source. 15. For example, in the semiconductor device of Patent Application Section 13, where the first bias voltage is higher than the power source and the second bias voltage is negative for a known potential (⑽) A嶋 ⑵0 X 297 read) --- -17-(please read the precautions on the back and then write this page) 丨 Installation-Order · Printed by Beibei Consumer Cooperative of the Bureau of Standards, Margin, Ministry of Agriculture 210402 A7 —lm__ Six 1. Apply for patent Fanyuan Electric Dust, the third bias of the tantalum is t source 0 Ιβ. As in the semi-conducting hip storage of item ls of the patent application, where the matrix of the first conductivity coefficient type includes a high concentration of first conductivity Coefficient type aunty area Ai • This area should be grounded and connected to the ground. I7. If the semi-conducting device of the patent application item W or item 1S includes an electric musk pump circuit, this circuit generates a higher electric current than the electric I source for a known electric potential. I8. The semiconductor device according to item 1Z of the patent application scope, wherein for a known potential, the first bias voltage is lower than the electric mushroom source, the second bias voltage is negative dust, and the third bias is repeatedly The electric I source. I9. For example, the semi-conductor storage of item 1δ of the patent application Fanteng, where the first bias is lower than the electric source for a known potential, the second bias is a negative charge, and is known for a In terms of electric potential, the third partial mushroom is lower than the electric source by 0.02. For example, the semiconducting device of patent application item is, it also includes an internal electric I generator. This electric generator is known in the art. Under the electric potential, a voltage lower than that of the electrical source is generated. 21 * —Semiconductor device, this storage has a memory cell array area pier and Zhou Feng circuit area gathered in the first conductivity coefficient to the basic poverty, the memory cell area has a zigzag word line, character line, Memory battery, induction sensor, column decoder and word line propeller, the side line area is filled with multiple TTL input buffers and data output motors, including: The first source of poor supply buffer liner, only "The memory cell array paper is supplied with the image". The scale is applicable to China's a standard (CNS) A4 specifications (210x297 mm). Λ 一 η 一 fPlease read the back page va notes first and then write this page j · /. . A7 ^ B7 2i〇4〇 ^ 〇7 經濟部中央標準局8工消费合作社印製 六、申請專利範園 列區域； 第二群電源供應緩衝概整，僅用來供應該周邊電路區 域； 第三群電源供應緩衝襯墊，僅用來供應該複數之字線 路及TTL輸入緩衝器； 第四群電源供應缓衝襯墊，僅用來供應該資料輪出驅 動機； 具有至少第一個第一傳輸係數型井的第一個第二傳輸 係數井，形成於該記憶單元陣列區域，並且和該第一 群電源供應緩衝襯墊連接； 具有至少有第一個第一傳輸係數型#的第二個第二傳 輸係數型井，形成於該周邊電路區域中，並且和該第 二群電源供應緩衝襯墊連接； 第一複數之第二傳導係數型MOS電晶體，此電晶體形 成於該第一個第一傳輸係數型#之中，並和該第三群 電源供應緩衝襯墊連接；以及 第二複數之第二傳導係數型MOS電晶體，此電晶體形 成於該第二第一傳輸係數型#之中，並且和第四群電 源供應緩衝襯墊連接。 22. —半導體装置包括： 一第一傳輸係數型基質； 一第二傳輸係數型井，此井形成於該基質； 一形成於該第一傳輸係數型#中之第一第二傳輸係數 型MOS電晶髏，及第一高濃度第一傳輸係數型擴散區 本紙張尺度適用中國國家樣準（CNS)甲4規格（210 X 297公釐） —19 — (請先閲讀背面之注意事項再塡寫本頁) 丨裝- 訂_ B7 C7 D7 210402 六、申請專利範圍 域； 一第二第一傳輸係數型MOS電晶體和第二高濃度第二 傳輸係數型擴散區域； 一第三高濃度第一傳輸係數型擴散區域，歧區域形成 於該第一傳輸係數型基質之内， 其中該第一M0S電晶體的源極和汲極，該第一高濃度 擴散區域、該第二M0S電晶體的閘極，以及該第三高 濃度擴散區域通常是連接的， 其中該第一M0S電晶體的閘極、該第二M0S電晶體的汲 極和源極，以及該第二高濃度擴散區域通常是連接的 (請先閲讀背面之注意事項再塡寫本頁) —裝- ,11. 經濟部中央標準局貝工消费合作社印製 本紙張尺度適用中國國家標準（CNS)甲4規格（210 X 297公釐） -20 -Printed by the Central Standards Bureau of the Ministry of Economic Affairs, 8 Industrial and Consumer Cooperatives. 6. Patent application areas listed; the second group of power supply buffers is summarized and used only to supply the peripheral circuit area; the third group of power supply buffers is used only for Supply the complex ZigZag circuit and TTL input buffer; the fourth group of power supply buffer pads are only used to supply the data wheel drive driver; the first and the second with the first well with the first transmission coefficient A transmission coefficient well formed in the memory cell array area and connected to the first group of power supply buffer pads; a second second transmission coefficient well having at least a first first transmission coefficient type # formed in In the peripheral circuit area, and connected to the second group of power supply buffer pads; the first complex second conductivity type MOS transistor, the transistor is formed in the first first transmission coefficient type #, And connected to the third group of power supply buffer pads; and a second complex second conductivity coefficient type MOS transistor formed in the second first transmission coefficient type #, and A fourth group connected to the power supply cushioning pad. 22. The semiconductor device includes: a first transmission coefficient type matrix; a second transmission coefficient type well formed in the substrate; a first second transmission coefficient type MOS formed in the first transmission coefficient type # Electric crystal skull, and the first high-concentration, first-transmission-coefficient diffusion zone. The paper size is applicable to China National Standards (CNS) A 4 specifications (210 X 297 mm) —19 — (Please read the precautions on the back before reading (Write this page) 丨 Package-book_ B7 C7 D7 210402 Six. Patent application domain; a second first transmission coefficient type MOS transistor and a second high concentration second transmission coefficient type diffusion area; a third high concentration A transmission coefficient type diffusion region, a divergent region is formed within the first transmission coefficient type matrix, wherein the source and the drain of the first MOS transistor, the first high concentration diffusion region, the second MOS transistor The gate and the third high-concentration diffusion region are usually connected, wherein the gate of the first MOS transistor, the drain and source of the second MOS transistor, and the second high-concentration diffusion region are usually connected( Read the precautions on the back first and then write this page) — Installation-, 11. The paper size printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs applies the Chinese National Standard (CNS) A4 specifications (210 X 297 mm)- 20-
TW082100028A 1992-07-13 1993-01-05 A semiconductor device with a memory cell array region TW210402B (en)

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