JP2000101045A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make effective use of a dead space located near to a bottom N well by a method, wherein a MOS capacitor that is possessed of electrodes which face opposite each other through the intermediary of an insulating film and located distance from a boundary between a second and a third well by a prescribed distance is provided on the top side of a third well. SOLUTION: A DRAM is equipped with an N-type bottom well 15, that is formed on a semiconductor substrate 10 coming into contact with the base of a P well 14. Furthermore, the DRAM is equipped with an N-type well 16 (second well), that is formed on the semiconductor substrate 10 coming into contact with the side of the P well 14. A P well 17 (third well) is formed, coming into contact with the N well 16 and adjacent to the P well 14 through the intermediary of the N well 16. A MOS capacitor 206 is formed in the P well 17, where no transistor is formed to make effective use of dead space. The MOS capacitor 206 is possessed of an electrode 206a that faces opposite the top surface of the P well 17, through the intermediary of an insulating film 206b. The MOS capacitor 206 is located within a distance of 3 μm from a boundary between an N well constituted of the bottom N well 12 and an N well 13 and the P well 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having wells of different conductivity types.

[0002]

2. Description of the Related Art In recent years, semiconductor devices in which a large number of transistors are integrated have been used for various electric appliances such as workstations and personal computers. FIG. 12 is a sectional view showing a part of a conventional DRAM used as a main memory of a personal computer.

Referring to FIG. 12, a DRAM includes a P-type P well 2 and a P-type P well formed on a P-type silicon semiconductor substrate 1.
Includes 3 and N-type N-well 4. This DRAM also has an N-type N-well 5 formed around the side wall of P-well 2, and a P-type well.
An N-type bottom N well 6 formed below the well 2 is included. This DRAM further includes an N-channel MOS transistor 7 formed in the P-well 2, and an N-channel M transistor formed in the P-well 3.
P channel formed in OS transistor 8 and N well 4
Includes MOS transistor 9.

[0004]

Referring to FIG. 13, in this conventional DRAM, before forming P wells 2, 3 and N well 4, regions other than the region where bottom N well 6 is formed are formed. By masking with a photoresist RE, N-type ions are implanted from above the P-type well semiconductor substrate 1 to form a bottom N-well 6. However, since the boundary between the remaining portion of the photoresist RE and the removed portion, that is, the side wall of the photoresist RE has a tapered shape as shown in the figure, a part of the N-type ions is formed in the P well 3 later. Is also implanted near the surface of the region. If a transistor is formed in a portion where the N-type ions are implanted, the transistor does not have desired characteristics.Therefore, a dead space where no element is formed within 4 μm from the boundary of the bottom N well 6 is formed. Was.

An object of the present invention is to effectively utilize a dead space near a bottom N well. It is another object of the present invention to reduce power supply noise by using a capacitor formed in a dead space.

[0006]

A semiconductor device according to the present invention is formed of a first well of a first conductivity type, a first well surrounding the first well, and being in contact with a side portion and a bottom portion of the first well. A second well of a second conductivity type including a bottom well
And a third well of the first conductivity type, which is formed in contact with the second well and is adjacent to the first well with the second well interposed therebetween, and an insulating film on the upper surface of the third well. And a MOS capacitor located within 3 μm from the boundary between the second well and the third well.

A first well of a first conductivity type, a second well surrounding the first well and formed in contact with a side portion and a bottom portion of the first well, including a bottom well provided on the bottom portion.
A first well formed in contact with the second well of the conductivity type and the second well and adjacent to the first well with the second well interposed therebetween;
A conductive third well, an isolation insulator located at a boundary between the second well and the third well, and an electrode opposed to the upper surface of the third well via an insulating film and in contact with the isolation insulator. Is provided.

A memory cell including a memory transistor of the second conductivity type formed in the first well, a fourth well of the second conductivity type opposed to the second well across the third well, and , A peripheral circuit including a transistor of the first conductivity type formed in the fourth well.

Further, the peripheral circuit includes a sense amplifier having a transistor of the first conductivity type and a transistor of the second conductivity type formed in the first well.

Further, the peripheral circuit includes a word line driver having a transistor of the first conductivity type formed in the second well and a transistor of the second conductivity type formed in the first well. Things.

The first conductivity type is P-type, the second conductivity type is N-type, a power supply potential is applied to the fourth well, and a boosted potential higher than the power supply potential is applied to the second well. It is something that has been done.

Further, the semiconductor device further includes a sense amplifier and an operating potential line for supplying an operating potential to the sense amplifier, and an electrode of the MOS capacitor is connected to the operating potential line.

The first, second and third wells are
It is formed on a semiconductor substrate of a first conductivity type, and a substrate potential is applied to an electrode of the first conductivity type formed in a third well. In addition, the MOS capacitor is formed in the third well from the boundary between the second well and the third well.
It includes another electrode provided at a position separated by 2 μm or more.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, a DRAM (Dynamic Random Access Memory) according to an embodiment of the present invention
Will be described with reference to FIGS. 1 to 9. FIG. 1 is a schematic view of a DRAM. Referring to FIG. 1, the DRAM is a semiconductor chip CH.
Formed. DRAM has four sub memory cell arrays 100a,
A memory cell array including 100b, 100c and 100d is provided. The sub memory cell arrays 100a, 100b, 100c and 10
Each of 0d includes a plurality (32 in this embodiment) of memory cell blocks 110. Each of the memory cell blocks 110 includes a plurality (four in this embodiment) of sub-memory cell blocks 111. The DRAM includes a sense amplifier block 200 provided with the memory cell block 110 interposed therebetween.

Further, the DRAM has a sub memory cell block 11
It includes a sub-row decoder block 310 provided with 1 interposed therebetween. Furthermore, the DRAM has four sub-memory cell arrays 1
A main row decoder block 320 is provided corresponding to each of 00a, 100b, 100c and 100d. The main row decoder block 320 includes a plurality of main row decoders provided corresponding to the memory cell blocks 110, respectively.
Including 321. Furthermore, DRAM has four sub-memory cell arrays.
A column decoder block 410 is provided corresponding to each of 100a, 100b, 100c and 100d. Column decoder block 410 includes a plurality of column decoders 411 provided corresponding to sub memory cell blocks 111, respectively. These sense amplifier block 200, sub-row decoder block 310, main row decoder block 320, and column decoder block 410 are included in peripheral circuits.

FIG. 2 shows the correspondence between the memory cell block 110 and its peripheral circuits. Referring to FIG. 2, each sub memory cell block 111 has a plurality of (512 in this embodiment) bit line pairs 112 having bit lines 112a and 112b.
Is provided. The sense amplifier block 200, or amplifies the potential difference generated in the bit line pair 112, the bit lines 112a and 112b potential BL _i and _{/ BL i (i = 0,1,} ...) a bit line precharge the It has an amplification / precharge / equalize circuit 210 for precharging / equalizing the potential V _BL. The precharge potential _VBL is a potential (1/2) (V _CC + V _SS ) intermediate between the power supply potential V _CC and the ground potential V _SS . Ground potential V _SS
Is 0 V in this embodiment, and V _CC is higher than the ground potential and 1.5 V in this embodiment. The power supply potential and the ground potential are supplied as operating potentials for operating the DRAM.

The sense amplifier block 200 has N-channel MOS transistors 221 and 222 and has a bit line pair 112 in response to a bit line isolation signal BLI _j (j = 0, 1,...). From the amplification / precharge / equalization circuit 210. Further, sense amplifier block 200 has a pair of data bus lines 231 and 232 and includes a data bus 230 for transmitting data from the memory cell array. Furthermore, the sense amplifier block 200 outputs a column selection signal CSL _k (k = 0, 1,...)
And a data transfer circuit 240 for selectively connecting the bit line pair 112 and the data bus 230 in accordance with the data transfer condition. This data transfer circuit 240 includes N-channel MOS transistors 241 and 242
Having.

FIG. 3 is a schematic diagram showing the correspondence between the sub memory cell block 111 and peripheral circuits. Referring to FIG. 3, main word line 113 connected to main row decoder 321 and common to a plurality of (four in this embodiment) sub memory cell blocks 111 is arranged. A plurality (64 in this embodiment) of main word lines 113 are provided corresponding to one memory cell block 110. Main row decoder 3
21 selects one main word line 113 from 64 lines in response to the address signal, and a main word signal MWL _m (m = 1, 2,...) Applied to the selected main word line 113 To a high level.

Each of the sub memory cell blocks 111 includes a plurality of sub word lines 114. Focusing on one sub memory cell block 111, one main word line 113
Correspond to four sub-word lines 114. The sub-row decoder block 310 is provided corresponding to the sub-word line 114, and receives a main word signal MWL _m transmitted from the corresponding main word line 113 and a row decode signal X _n ⁺ (n = 0, 1) according to an address signal. , 2,3) (+ indicates a high potential V _PP higher than the power supply potential V _CC ), and a high potential V _PP (5 V in this embodiment) is applied to the corresponding sub-word line 114. Including a plurality of word line drivers 311. A plurality of sub-row decoders are provided corresponding to each of the main word lines 113, and a plurality (10 in this embodiment) of word line drivers corresponding to one main word line 113 are provided.
311 is included in one sub-row decoder.

FIG. 4 is a circuit diagram showing the sub-memory cell block 111 shown in FIGS. 2 and 3 and a part of peripheral circuits in more detail. Referring to FIG. 4, sub memory cell block 111 includes a plurality of memory cells 115 arranged in a plurality of rows and a plurality of columns. Each memory cell 115 includes a memory capacitor 1 for receiving a cell plate potential V _CP to one electrode
15a, the other electrode of the memory capacitor 115a and the bit line 112
a or 112b, and the gate is connected to sub-word line 1
14 and a memory transistor 115b composed of an N-channel MOS transistor. Main word line 113 and sub word line 114 are arranged extending in the row direction, and bit line pair 112 is arranged extending in the column direction. Sub word line 1
14 are arranged corresponding to the row of the memory cells 115 and are connected to the plurality of memory cells 115 in the corresponding row. Bit line pairs 112 are arranged corresponding to the columns of the memory cells, and are connected to memory cells 115 in the corresponding columns.

The peripheral circuits include a power supply line 201 to which the power supply potential V _CC is supplied, a power supply line 202 to which the ground potential V _SS is supplied,
It includes a common source line 203, a common source line 204, and a precharge potential line 205 transmitting bit line precharge potential _VBL . The peripheral circuit also uses the sense amplifier enable signal / P
According to SE _p (p = 0,1,2, ...), the common source line 203
And an N-channel MOS transistor 252 for discharging the common source line 204 to the ground potential V _SS in response to the P-channel MOS transistor 251 and the sense amplifier enable signal NSE _p for charging the _CC.

The peripheral circuit further includes an isolation gate circuit 220.
Amplifies the potential difference of the bit line pair 112 connected via
Power line potential V_CCTo the other potential
Earth potential V _SSSense amplifier 211 is included. sense
The amplifier 211 is cross-coupled and connected to the bit line 112a.
Or supply the potential of the higher bit line out of 112b to the power supply
Potential V_CCP-channel MOS transistor 211 for amplification
a, 211b, cross-coupled, and bit line 112a or
Is the ground potential of the bit line with the lower potential of 112b
V_SSN-channel MOS transistors 211c, 21
Has 1d. The sense amplifier 211 is included in the operating potential line.
Power supply potential V which is an operating potential from power supply lines 201 and 202_CC
And ground potential V_SSSupplied.

Further, the peripheral circuit includes a bit line precharge / equalize circuit 212 for equalizing / precharging the potentials of bit lines 112a and 112b according to a precharge signal PR. The bit line precharge / equalize circuit 212 responds to a precharge signal PR to generate a bit line 112a.
N-channel MOS for equalizing the potentials of 112 and 112b
Transistor 212a and the potential of bit lines 112a and 112b are set to the bit line precharge potential in accordance with precharge signal PR.
N-channel MOS transistor 212b for precharging the V _BL, and a 212c. The sense amplifier 211 and the bit line precharge / equalize circuit 212
It is included in the precharge / equalize circuit 210.

Further, the peripheral circuit includes a precharge signal.
A common source line precharge / equalize circuit 261 for equalizing / precharging the potentials of the common source lines 203 and 204 according to PR is included. The common source line precharge / equalize circuit 261 includes an N-channel MOS transistor 261a for equalizing the potential of the common source lines 203 and 204 according to the precharge signal PR, and the common source line 203 and N-channel MOS transistor 261b for precharging the 204 potential to the bit line precharge potential V _BL, and a 261 c.

FIG. 5 is a specific circuit diagram of the word line driver 311.
It is. Referring to FIG. 5, word line driver 311
Connected between the code signal line 310a and the sub word line 114
And the gate is connected to the potential MWL of the main word line 113._mReceiving
High potential V on the lock gate_PPP-channel MOS transistor
Including star 311a. In addition, the word line driver 311
Word line 114 and ground potential V_SSWith the ground node given
And the gate is connected to the potential MWL of the main word line 113._m
Receiving N channel MOS transistor 311b. further
The word line driver 311 is connected to the sub word line 114 and the ground.
Connected to the node, and the row decode signal X_n
⁺Inverted signal of / X_n(However, X_n ⁺As V_PP-V _SSAmplitude
And V_CC-V_SSN-channel MOS transistor receiving amplitude
Including the resistor 311c.

Next, the read / write operation of the DRAM will be described with reference to FIG. First, when the DRAM is in the standby state, the main row decoder 321 sets all the main word lines 113 to the boosted potential _VPP . Also,
The row decode signals X ₀ ⁺ -X ₃ ⁺ are all at a low level, and the inverted row decode signal / X _0- / X ₃ is at a high level. Therefore, the transistor 3 shown in FIG.
11c is conductive, the potential of all the sub-word line 114 is at the ground potential V _SS. Memory transistor 115b included in memory cell 115 receiving the potential of sub word line 114.
Is in a non-conductive state, and the memory cell 115 is in a state of holding data.

In the standby mode, the bit line isolation signal BL
All I _j are boosted potentials V _PP , and all bit line pairs 112 are connected to the corresponding sense amplifier 211 and bit line precharge / equalize circuit 212. Further, the precharge signal PR is at a high level. since going on, it receives this bit line precharge / equalization circuit 212 potential BL _i of the bit lines 112a and 112b, / BL _i are precharged and equalized to the bit line precharge potential V _BL and a common source Line precharge / equalize circuit 261
Is the precharge potential of the common source lines 203 and 204
Precharged and equalized to V _BL .

In the standby state, the sense amplifier enable signals / PSE _p and NSE _p are at the high level and the low level, respectively, so that the P-channel MOS transistor 251 and the N-channel MOS transistor 252 are in a non-conductive state. Since the potentials of the common source lines 203 and 204 are both at the bit line precharge potential _VBL , the sense amplifiers 211 are all inactivated. The column selection signals CSL _k are all at low level, and the column selection signals CSL _k
The N-channel MOS transistors 241 and 242 in the data transfer circuit 240 receiving the current are both non-conductive, and the bit line pair 112 and the data bus 230 are separated.

When an access (read / write operation) to the DRAM is requested, the DRAM enters an active state, and the precharge signal PR changes to a low level. In response, bit line precharge / equalize circuit 212
Suspends precharging and equalizing of bit lines 112a and 112b. The common source line precharge / equalize circuit 261 also interrupts the precharge and equalize of the common source lines 203 and 204. Further, the bit line isolation signal BLI _j corresponding to the memory cell block 110 selected by the address signal is maintained at the boosted potential V _PP, the bit line isolation signal BLI _j corresponding to the non-selected memory cell block 110 is in the low level Fall. In response to this, bit line pair 1 in unselected memory cell block 110
12 is separated from the sense amplifier 211 and the bit line precharge / equalize circuit 212 by the separation gate circuit 220.

Then, the selected main word line 113 (sub-memory cell arrays 100a, 100b, 100c and 1c) in the memory cell block 110 selected according to the address signal is output.
00d, memory cell blocks 110 are selected one by one, and the main word line 113 is selected from each selected memory block 110.
1 potential MWL _m of the present one by selected) is the ground potential V _SS from the boosted potential V _PP by the main row decoder 321. Also, a row decode signal selected according to the address signal
In the word line driver 311 in which X _n ⁺ is set to the boosted potential V _PP and the two inputs of the main word signal MWL _m and the row decode signal X _n ⁺ are both selected, N-channel MOS transistors 311 b and 311 c
Is nonconductive state, P channel MOS transistor 311a is turned, the potential SWL _q of the sub-word line 114 is selected,
It changes to the boosted potential _VPP .

Then, the memory transistors 115b in the plurality of memory cells 115 connected to each of the selected sub-word lines 114 become conductive, and the capacitors 115a
Between the other electrode and the bit line 112a or 112b, and the potential BL _i , / BL _{i of} the bit line 112a or 112b is changed to the high level or the low level stored in the capacitor 115a of the memory cell 115. slightly raised or lowered than the precharge potential V _BL in accordance with the data (Fig. 6
Shows a case where low-level data is stored.)

Thereafter, the selected memory cell block 11
When 0 sense amplifier enable signal NSE _p corresponding to becomes a high level, the N-channel MOS transistor 252 receiving a sense amplifier enable signal NSE _p is rendered conductive, the potential drop of the common source line 204 toward the ground potential V _SS by slightly potential towards lower potentials BL _i or / BL _i the ground potential V _SS of the N-channel MOS transistors 211c and the N-channel sense amplifier consisting 211d the bit line 112a or 112b in the sense amplifier 211 Lower towards.

Then, the selected memory cell block 11
When the sense amplifier enable signal / PSE _p corresponding to 0 goes low, the sense amplifier enable signal / PSE _p
The P-channel MOS transistor 251 receiving the P-channel MOS transistor 211a and 211b in the sense amplifier 211 is turned on by the potential of the common source line 203 rising toward the power supply potential V _CC. the potential BL _i or / BL _i of higher potential of the line 112a or 112b is increased toward the power supply potential V _CC.

After the slight potential difference generated in the bit line pair 112 is amplified by the sense amplifier 211,
Column selection signal CSL selected according to the address signal
_k (one column selection signal CSL _k is selected in each of the columns of the sub-memory block 111) becomes high level, and the data bus corresponding to the bit line pair 112 corresponding to the high level column selection signal CSL _k Data transfer circuit 240 to 230
And the potential difference of the bit line pair 112 amplified by the sense amplifier 211 is transmitted to the data bus 230. During a read operation (read), this data bus 230
Is amplified and read as read data. During a write operation (write), the data bus 23
A potential difference corresponding to the write data is given to 0, and a potential corresponding to the write data is given to the selected memory cell 115 via the bit line 112a or 112b.

[0035] When the read or write operation is completed, the potential SWL _q of the sub-word line 114 to a low level, the bit line isolation signal BLI _j is V _PP level, the column select signal CSL _k is the low level, the sense amplifier enable signal / PSE _p is the high level, the sense amplifier enable signal NSE _p is at the low level. Also, the precharge signal PR
Becomes high level, the bit line precharge / equalize circuit 212 which receives the precharge signal PR, potential BL _i of the bit line pair 112, / BL _i is precharged and equalized to the bit line precharge potential V _BL, pre the potential of the common source lines 203 and 204 are precharged and equalized to the bit line precharge potential V _BL by the common source line precharge / equalize circuit 261 for receiving a charge signal PR, the flow returns to the standby state.

FIG. 7 is a cross-sectional view taken along the row direction, schematically showing the vicinity of the boundary between the sub memory cell block 111 and the sub row decoder block 310. Referring to FIG. 7, the DRAM includes a P-type P well 11 formed on a P-type semiconductor substrate 10.
The DRAM includes an N-type bottom N-well 12 formed on a semiconductor substrate 10 in contact with the bottom of the P-well 11. Further, the DRAM includes an N-type N-well 13 formed on the semiconductor substrate 10 in contact with the side of the P-well 11. The bottom N well 12 and the N well 13 are electrically conductive, and integrally form an N well for separating the P well 11 from the semiconductor substrate 10. Also, the P well 11 has a P well
An electrode 11a composed of a P-type diffusion region for providing a back bias potential _VBB lower than the ground potential to 11 is provided.
Further, the N well 13 is provided with an electrode 13a formed of an N type diffusion region for applying a high potential _VPP to the bottom N well 12 and the N well 13. P well 11, bottom N well 12, and N well 13 constitute a so-called triple well structure. Further, an isolation insulator 10a is formed between the elements.

The memory transistor 115b in the memory cell 115 is formed in the P well 11. This memory transistor 115b has one and the other source / drain 115ba and 115bb formed of an N type diffusion region. Also,
The memory transistor 115b has a gate 115bc provided to face a region between the source / drain 115ba and 115bb of the P well 11 with a gate insulating film therebetween. The N-channel MOS transistor 3 in the word line driver 311
11b is formed in the same P well 11 as the memory transistor 115b. The N-channel MOS transistor 311b has a drain 311bb of N-type diffusion region to provide a source 311ba and sub word signal SWL _q a diffusion region of the N type which receives a ground potential V _SS. This drain 311bb
Connected to gate 115bc of memory transistor 115b.
The N-channel MOS transistor 311b has a gate 311bc provided to face a region between the source 311ba and the drain 311bb of the P well 11 with a gate insulating film interposed therebetween. This gate 311bc receives main word signal MWL _m .

Further, a P-channel MOS transistor 311 a in the word line driver 311 is formed in the N well 13. The P-channel MOS transistor 311a includes a source 311aa formed of a P-type diffusion region receiving the row decode signal X _n ⁺ and a P-type diffusion region,
It has a drain 311ab connected to the drain 311bb of 11b. Further, the P-channel MOS transistor 311a has a source 311aa and a drain 311ab of the N well 13 with a gate insulating film interposed therebetween.
And a gate 311ac provided opposite to a region sandwiched between the two. The gate 311ac receives the main word signal MWL _m. Although not shown in FIG. 7, the N-channel MOS transistor 311c of the word line driver 311 is also an N-channel MOS transistor.
It is formed in the P well 11 similarly to the MOS transistor 311b.

As described above, in the DRAM of the first embodiment, N-channel MOS transistors 311b and 311c forming word line driver 311 are both memory transistors 1111 and 311c.
The potential of the N well forming the bottom N well 12 and the N well 13 formed in the P well 11 where the 5b is formed and surrounding the P well 11 is the same as the back bias of the P channel MOS transistor 311a of the word line driver 311. as boosted potential V _PP, since the N-well for forming the P-channel MOS transistor 311a and a separately may not be provided constituting the N-well surrounding the P-well 11, along the bottom N-well 12 in the row direction is sub It is provided in common to the memory cell block 111 and the sub-row decoder block 310, and there is no break between the sub-memory cell blocks 111.

FIG. 8 is a cross-sectional view schematically showing the vicinity of the boundary between the memory cell block 110 and the sense amplifier block 200 along the column direction. Referring to FIG. 8, the DRAM includes P well 11, bottom N well 12, and N well 1 described with reference to FIG.
In addition to 3, the semiconductor device further includes a P-type P well 14 formed on the semiconductor substrate 10. The DRAM is formed on an N-type bottom N-well 15 formed on the semiconductor substrate 10 in contact with the bottom of the P-well 14.
Is provided. Further, the DRAM has a P-well 1 on a semiconductor substrate 10.
4 is provided with an N-type N-well 16 formed in contact with the side portion.
Furthermore, the DRAM is formed on the semiconductor substrate 10 in contact with the N well 13 and is adjacent to the P well 11 via the N well 13.
A P well 17 is provided. Bottom N-wells 12 and 15 are formed first of these wells, then N-wells 13 and 1
After 6 is formed, P-wells 11, 14 and 17 are formed.

The bottom N well 15 and the N well 16 are electrically conductive, and integrally form an N well for separating the P well 14 from the semiconductor substrate 10. Also, P
The well 14 is provided with an electrode 14a formed of a P-type diffusion region for applying a back bias potential _VBB lower than the ground potential to the P well 14. In addition, the N well 16 has a bottom
An electrode 16a composed of an N-type diffusion region for applying power supply potential V _CC to N well 15 and N well 16 is provided. P well 14, bottom N well 15 and N well 16 constitute a so-called triple well structure.

The P well 17 contacts the N well 16 and the N well 16
Also, it is formed adjacent to the P well 14 via a hole. Since the N-well composed of the bottom N-well 12 and the N-well 13 and the N-well composed of the bottom N-well 15 and the N-well 16 have different applied potentials, 4 μm is provided between the N wells. That is, the P-well 17 has a width of 4 μm. Then, in the same manner as described with reference to FIG. 13, the region where the P well 17 is formed is masked with a photoresist, and N-type ions are implanted from above to form the bottom N wells 12 and 15. Since the photoresist has a tapered shape, N-type ions are implanted near the upper surface of the P well 17. If a transistor is formed in this P well 17, the threshold value thereof will fluctuate in the process. Therefore, forming a transistor in this P well 17 is avoided.

In this DRAM, a MOS capacitor 206 is formed in the P-well 17 where no transistor is formed, and dead space is effectively used. N near the upper surface of the P well 17
Even if the type ions are implanted, it is not enough to cancel the P-type polarity of the P-well 17, so that even if the threshold value fluctuates, the function as a capacitor is sufficiently exhibited. MOS capacitor 206 includes an electrode 206a facing the upper surface of P well 17 with a gate insulating film 206b interposed therebetween. Electrode 206a
Are connected to a power supply line 201 for supplying a power supply potential V _CC to the sense amplifier 211.

The MOS capacitor 206 is located within 3 μm from the boundary between the N well composed of the bottom N well 12 and the N well 13 and the P well 17. Further, MOS capacitor 206 is located within 3 μm from the boundary between N well composed of bottom N well 15 and N well 16 and P well 17. Here, the position within 3 μm means that the MOS capacitor 2
This means that at least a part of the portion facing the electrode 206a of 06 with the insulating film 206b of the P well 17 is within 3 μm. The electrode 206a is in contact with the isolation insulator 10a located at the boundary between the N well 13 and the P well 17. Further, the electrode 206a is also in contact with the isolation insulator 10a located at the boundary between the N well 16 and the P well 17. Also, MOS capacitors
206 is located within 3 μm from the boundary of bottom N-wells 12 and 15.

The N-channel MOS transistor 211c in the sense amplifier 211 is formed in the P well 14. This N-channel MOS transistor 211c has a source 211ca formed of an N-type diffusion region and a drain 211cb formed of an N-type diffusion region.
Having. The drain 211cb is connected to the potential B of the bit line 112a.
Receive the L _i. Source 211ca is more MOS than drain 211cb
It is located near the capacitor 206. Also, N-channel MOS
The transistor 211c is connected to the P-well 14 via the gate insulating film.
The gate 211cc is provided to face a region sandwiched between the source 211ca and the drain 211cb. This gate 211cc is subject to potential / BL _i of the bit line 112b.

Further, a P-channel MOS transistor 211a in the sense amplifier 211 is formed in the N well 16. P
The channel MOS transistor 211a includes a source 211aa formed of a P-type diffusion region and a drain 211ab formed of a P-type diffusion region and connected to the drain 211cb of the N-channel MOS transistor 211c. Also, the P-channel MOS transistor 211a is connected to the source 211
It has a gate 211ac provided opposite to a region sandwiched between aa and the drain 211ab. This gate 211ac is connected to the gate 211cc of the N-channel MOS transistor 211c.

Although not shown in FIG. 8, the N-channel MOS transistor 252 and the N
Channel MOS transistors 221, 222, N of sense amplifier 211
The channel MOS transistor 211d, the N-channel MOS transistors 212a, 212b, 212c in the bit line precharge / equalize circuit 212 and the N included in the data transfer circuit 240
The channel MOS transistors 241 and 242 are formed in the same P well 14 as the N channel MOS transistor 211c. Furthermore, P
Channel MOS transistor 251 and sense amplifier 211 P
The channel MOS transistor 211b is formed in the same N well 16 as the P channel MOS transistor 211a.

FIG. 9 is a schematic view of the vicinity of the MOS capacitor 206 shown in FIG. 8, (A) is a top view, (B) is a sectional view of the BB plane of (A), and (C) is ( A) shows a cross-sectional view of the CC plane. Referring to FIG. 9, an electrode 17a formed of a P-type diffusion region for applying a substrate potential (ground potential V _SS in this embodiment) to P well 17 is provided.
Is provided. Another electrode 206c of the MOS capacitor 206 formed of an N-type diffusion region is provided in the P well 17. The electrode 206c, is given a ground potential V _SS. Also, electrode 1
The substrate potential is applied to 7a, and this substrate potential is
Through the semiconductor substrate 10. The electrode 206a is an electrode
To apply potential to 17a and 206c, electrodes 17a and 20
It has an opening on 6c.

As described above, in the DRAM of the first embodiment, the dead space can be effectively used by forming the MOS capacitor 206 in the P well 17 where no transistor is formed. In addition, P where no transistor is formed
A MOS capacitor 206 is formed in the well 17 and the sense amplifier 21 is formed.
Since it was connected to the power supply line 201 that supplies the power supply potential V _CC to 1,
Without increasing the layout area, the sense amplifier 21
Power line 201 noise (1.5V
Thus, a semiconductor device capable of performing a stable sensing operation can be obtained. Further, the ground potential is applied to the sense amplifier 211 on the electrode 206c of the MOS capacitor 206.
By connecting the power supply line 202 that supplies V _SS , noise (0%) of the power supply line 202 generated when the sense amplifier 211 is activated is generated.
V) can also be suppressed.

Incidentally, as the semiconductor substrate 10, it is preferable to use an epi substrate having a low resistance value. If the substrate has a low resistance value, the substrate potential is firmly fixed to the ground potential V _SS , so that the substrate potential does not easily fluctuate, and the fluctuation occurring on the substrate is supplied to the sense amplifier 211 via the MOS capacitor 206 by the power supply potential V _CC. The fluctuation transmitted to the power supply line 201 that gives the power can be reduced.

Embodiment 2 Hereinafter, a DRAM according to another embodiment of the present invention will be described with reference to FIG. The DRAM of the second embodiment is different from the DRAM of the first embodiment in the well configuration of the sense amplifier block 200. This difference will be described. FIG. 10 is a cross-sectional view schematically showing the vicinity of the boundary between the memory cell block 110 and the sense amplifier block 200 along the column direction. FIG.
8, the DRAM of the second embodiment is different from the DRAM of the first embodiment shown in FIG. 8 in that the N-channel MOS transistor 211c included in the sense amplifier 211 has the same P-well as the memory transistor 115b. 11 is different. Therefore, no P well 14 is formed and no bottom N well 15 is formed. N well 16 and P well 17
Constitutes a so-called twin well structure.

Since the N-well constituted by the bottom N-well 12 and the N-well 13 and the N-well 16 have different applied potentials, these N-wells are prevented from being short-circuited.
3.5 μm intervals are provided between the wells. That is, the P well 17 has a width of 3.5 μm. And
Similar to the DRAM shown in FIG. 8, a MOS capacitor 206 is formed in a P-well 17 where no transistor is formed, to effectively use a dead space. MOS capacitor 206 is located within 3 μm from the boundary between N well composed of bottom N well 12 and N well 13 and P well 17. Also,
The electrode 206a contacts the isolation insulator 10a located at the boundary between the N well 13 and the P well 17. MOS capacitor 206 is located within 3 μm from the boundary of bottom N well 12. N-channel MOS
The source 211ca of the transistor 211c is closer to the MOS capacitor 206 than the drain 211cb. MOS capacitor 2
The electrode 206c included in the electrode 206a is separated from the N well by 2 μm or more to suppress a leak current between the N well and the N well formed by the bottom N well 12 and the N well 13.
Is provided at a position facing the N well 13 with the.

Although not shown in FIG. 10, N channel MOS transistor 252, N channel MOS transistors 221 and 222 included in isolation gate circuit 220, and sense amplifier 211
The N channel MOS transistor 211d, the N channel MOS transistors 212a, 212b, 212c in the bit line precharge / equalize circuit 212 and the N channel MOS transistors 241 and 242 included in the data transfer circuit 240 are N channel MOS transistors.
It is formed in the P well 11 like the transistor 211c. Further, the P-channel MOS transistor 251 and the P-channel MOS transistor 211b of the sense amplifier 211
It is formed in the same N well 16 as the S transistor 211a.

As described above, in the DRAM of the second embodiment, similarly to the DRAM of the first embodiment, the MOS capacitor 206 is formed in the P well 17 where no transistor is formed, and the dead space is effectively used. be able to. The MOS capacitor 20 is placed in the P well 17 where no transistor is formed.
6 is formed and connected to the power supply line 201 for supplying the power supply potential V _CC to the sense amplifier 211, so that the noise of the power supply line 201 generated when the sense amplifier 211 is activated (1.5 V) can be suppressed, and a semiconductor device capable of performing a stable sensing operation can be obtained. Further, the electrode 206c of the MOS capacitor 206
Power supply line 20 that supplies the ground potential V _SS to the sense amplifier 211.
By connecting 2, it is possible to suppress noise (floating from 0 V) of the power supply line 202 generated when the sense amplifier 211 is activated.

Further, the N-channel MOS transistors 211c and 211d included in the sense amplifier 211 are formed in the same P-well 11 as the memory cell transistor 115b, and the N-well 16 in which the P-channel MOS transistors 211a and 211b are formed is a twin well. Due to the structure, the interval between the bottom N well and the twin N well can be reduced to 3.5 μm as compared with the interval between the bottom N wells of 4 μm. That is, the bottom N
At the time of ion implantation of the well, since the thickness of the photoresist must be thicker than the photoresist used at the time of ion implantation of the N well 16, the interval between the bottom N wells must be large. It is.

Embodiment 3 Hereinafter, a DRAM according to another embodiment of the present invention will be described with reference to FIG. The DRAM according to the third embodiment is different from the DRAM according to the first or second embodiment in the structure of the N well composed of the bottom N well 12 and the N well 13. This difference will be described. FIG. 11 is a schematic cross-sectional view of the vicinity of the boundary between the N well and the P well 17 along the column direction. Referring to FIG. 11, the DRAM of the third embodiment is different from the DRAM of the first or second embodiment shown in FIG. 8 or FIG.
The difference is that N well 13 surrounding 1 is tapered inward. Then, the electrode 206a of the MOS capacitor 206 and the P well 1
The portion where 7 is opposed across the insulating film 206b extends to the boundary of the bottom N well 12.

Also in the third embodiment, the MOS capacitor 206
Is located within 3 μm from the boundary between the N well composed of the bottom N well 12 and the N well 13 and the P well 17.
MOS capacitor 206 is located within 3 μm from the boundary of N well 13. Further, the MOS capacitor 206 is located within 3 μm from the boundary of the bottom N well 12, and particularly in the third embodiment, 0 μm from the boundary of the bottom N well 12.
It is located at. Embodiment 1 or 2
Similarly, the electrode 206a contacts the isolation insulator 10a located at the boundary between the N well 13 and the P well 17.

As described above, in the DRAM of the third embodiment, the boundary between N well 13 and P well 17 is moved to the inside of N well 13, so that the area of MOS capacitor 206 can be increased, and Not only can the capacity of the 206 be increased, but also the tolerance of photomask shift (mask shift margin) in the process of manufacturing the bottom N-well 12 and N-well 13 can be increased. That is, the gap between the bottom N well 12 and the N well 13 due to the shift of the photomask and the short circuit between the P well 11 and the P type semiconductor substrate 10 can be suppressed. Also, in the third embodiment, the same effect as in the first or second embodiment can be obtained.

Embodiment 4 FIG. Hereinafter, a DRAM according to another embodiment of the present invention will be described with reference to FIG. The DRAM of the fourth embodiment is different from the DRAM of the first embodiment in that the electrode 206c included in the MOS capacitor 206 is at least 2 μm from the N well composed of the bottom N well 12 and the N well 13 and This is provided at a position separated from the N well constituted by the bottom N well 15 and the N well 16 by 2 μm or more to suppress a leak current flowing between the electrode 206c and the N wells. This difference will be described.

Referring to FIG. 14A, MOS capacitor 206
The electrode 206c included in is located at a substantially central portion of the electrode 206a.
It is formed in the P well 17. The structure viewed from the top surface of the electrode 206c may be a structure localized near the contact hole with the ground potential V _SS and arranged at appropriate intervals as shown in FIG. As shown in C), a structure that is continuously arranged along the direction in which the MOS capacitor 206 extends may be used.

Embodiment 5 Hereinafter, a DRAM according to another embodiment of the present invention will be described with reference to FIGS. In the first to fourth embodiments of the present invention, the N well 13
_Applied to the word line driver 311
Since the P-channel MOS transistor 311a is formed in the N well 13, there is no break in the bottom N well 12 along the row direction, and a dead space occurs along the row direction as in the direction along the column direction. Did not. With the same idea, in the fifth embodiment, as shown in FIG.
Is supplied with the power supply potential V _CC instead of the boosted potential V _PP , and the P-channel MOS transistor included in the sense amplifier block 200 is formed in the N well 13 so that the bottom N well 12 is not cut along the column direction. I have.

However, P included in word line driver 311
Channel MOS transistor 311a is another fed a high potential V _PP
Since it must be formed in the N-well, this time, as shown in FIG.
There is a break in In the fifth embodiment, the dead space along the column direction as in the first to fourth embodiments is eliminated, but a dead space is generated along the row direction instead.
To make effective use of dead space.

In the first to fourth embodiments, the bottom
The boosted potential _VPP was applied to the N well 12 and the N well 13. The bottom N well 12 and the N well 13 surround the P well 11 in which the memory cell block 110 is formed. Figure 1
Referring to, since the area occupied by memory cell block 110 in semiconductor chip CH is large, the area occupied by P well 11 is also large. Therefore, P well 11 and bottom N well 12
Also, the capacitance between the N well 13 and the N well 13 is large, and the boosted potential V _PP is applied to this capacitance to stabilize the boosted potential V _PP . In the fifth embodiment, since the applied power supply voltage V _CC instead of boosted potential V _PP to the bottom N-well 12 and N well 13, the capacitance associated with the boosted potential V _PP is reduced. To compensate for this, in the fifth embodiment, the boosted potential is applied to the electrode 206a of the MOS capacitor 206.
V _PP is given.

[0064] In the case, had connected the electrode 206a of the 4 in the MOS transistor 206 from the first embodiment to the power supply line 201, the better the stabilization of the boosted potential V _PP has priority over the stabilization of the power supply line 201 Is the same as that of the fifth embodiment
Similarly, the boosted potential _VPP may be connected. Conversely, although giving boosted potential V _PP to the electrode 206a of the MOS transistor 206 in the fifth embodiment, the power supply line if more stabilization of the power supply line 201 has priority in place of the boosted potential V _{P P} 201 May be connected.

The gate insulating film 206b of the MOS transistor 206 according to the first to fifth embodiments is
The electrode 206 is formed simultaneously with the gate insulating film of b.
be given a boosted potential V _PP to a is in the range of withstand voltage of the gate insulating film 206 b. If this capacitor 206 is
Of the of the same structure as the memory capacitor 115a, since the memory capacitor 115a does not assume that only up to a voltage of V _CC / 2 at most is applied, applying a boosted potential V _PP capacitor dielectric film is broken Could be done.

[0066]

As described above, according to the present invention, since the capacitor is provided near the boundary between the third well and the second well including the bottom well, the region near the boundary is effectively utilized. This has the effect.

Further, since the capacitor is connected to the operating potential line of the sense amplifier, a stable operating potential can be supplied to the sense amplifier without increasing the layout area.

Further, since the other electrode of the capacitor is separated from the second well by 2 μm or more, there is an effect that a leak current generated between this electrode and the second well can be suppressed.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a DRAM chip according to a first embodiment of the present invention;

FIG. 2 is a simplified circuit diagram of the DRAM according to the first embodiment of the present invention;

FIG. 3 is a simplified circuit diagram showing a correspondence relationship between main and sub row decoders according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a sub memory cell block and peripheral circuits according to the first embodiment of the present invention;

FIG. 5 is a circuit diagram of the word line driver according to the first embodiment of the present invention.

FIG. 6 is a timing chart showing an access operation of the DRAM according to the first embodiment of the present invention;

FIG. 7 is a schematic sectional view along a row direction of the DRAM according to the first embodiment of the present invention;

FIG. 8 is a schematic sectional view along a column direction of the DRAM according to the first embodiment of the present invention;

FIG. 9 is a diagram showing an upper surface and a cross section near a capacitor according to the first embodiment of the present invention;

FIG. 10 is a schematic sectional view along a column direction of a DRAM according to a second embodiment of the present invention;

FIG. 11 is a schematic sectional view along a column direction of a DRAM according to a third embodiment of the present invention;

FIG. 12 is a schematic sectional view of a conventional DRAM.

FIG. 13 is a cross-sectional view showing how a conventional DRAM forms a bottom N well.

FIG. 14 is a diagram showing a cross section and a top surface near a capacitor according to a fourth embodiment of the present invention.

FIG. 15 is a schematic sectional view taken along the column direction of a DRAM according to a fifth embodiment of the present invention;

FIG. 16 is a schematic sectional view taken along the row direction of a DRAM according to a fifth embodiment of the present invention;

[Explanation of symbols]

10 Semiconductor substrate, 10a Isolation insulator 11 P well, 12 Bottom N well, 13 N well 16 N well, 17 P well, 17a electrode 115 Memory cell, 115b Memory transistor 202 Power line 206 Capacitor, 206a electrode, 206b Gate insulating film , 206c electrode 211 sense amplifier, 211a P-channel MOS transistor 211c N-channel MOS transistor 311 word line driver, 311a P-channel MOS transistor 311b N-channel MOS transistor

Claims (9)

[Claims] A first well of a first conductivity type, including a bottom well formed around the first well, in contact with a side and a bottom of the first well, and provided at the bottom. A second well of a second conductivity type, a third well of a first conductivity type formed in contact with the second well and adjacent to the first well with the second well interposed therebetween;
And an electrode facing the upper surface of the third well with an insulating film interposed therebetween, wherein the second well and the third
Semiconductor device having a MOS capacitor located within 3 μm from the boundary of the well. 2. A first well of a first conductivity type, including a bottom well formed around the first well, in contact with a side and a bottom of the first well, and provided on the bottom. A second well of a second conductivity type, a third well of a first conductivity type formed in contact with the second well and adjacent to the first well with the second well interposed therebetween;
A well, an isolation insulator located at a boundary between the second well and the third well, and an electrode opposed to an upper surface of the third well via an insulating film and in contact with the isolation insulator. Semiconductor device with MOS capacitor. 3. A memory cell including a memory transistor of a second conductivity type formed in the first well, a fourth of a second conductivity type opposed to the second well with the third well interposed therebetween. 3. The semiconductor device according to claim 1, further comprising a well and a peripheral circuit including a transistor of a first conductivity type formed in said fourth well. 4. The semiconductor device according to claim 3, wherein said peripheral circuit includes a sense amplifier having said transistor of a first conductivity type and a transistor of a second conductivity type formed in said first well. 5. The peripheral circuit includes a word line driver having a first conductivity type transistor formed in the second well and a second conductivity type transistor formed in the first well. The semiconductor device according to claim 3. 6. The first conductivity type is P-type, the second conductivity type is N-type, a power supply potential is applied to the fourth well, and a boost voltage higher than the power supply potential is applied to the second well. 4. The semiconductor device according to claim 3, wherein a potential is applied. 7. The semiconductor device according to claim 1, further comprising a sense amplifier, and an operating potential line for supplying an operating potential to the sense amplifier, wherein the electrode of the MOS capacitor is connected to the operating potential line. . 8. The first, second, and third wells include:
3. The semiconductor device according to claim 1, wherein a substrate potential is applied to an electrode of the first conductivity type formed on the semiconductor substrate of the first conductivity type and formed in the third well. 9. The MOS capacitor according to claim 1, further comprising another electrode formed in the third well and provided at a position separated from the boundary between the second well and the third well by at least 2 μm. 3. The semiconductor device according to 2.