JPH07307443A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent latchup caused by the coupling of internal parastic capacity just after the power is turned on, in a semiconductor device of CMOS structure provided with a self substrate bias generation circuit. CONSTITUTION:A P-well 6 is provided with a P-type diffusion area 4 whose impurity concentration is higher than that of P-well, a reverse bias supply terminal Vbb that is formed in the area 4 and is electrically connected with a self substrate bias generation circuit, and a reference voltage supply terminal Vss that is formed in the P-well and is also formed on an MOS type capacitor 10, that is comprised of an insulation film 8 formed on the surface of a semiconductor substrate 20 and an electrode 16 on the film 8, and the electrode 16. The MOS type capacitor is constructed within a well to which a reverse bias of the semiconductor device with CMOS structure provided with a self substrate bias generation circuit is to be applied and an external power supply is fed to the MOS type capacitor, thereby suppressing the variation of well potential at the time when the power supply is turned on and preventing the generation of latchup as a result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a self-substrate bias generating circuit therein, and provides a reverse bias to a well region formed inside a semiconductor substrate by this circuit.
The present invention relates to a semiconductor device having a structure.

[0002]

2. Description of the Related Art In a semiconductor device having a CMOS structure, it is known that when the terminal voltage exceeds a certain value, a latch-up phenomenon occurs in which the entire semiconductor device is fixed in a low impedance state. That is, as shown in FIG. 8, when MOS transistors are formed in the P well and the N well, respectively, a parasitic PNPN thyristor is formed here. In this figure, a field oxide film 7 is formed on the main surface of a semiconductor substrate 20 such as silicon, and an N well 5 and a P well 6 are formed in the surface region of the same main surface. A gate electrode 9 made of polysilicon or the like is formed in the P well 6 via a gate insulating film 8 made of a silicon oxide film or the like. Then, N ⁺ diffusion regions 3 are formed on both sides of the gate electrode 9, and these become the source / drain regions of the NMOS transistor formed in this well. In addition, a P ⁺ diffusion region 4 serving as an electrode lead-out region is formed in the P well 6, and a terminal for applying a predetermined potential Vbb to this electrode is provided. On the other hand, in the N well 5, a gate electrode 11 made of polysilicon or the like is formed via a gate insulating film 8 made of a silicon oxide film or the like. Then, P ⁺ diffusion regions 2 are formed on both sides of the gate electrode 11, which serve as the source / drain regions of the PMOS transistor formed in this well. Further, the N well 5 is formed with an N ⁺ diffusion region 1 serving as an electrode lead-out region, and a terminal for supplying a positive power supply Vpp to this electrode is provided.

The equivalent circuit is as shown in FIG.
In the cross-sectional structure shown in FIG. 8, a thyristor structure including a parasitic bipolar transistor exists between the positive power supply node Vdd and the reference power supply node Vss. The PNP type bipolar transistor of Tr1 of FIG. 9 is the P ⁺ diffusion region 2 of the N well 5 of FIG.
Is an emitter, the N well 5 is a base, and the P well 6 is a collector. The NPN type bipolar transistor of Tr2 uses the N ⁺ diffusion region 3 as an emitter, the P well 6 as a base, and the N well 5 as a collector. The electrode extraction region for applying a voltage to the N-well 5 is N ⁺ diffusion region 1, between the N-well 5 and the N ⁺ diffusion region 1 parasitic resistance R1 exists.
Similarly an electrode P ⁺ diffusion region 4 for applying a voltage to the P well 6, the parasitic resistance R2 exists between the P well 6 and the P ⁺ diffusion region 4.

In this circuit, the Vss terminal is used as a reference potential, and the Vdd terminal and the Vpp terminal are positive power supplies, for example, + 5.0V.
Now, let us consider the operation when a voltage is applied and an arbitrary potential is applied to the Vbb terminal. When 0V is applied to the Vbb terminal, Tr1
Since both Tr2 and Tr2 are cut off, no current flows in the circuit. However, when the potential of the Vbb terminal exceeds the junction potential between the base and emitter of Tr2 and the base current Ib2 flows through Tr2, the collector current Ic2 amplified by Tr2 flows and a potential difference is generated across the resistor R2. To do. When a base current Ib1 is generated in Tr1 due to the potential difference across R1, a collector current Ic1 amplified by Tr1 flows and a potential difference occurs across resistor R2. After that, regardless of the potential at Vbb terminal, Vdd terminal is generated. And V
A latch-up phenomenon occurs in which a large current continues to flow between the ss terminals. This latch-up phenomenon continues as long as power is supplied between the Vdd terminal and the Vss terminal, and it is difficult to cancel it until the power supply is stopped. To avoid this phenomenon,
Generally, in a semiconductor device having a CMOS structure, the P well is connected to Vss.
Used with the N-well biased to Vdd at the same time.

However, the parasitic capacitance of the diffusion layer necessary for forming an active element such as a MOS transistor in the well to the well or the substrate is a problem for high-speed operation of the semiconductor device. In the case of the one-sided staircase junction, the relationship between the junction capacitance Cj and the reverse bias voltage Vr is represented by 1 / Cj ² = A (Vr + φB) (1). Here, A is a coefficient including variables of relative permittivity and impurity density, and φB is a diffusion voltage. FIG. 10 shows the CV characteristic of the junction capacitance. As shown by the equation (1), when the reverse bias value applied to the junction decreases, the capacitance per junction per unit area increases. For example, in the case of the P well, the potential of the N ⁺ diffusion region is Vdd level and Vss.
Varies between levels. Therefore, when the P well is biased to Vss, the parasitic capacitance of the N ⁺ diffusion region portion of each node operates in the voltage region where the capacitance value is maximum. On the other hand, in order to reduce the parasitic capacitance of the diffusion region wiring portion in the well, a reverse bias may be actively applied to the well. If a larger reverse bias is applied to the well, it is possible to operate by avoiding the voltage region where the parasitic capacitance value is maximum. Therefore, it becomes possible to operate the device under less parasitic capacitance,
As a result, higher speed operation can be obtained.

The reverse bias power supply applied to the well is not supplied externally, but a self-substrate bias generation circuit is mounted inside the semiconductor device, and the reverse bias power supply Vbb is supplied to the P well by this circuit, for example, in SRAM. There is such a semiconductor device. By sharing the power supply to the self-substrate bias generation circuit with the power supply Vdd of other circuits in the semiconductor device, it is possible to obtain a high-speed circuit operation in which the parasitic capacitance is suppressed by supplying only a single power supply Vdd. It becomes possible.
FIG. 6 shows an example of a self-substrate bias generating circuit for applying a reverse bias to the P well. As shown in the figure, the self-substrate bias generation circuit is constituted by, for example, a ring oscillator circuit, a coupling capacitor, and a pumping circuit. After the power is turned on, the ring oscillator circuit first operates to output a rectangular wave. Coupling to the rising edge of the rectangular wave, the pumping circuit accumulates negative charges on the capacitor, and then coupling to the falling edge of the rectangular wave, and the pumping circuit discharges the negative charges stored in the capacitor to the output terminal. By repeating this operation, the self-bias circuit keeps the internal power supply terminal Vbb at a negative potential and applies a reverse bias to the P well.

[0007]

The operation of the semiconductor device having the CMOS structure when the power is turned on will be described below. As the semiconductor device, one in which the self-substrate bias generating circuit described above is mounted and a single power source is supplied between the positive power source terminal Vdd and the reference power source terminal Vss is used. First, it is assumed that Vdd is not sufficiently applied immediately after the power is turned on, for example, Vdd ≦ VthN and Vdd ≦ | VthP |. VthN and VthP are threshold voltages of the NMOS transistor and the PMOS transistor, respectively. At this point, the supplied power supply Vdd is below the Vth of each MOS transistor, so that each transistor cannot be turned on to its gate. Therefore CMO
The S logic circuit does not operate, and at the same time, the MOS transistor at the output end of the self-substrate bias generating circuit is in the off state, that is, the P well is in the floating state.
In this state, the potential of the P well is determined by the ratio of the parasitic capacitance between the power supply wiring and each node.

Now, the parasitic capacitance between each power source and the well will be described. FIG. 7 summarizes the relationship between each power source and the parasitic capacitance between wells. Since Vdd is supplied to the N well, if the capacitance between the same potential and the capacitance between Vdd and Vss are excluded,
The main parasitic capacitances are concentrated into three capacitances: a parasitic capacitance C1 between the Vdd node and the P well, a parasitic capacitance C2 between the N well and the P well, and a parasitic capacitance C3 between the P well and the Vss node. C1 is an N biased to the Vdd terminal in the P-well
Mainly the junction capacitance with the ⁺ diffusion region and the parallel plate capacitance between the Pdd and the metal wiring of the Vdd terminal in the P well. C2
Is a junction capacitance between the P well and the N well, a capacitance obtained by connecting the junction capacitance of the P ⁺ diffusion region and the junction capacitance of the N ⁺ diffusion region on the output node side of the logic circuit in series, and the PMOS on the input node side of the logic circuit. Parasitic capacitance of gate of transistor and NM
The main capacitance is the parasitic capacitance of the gate of the OS transistor connected in series. C3 is mainly the junction capacitance of the N ⁺ diffusion region biased to Vss in the P well.

Therefore, the potential V (P well) of the P well immediately after the power is turned on is V (P well) = Vdd × ((C1 + C2) / (C1 + C2 + C3)) (2) ) Is required. In other words, (C1 + C2) and C3
Ratio determines the potential of the P well immediately after the power is turned on. Next, the operation at the time when the power supply voltage gradually rises and the logic circuits and the like in the semiconductor device start operating will be described. The self-substrate bias generation circuit also starts operating, and the ring oscillator circuit outputs a rectangular wave. However, if the potential of Vdd is insufficient, the amplitude of the output of the ring oscillator circuit is small, and the amount of negative charges discharged from the pumping circuit to the P well is also small. Therefore, the potential of the P well continues to rise until the power supplied from the internal power supply Vbb suppresses the potential rise of the P well due to the parasitic capacitance. And
If the potential of the P well exceeds the junction potential between the N ⁺ diffusion regions biased to the Vss terminal, the semiconductor device will be in a latch-up state. The present invention has been made under the circumstances as described above, and is provided with a self-substrate bias generation circuit and a CMOS.
It is an object of the present invention to prevent the occurrence of latch-up in a semiconductor device having a structure due to coupling of internal parasitic capacitance immediately after power is turned on.

[0010]

A semiconductor device according to the present invention includes a semiconductor substrate on which a self-substrate bias generating circuit is formed, a P well formed on the semiconductor substrate and having an N-type MOS transistor, and the semiconductor substrate. Formed on P
Type MOS transistor and a P well region formed in the P well region and having a higher impurity concentration than the P well region, and in the P type diffusion region and electrically connected to the self substrate bias generation circuit. A reverse bias supply terminal connected to the MOS transistor, a MOS type capacitor formed of an insulating film formed in the P well region and formed on the surface of the semiconductor substrate, and an electrode formed on the insulating film; The first feature is that the electrode is provided with a reference voltage supply terminal formed on the electrode. Also, a semiconductor substrate on which a self-substrate bias generation circuit is formed, a P well formed on the semiconductor substrate and having an N-type MOS transistor, and an N well formed on the semiconductor substrate and having a P-type MOS transistor. Formed in the N well region,
An N-type diffusion region having an impurity concentration higher than that of the N-well, a reverse bias supply terminal formed in the N-type diffusion region and electrically connected to the self-substrate bias generating circuit, and formed in the N-well region, A second feature is that it is provided with a MOS capacitor having an insulating film formed on the surface of the semiconductor substrate and an electrode formed on the insulating film, and a power supply voltage supply terminal formed on the electrode. I am trying.

Further, a semiconductor substrate on which the first and second self-substrate bias generating circuits are formed, a P well formed on the semiconductor substrate and having an N-type MOS transistor, and formed on the semiconductor substrate, An N well having a P type MOS transistor and formed in the P well region,
A P-type diffusion region having an impurity concentration higher than that of the P-well, a first reverse bias supply terminal formed in the P-type diffusion region and electrically connected to the first self-substrate bias generation circuit, and the P-type diffusion region. A first MOS type capacitor formed in a well region and including an insulating film formed on the surface of the semiconductor substrate and an electrode formed on the insulating film, and formed on an electrode of the first MOS capacitor The reference voltage supply terminal, the N-type diffusion region formed in the N-well region and having an impurity concentration higher than that of the N-well, and the N-type diffusion region, and electrically connected to the second self-substrate bias generation circuit. Second MOS type capacitor having a reverse bias supply terminal electrically connected thereto, an insulating film formed in the N well region and formed on the surface of the semiconductor substrate, and an electrode formed on the insulating film. And Sita, and that and a second MOS-type electrode formed power supply voltage supply terminal of the capacitor and the third feature.

A semiconductor substrate on which a self-substrate bias generating circuit is formed, and N formed on the semiconductor substrate.
Type P-well having a P-type MOS transistor, an N-well having a P-type MOS transistor formed on the semiconductor substrate, and a first P-well having a P-type MOS transistor formed on the semiconductor substrate.
A P-type diffusion region having an impurity concentration higher than that of the well;
A reverse bias supply terminal formed in the P type diffusion region in the P well and electrically connected to the self substrate bias generating circuit, an insulating film formed on the surface of the semiconductor substrate, and an insulating film formed on the insulating film. MO composed of formed electrodes
An S-type capacitor, a second P-well having a high-concentration P-type diffusion region to which a reverse bias supplied from the MOS type capacitor and the self-substrate bias generating circuit is applied, and an electrode of the MOS-type capacitor. The fourth feature is that the reference voltage supply terminal is provided.

Further, a semiconductor substrate on which a self-substrate bias generating circuit is formed, and a semiconductor substrate formed on the semiconductor substrate,
A P well having an N-type MOS transistor, a first N well formed in the semiconductor substrate and having a P-type MOS transistor, and formed in the first N well and having an impurity concentration higher than that of the N well. An N type diffusion region, a reverse bias supply terminal formed in the N type diffusion region in the first N well and electrically connected to the self substrate bias generating circuit, and an insulation formed on the semiconductor substrate surface. A MOS capacitor having a film and an electrode formed on the insulating film; and a high concentration N-type diffusion region to which a reverse bias supplied from the MOS capacitor and the self-substrate bias generating circuit is applied. 2 N wells and the above M
The fifth feature is that the power supply voltage supply terminal is formed on the electrode of the OS type capacitor.

[0014]

In the CMOS semiconductor device having the self-substrate bias generation circuit, M is formed in the well to which the reverse bias is applied.
By forming an OS type capacitor and supplying an external power source to this MOS type capacitor, fluctuations in the well potential at power-on are suppressed, and latch-up is prevented from occurring.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIGS. FIG. 1 is a cross-sectional view of a semiconductor device such as SRAM, and FIG. 2 is an equivalent circuit diagram of this semiconductor device. The semiconductor substrate 20 is made of, for example, a silicon semiconductor, and the field oxide film 7 made of SiO ₂ or the like is formed on its main surface. An N well 5 and a P well 6 in contact with this N well are formed in the surface region of the same main surface. A gate electrode 9 made of polysilicon or the like is formed in the P well 6 via a gate insulating film 8 made of a silicon oxide film or the like. Then, on both sides of the gate electrode 9, N
^{A +} diffusion region 3 is formed, which becomes the source / drain region of the NMOS transistor formed in this well. Further, a P ⁺ diffusion region 4 serving as an electrode lead-out region is formed in the P well 6, and a Vbb terminal for applying a predetermined potential Vbb to this electrode is provided. Then, the MOS capacitor 10 is formed near the P ⁺ diffusion region 4.

The MOS capacitor 10 is separated from the P ⁺ diffusion region 4 by a field oxide film 7. M
The OS capacitor 10 is formed on the main surface of the semiconductor substrate 20, and is composed of, for example, the insulating film 8 formed of the same thin film as the gate insulating film and the electrode 16 thereon. Then, the electrode 16 is formed on the entire surface of the region surrounded by the field oxide film formed in the P well 6. The electrode 16 is made of the same polysilicon as the gate electrode 9 and can be formed in the same step. A Vss terminal for applying a reference potential Vss is provided to one of the source / drain regions 3 and the electrode 16 of the MOS capacitor 10. On the other hand, a gate electrode 11 made of polysilicon or the like is formed on the N well 5 via a gate insulating film 8. Then, P ⁺ diffusion regions 2 are formed on both sides of the gate electrode 11, and these become the source / drain regions of the PMOS transistor formed in this well. In addition, the N well 5 will be an N
^{A +} diffusion region 1 is formed, and a Vdd terminal for supplying a positive power supply Vdd to this electrode is provided. The positive power supply Vdd is also configured to supply to one of the source / drain regions 2. In this semiconductor device, the common gate oxide film 8 is used as the insulating film of the MOS type transistor and the MOS type capacitor 10.

Further, the electrode 16 of the MOS capacitor 10
Uses a thin film common to the gate electrodes 9 and 11 of the MOS type transistor. That is, the MOS type capacitor is
It is formed in the same process as the MOS type transistor region.
FIG. 2 shows an equivalent circuit of the parasitic capacitance of the semiconductor device shown in FIG. Since Vdd is supplied to the N well, if the capacitance between the same potential and the capacitance between Vdd and Vss are excluded, the main parasitic capacitance is the parasitic capacitance C1 between the Vdd node and the P well and between the N well and the P well. The parasitic capacitance C2 and the parasitic capacitance C3 between the P well and the Vss node are collected. C1 is mainly the junction capacitance with the N ⁺ diffusion region biased to the Vdd terminal in the P well, and the parallel plate capacitance between the metal wiring of the Vdd terminal in the P well and the P well. C2 is a junction capacitance between the P well and the N well, a capacitance obtained by connecting the junction capacitance of the P ⁺ diffusion region on the output node side of the logic circuit and the junction capacitance of the N ⁺ diffusion region in series, and a PMOS transistor on the input node side of the logic circuit. Mainly, the parasitic capacitance of the gate and the parasitic capacitance of the gate of the NMOS transistor are connected in series. C3 is P
Mainly the junction capacitance of the N ⁺ diffusion region biased to Vss in the well. C10 is a MOS type capacitor 10
Is the capacity of.

From this, the potential V of the P well immediately after the power is turned on.
(P well) is calculated from V (P well) = Vdd × ((C1 + C2) / (C1 + C2 + C3 + C10)) (3), ignoring elements such as parasitic resistance. In other words, (C1 + C2) and (C
3 + C10) capacity ratio, P
The well potential is determined. MOS type capacitors are MO
Since it is insulated by an oxide film having the same thickness as the gate insulating film of the S-type transistor, the parallel plate capacitance per unit area is very large. Therefore, in the semiconductor device, (C1 + C
2) It is easy to establish a capacitance relationship such as << (C3 + C10). That is, Vdd >> V (P well) is always maintained.

Now, let us consider the operation at the time when the power supply voltage gradually rises and the logic circuits and the like in the semiconductor device start operating. The self-substrate bias generation circuit also starts operating, and the ring oscillator circuit shown in FIG. 6 outputs a rectangular wave. However, if the potential of Vdd is insufficient, the amplitude of the output of the ring oscillator circuit is small, and the amount of negative charges discharged from the pumping circuit to the P well is also small. Therefore, the potential of the P well continues to rise until the power supplied from the internal power supply Vbb suppresses the potential rise of the P well due to the parasitic capacitance. Then, when the potential of the P well exceeds the junction potential between the N ⁺ diffusion regions biased to the Vss terminal, the semiconductor device will be in a latch-up state. However, in the present invention, due to the presence of the MOS type capacitor, V (P well) immediately after the power is turned on
Since it is possible to reliably suppress the potential fluctuation of the voltage of not more than the junction potential with the N ⁺ diffusion region, it is possible to effectively prevent the occurrence of the latch-up phenomenon.

Next, a second embodiment will be described with reference to FIG. The figure is a cross-sectional view of a semiconductor device including a self-substrate bias generation circuit such as an SRAM. A field oxide film 7 made of SiO ₂ or the like is formed on the main surface of the semiconductor substrate 20. An N well 5 and a P well 6 in contact with this N well are formed in the surface region of the same main surface. A gate electrode 9 made of polysilicon or the like is formed in the P well 6 via a gate insulating film 8 made of a silicon oxide film or the like. Then, N ⁺ diffusion regions 3 are formed on both sides of the gate electrode 9, and these become the source / drain regions of the NMOS transistor formed in this well. In addition, the P well 6 has a P ⁺
A diffusion region 4 is formed, and a Vbb terminal for applying a predetermined potential Vbb to this electrode is provided. Then, a MOS capacitor 10 is formed adjacent to the P ⁺ diffusion region 4. The MOS capacitor 10 is formed on the main surface of the semiconductor substrate 20, and is composed of an insulating film 8 formed of the same thin film as the gate insulating film and an electrode 16 thereon. The electrode 16 is made of the same polysilicon as the gate electrode 9 and is formed in the same step. A Vss terminal for applying a reference potential Vss is provided to one of the source / drain regions 3 and the electrode 16 of the MOS transistor 10.

On the other hand, a gate electrode 11 made of polysilicon or the like is formed on the N well 5 via a gate insulating film 8. Then, P ⁺ diffusion regions 2 are formed on both sides of the gate electrode 11, and P ⁺ diffusion regions 2 are formed in this well.
It becomes the source / drain region of the S transistor. Further, in the N well 5, an N ⁺ diffusion region 1 to be an electrode extraction region is formed.
Is formed, and a Vdd terminal for supplying a positive power supply Vdd to this electrode is provided. The positive power supply Vdd is also configured to supply to one of the source / drain regions 2. In this semiconductor device, a MOS type transistor and a MOS type capacitor 10
A common gate oxide film 8 is used for the insulating film of
The electrode 16 of the type capacitor 10 uses the same thin film as the gate electrodes 9 and 11 of the MOS transistor. That is, the MOS capacitor 10 is formed in the same process as the MOS transistor region, and the region where the capacitor 10 is formed is surrounded by the field oxide film.
A P ⁺ diffusion region 4 is also formed in this region.
Without forming the polysilicon electrode 16 on the entire surface of this region,
Some are left exposed and a P ⁺ diffusion region is formed in a later step. Then, the substrate bias power source Vbb is connected here. In this case, since the parasitic resistance between the power source Vss and the substrate bias power source Vbb can be reduced, V (P
It is possible to further suppress the potential fluctuation of the well).

Next, a third embodiment will be described with reference to FIG. The figure is a cross-sectional view of a semiconductor device including a self-substrate bias generation circuit. The MOS capacitor of the present invention is
It is not necessary to coexist in the well in which the MOS transistor forming the CMOS structure is formed, and it may be formed in a well different from that well. A field oxide film 7 is formed on the main surface of the semiconductor substrate 20. An N well 5 and a P well 6 in contact with this N well are formed in the surface region of the same main surface. A gate electrode 9 made of polysilicon or the like is formed in the P well 6 via a gate insulating film 8 made of a silicon oxide film or the like. The N ⁺ diffusion regions 3 are formed on both sides of the gate electrode 9.
Are formed, which become the source / drain regions of the NMOS transistor formed in this well. Further, a P ⁺ diffusion region 4 serving as an electrode lead-out region is formed in the P well 6, and a Vbb terminal for applying a predetermined potential Vbb to this electrode is provided.

On the other hand, a gate electrode 11 made of polysilicon or the like is formed on the N well 5 via a gate insulating film 8. Then, P ⁺ diffusion regions 2 are formed on both sides of the gate electrode 11, and P ⁺ diffusion regions 2 are formed in this well.
It becomes the source / drain region of the S transistor. Further, in the N well 5, an N ⁺ diffusion region 1 to be an electrode extraction region is formed.
Is formed, and a Vdd terminal for supplying a positive power supply Vdd to this electrode is provided. The positive power supply Vdd is also configured to supply to one of the source / drain regions 2. The MOS capacitor 10 is not formed in the P well 6, but is formed in the P well 12 different from this well region. The boundary of the P well 12 is surrounded by the field oxide film 7 forming the element isolation region. The MOS capacitor 10 is composed of an insulating film 8 formed of the same thin film as the gate insulating film and an electrode 16 thereon. Further, a P ⁺ diffusion region 13 is formed in the P well 12 adjacent to the electrode 16, and a Vbb terminal for applying a predetermined potential Vbb to this electrode is provided.

Therefore, the electrode 16 is formed on the entire surface of the region surrounded by the field oxide film 7 formed on the boundary of the P well 12 except the P ⁺ diffusion region 13. The electrode 16 is made of the same polysilicon thin film as the gate electrodes 9 and 11, and can be formed in the same step. Vss for applying the reference potential Vss to one of the source / drain regions 3 of the NMOS transistor and the electrode 16 of the MOS type capacitor 10.
Provide terminals. In this semiconductor device, the common gate oxide film 8 is used as the insulating film of the MOS type transistor and the MOS type capacitor 10. By forming the MOS type capacitor in an arbitrary region in the semiconductor device, for example, an inactive region which is not used such as under the power supply wiring, it is possible to avoid increasing the chip size in order to add the MOS type capacitor.

Next, a fourth embodiment will be described with reference to FIG. The present invention is not only applied to the substrate bias applied to the P well, but can also be applied to a semiconductor device having a self-substrate bias generation circuit for applying a reverse bias power supply Vpp to the N well. MOS between power supply voltage Vpp
A type capacitor may be formed. This embodiment shows a case where a substrate bias is applied by an internal power source to both the N well and the P well. The figure is a cross-sectional view of a semiconductor device including two self-substrate bias generation circuits for supplying a voltage Vbb and a voltage Vpp. The MOS type capacitor of this embodiment does not coexist in the well in which the MOS transistor forming the CMOS structure is formed as in the third embodiment, but is formed in a well different from that well. A field oxide film 7 is formed on the main surface of the semiconductor substrate 20. An N well 5 and a P well 6 in contact with this N well are formed in the surface region of the same main surface.

In the P well 6, a gate electrode 9 made of polysilicon or the like is formed via a gate insulating film 8 made of a silicon oxide film or the like. Then, N ⁺ diffusion regions 3 are formed on both sides of the gate electrode 9, and these become the source / drain regions of the NMOS transistor formed in this well. Further, a P ⁺ diffusion region 4 serving as an electrode lead-out region is formed in the P well 6, and a predetermined potential Vbb is applied to this electrode.
The Vbb terminal that gives A gate electrode 11 made of polysilicon or the like is provided in the N well 5 via a gate insulating film 8.
Are formed. On both sides of the gate electrode 11, P ⁺
A diffusion region 2 is formed, which becomes the source / drain region of the PMOS transistor formed in this well.
Further, an N ⁺ diffusion region 1 serving as an electrode drawing region is formed in the N well 5, and a reverse bias positive power source Vpp is applied to this electrode.
A Vdd terminal that provides The positive power supply Vdd is configured to be supplied to one of the source / drain regions 2.

The MOS capacitor 10 is not formed in the P well 6, but is formed in the P well 12 different from this well region. The boundary of the P well 12 is surrounded by the field oxide film 7 forming the element isolation region. The MOS capacitor 10 is composed of an insulating film 8 formed of the same thin film as the gate insulating film and an electrode 16 thereon. In addition, a P ⁺ diffusion region 13 is formed in the P well 12 adjacent to the electrode 16, and V which gives a predetermined potential Vbb to this electrode.
Provide bb terminal. Therefore, the electrode 16 is formed on the entire surface of the region surrounded by the field oxide film 7 formed on the boundary of the P well 12 except the P ⁺ diffusion region 13. The electrode 16 is made of the same polysilicon thin film as the gate electrodes 9 and 11 and is formed in the same step. One of the source / drain regions 3 of the NMOS transistor and the MOS type capacitor 10
A Vss terminal for applying the reference potential Vss to the electrode 16 of the above is provided.
In this semiconductor device, a MOS transistor and an MO
A common gate oxide film 8 is used as the insulating film of the S-type capacitor 10.

Further, the MOS capacitor 30 is the N well 5
N well 14 which is not formed in the well region and is different from this well region.
Is formed. The boundary of the N well 14 is surrounded by the field oxide film 7 forming the element isolation region. The MOS capacitor 30 is composed of an insulating film 8 formed of the same thin film as the gate insulating film and an electrode 17 thereon. Further, an N ⁺ diffusion region 15 is formed in the N well 14 adjacent to the electrode 17, and a Vpp terminal for providing a reverse bias Vpp to this electrode is provided. Therefore, the electrode 17 is formed on the entire surface of the region surrounded by the field oxide film 7 formed on the boundary of the N well 14 except the N ⁺ diffusion region 15. The electrode 17 is made of the same polysilicon thin film as the gate electrodes 9, 11, 16 and is formed in the same step. In the present invention, the MOS capacitor 30 of this embodiment may be provided in the N well 5.

The MOS type capacitor is formed in an arbitrary region in the semiconductor device, for example, in an inactive region which is not used, such as under the power supply wiring, so that it is not necessary to increase the chip size in order to add the MOS type capacitor. To be In this embodiment, the MOS capacitor 10 can suppress the potential fluctuation of V (P well) immediately after the power is turned on, and the MOS capacitor 30 can suppress the potential fluctuation of V (N well) immediately after the power is turned on. It is possible to effectively prevent the occurrence of the up phenomenon. Further, the two MOS capacitors are respectively P-type as in the first embodiment.
It can also be incorporated in the well in which the MOS transistor and the NMOS transistor are formed. In the present invention, either an N type substrate or a P type substrate may be used as the semiconductor substrate. It can also be applied to a semiconductor device having a CMOS structure provided only with the self-substrate bias generating circuit for supplying the reverse bias power supply Vpp shown in the fourth embodiment.

[0030]

According to the present invention, a MOS type capacitor is formed in the well of a semiconductor device having a CMOS structure equipped with a self-substrate bias generating circuit, and an external power supply is supplied to this MOS type capacitor to reverse bias when the power is turned on. It suppresses the fluctuation of the well potential of the well to which is applied and prevents the occurrence of latch-up.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the semiconductor device of FIG.

FIG. 3 is a sectional view of a semiconductor device according to a second embodiment.

FIG. 4 is a sectional view of a semiconductor device according to a third embodiment.

FIG. 5 is a sectional view of a semiconductor device according to a fourth embodiment.

FIG. 6 is a circuit diagram of the present invention and a conventional self-substrate bias generation circuit.

FIG. 7 is an equivalent circuit diagram of a parasitic capacitance of a conventional semiconductor device.

FIG. 8 is a sectional view of a conventional semiconductor device.

FIG. 9 is an equivalent circuit diagram of a parasitic bipolar transistor of a conventional semiconductor device.

FIG. 10 is a Cj-Vr characteristic diagram of the junction capacitance of the conventional semiconductor device.

[Explanation of symbols]

1, 3, 15 N ⁺ diffusion region 2, 4, 13 P ⁺ diffusion region 5, 14 N well 6, 12 P well 7 Field oxide film 8 Insulating film (gate insulating film) 9, 11 Gate electrode 10, 30 MOS type Capacitors 16 and 17 Capacitor electrodes 20 Semiconductor substrate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 21/8238 27/092 21/8244 27/11 29/78 H01L 27/10 381 29/78 301 S

Claims (5)

[Claims] 1. A semiconductor substrate on which a self-substrate bias generating circuit is formed, a P well formed on the semiconductor substrate and having an N-type MOS transistor, and a P-type MOS transistor formed on the semiconductor substrate. An N well, a P-type diffusion region having a higher impurity concentration than the P-well region, and a P-type diffusion region having an impurity concentration higher than that of the P-well and being electrically connected to the self-substrate bias generating circuit. A bias supply terminal, a MOS type capacitor formed of the P well region and including an insulating film formed on the surface of the semiconductor substrate and an electrode formed on the insulating film, and a MOS capacitor formed on the electrode. A semiconductor device comprising a reference voltage supply terminal. 2. A semiconductor substrate on which a self-substrate bias generation circuit is formed, a P-well formed on the semiconductor substrate and having an N-type MOS transistor, and a P-type MOS transistor formed on the semiconductor substrate. An N well, an N type diffusion region formed in the N well region and having an impurity concentration higher than that of the N well, and an N type diffusion region formed in the N type diffusion region and electrically connected to the self substrate bias generating circuit. A MOS type capacitor having a bias supply terminal, an insulating film formed in the N well region and formed on the surface of the semiconductor substrate, and an electrode formed on the insulating film; and a power supply voltage formed on the electrode. A semiconductor device comprising a supply terminal. 3. A semiconductor substrate on which first and second self-substrate bias generating circuits are formed, a P well formed on the semiconductor substrate and having an N-type MOS transistor, and formed on the semiconductor substrate, An N well provided with a P type MOS transistor, a P type diffusion region formed in the P well region and having an impurity concentration higher than that of the P well, and formed in the P type diffusion region to generate the first self-substrate bias. A first reverse bias supply terminal electrically connected to the circuit, an insulating film formed in the P well region and formed on the surface of the semiconductor substrate, and an electrode formed on the insulating film. A first MOS capacitor, a reference voltage supply terminal formed on the electrode of the first MOS capacitor, and an impurity concentration from the N well formed in the N well region. A high N-type diffusion region, a reverse bias supply terminal formed in the N-type diffusion region and electrically connected to the second self-substrate bias generation circuit, and formed in the N-well region, the semiconductor substrate surface A second MOS type capacitor having an insulating film formed on the insulating film and an electrode formed on the insulating film; and a power supply voltage supply terminal formed on the electrode of the second MOS type capacitor. A semiconductor device characterized by the above. 4. A semiconductor substrate on which a self-substrate bias generation circuit is formed, a first P well formed on the semiconductor substrate and having an N-type MOS transistor, and a P-type MOS formed on the semiconductor substrate. An N well including a transistor, a P type diffusion region formed in the first P well and having an impurity concentration higher than that of the P well, and formed in the P type diffusion region in the first P well,
A reverse bias supply terminal electrically connected to the self-substrate bias generating circuit, a MOS capacitor including an insulating film formed on the surface of the semiconductor substrate and an electrode formed on the insulating film, A second P-well having a high-concentration P-type diffusion region to which a reverse bias supplied from the MOS type capacitor and the self-substrate bias generating circuit is applied; and a reference voltage supply terminal formed on an electrode of the MOS type capacitor. A semiconductor device comprising: 5. A semiconductor substrate on which a self-substrate bias generation circuit is formed, a P well formed on the semiconductor substrate and having an N-type MOS transistor, and a P-type MOS transistor formed on the semiconductor substrate. A first N well, an N type diffusion region formed in the first N well and having an impurity concentration higher than that of the N well, and an N type diffusion region in the first N well. A MOS type capacitor having a reverse bias supply terminal electrically connected to a substrate bias generating circuit, an insulating film formed on the surface of the semiconductor substrate, and an electrode formed on the insulating film, and the MOS type capacitor A second N well having a high-concentration N-type diffusion region to which a reverse bias supplied from the self-substrate bias generating circuit is applied; The semiconductor device is characterized in that a power supply voltage supply terminal formed on the electrode.