TW202429087A - Method for detecting of detection circuit - Google Patents

Method for detecting of detection circuit Download PDF

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TW202429087A
TW202429087A TW112100188A TW112100188A TW202429087A TW 202429087 A TW202429087 A TW 202429087A TW 112100188 A TW112100188 A TW 112100188A TW 112100188 A TW112100188 A TW 112100188A TW 202429087 A TW202429087 A TW 202429087A
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test
circuit
tested
value
signal
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TW112100188A
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TWI848501B (en
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汪光夏
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黑澤科技股份有限公司
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Abstract

The present invention discloses a method for detecting of a detection circuit, which is applied for detecting a circuit under test. The method according to the present invention provides a test power source to an input terminal of at least one line in the circuit under test, and a test signal is detected from an output terminal of the least one line in the circuit under test by coupling a probe element during a test period. And, the test period is corresponding to a material characteristic of the least one line. Thus, the quantitative characteristic of the detection circuit may be detected, and the least one line is completed to test in the corresponded test period.

Description

檢測電路之檢測方法Testing method of testing circuit

本發明係關於一種測試方法,特別是一種檢測電路之檢測方法,其係用以檢測待測電路之元件電性及線路電性。The present invention relates to a testing method, in particular to a testing method for testing circuits, which is used to test the electrical properties of components and circuits of the circuit to be tested.

積體電路(integrated circuit,IC)或晶片(Chip)的製造會先經過上游的IC設計公司提出對應之電路設計方案,中游的半導體代工廠依據IC設計公司之電路設計方案提供對應之半導體製程進行代工製造,再接續由下游之封裝測試廠對半導體代工廠所代工生產之積體電路(integrated circuit,IC)或晶片(Chip)進行電路測試,因此電路測試對於積體電路(integrated circuit,IC)或晶片(Chip)的製造過程屬於不可或缺的其中一階段。不論是傳統封裝型態還是晶圓級封裝,在積體電路(integrated circuit,IC)或晶片(Chip)的晶圓型態與封裝型態,都必須經過一個特定的測試程序,以確保積體電路(integrated circuit,IC)或晶片(Chip)的內部中每一電子元件都正常運作。The manufacturing of integrated circuits (ICs) or chips will first go through the upstream IC design company proposing a corresponding circuit design solution. The midstream semiconductor foundry will provide the corresponding semiconductor process for foundry manufacturing based on the IC design company's circuit design solution. The downstream packaging and testing factory will then conduct circuit testing on the integrated circuits (ICs) or chips produced by the semiconductor foundry. Therefore, circuit testing is an indispensable stage in the manufacturing process of integrated circuits (ICs) or chips. Whether it is a traditional packaging type or a wafer-level packaging, the wafer type and packaging type of the integrated circuit (IC) or chip must undergo a specific testing procedure to ensure that each electronic component inside the integrated circuit (IC) or chip operates normally.

進一步地,積體電路(integrated circuit,IC)或晶片(Chip)設置於電路板上後,電路板上的電路佈局亦是需要測試與驗證,例如:印刷電路板(PCB)的電路測試與電路驗證,現今更是利用自動化測試機台(Automatic test equipment,ATE),應用於自動化測試電路板上的電子零件,甚至是測試電路板上的積體電路(integrated circuit,IC)或晶片(Chip)。Furthermore, after the integrated circuit (IC) or chip is placed on the circuit board, the circuit layout on the circuit board also needs to be tested and verified, such as circuit testing and circuit verification of the printed circuit board (PCB). Nowadays, automatic test equipment (ATE) is used to automatically test electronic components on the circuit board, and even to test the integrated circuit (IC) or chip on the circuit board.

然而,測試過程中,不外乎是利用探針進行接觸電路板上的測試墊或腳位,而測試電壓有可能導致火花產生,自動化測試機台並未能有一個有效量化數據提供給測試人員了解。例如:日本電產理德股份有限公司之中國專利號第CN104422860B之檢測裝置為利用判定部判斷恆定電流源提供恆定電流至帶測電路並以待測電路之測試電壓是否維持一電壓斜度判斷待測電路是否不良,卻未能獲得確切之可量化數值。However, during the test process, the probe is used to contact the test pad or pin on the circuit board, and the test voltage may cause sparks. The automated test machine does not provide effective quantitative data for the test personnel to understand. For example, the detection device of Chinese Patent No. CN104422860B of Nidec Read Co., Ltd. uses a determination unit to determine whether the constant current source provides a constant current to the test circuit and whether the test circuit maintains a voltage slope to determine whether the test circuit is defective, but it cannot obtain an accurate quantifiable value.

除此之外,待測電路之線路材料不同會導致待測電路之線路的極化反應時間不同,甚至超過一般待測電路之測試時間,因而導致待測電路於測試時間過後方才發生的線路缺陷並未能被偵測到。In addition, different materials of the circuits under test will result in different polarization reaction times of the circuits under test, which may even exceed the test time of the general circuits under test, thereby causing circuit defects of the circuits under test that occur after the test time has passed to be undetected.

基於上述之問題,本發明提供一種檢測電路之檢測方法,其藉由一測試電源提供至一待測電路之至少一線路之一輸入端,並經由至少一探針元件於該至少一線路之一輸出端耦接並量測,並讓該待測電路於該至少一線路之線路材料特性所對應之一測試時間內產生一測試訊號,藉此讓檢測電路可從待測電路取得可量化數據並可在對應之測試時間中完成測試。Based on the above-mentioned problem, the present invention provides a detection method for a detection circuit, which provides a test power supply to an input end of at least one line of a circuit to be tested, and couples and measures at an output end of the at least one line through at least one probe element, and allows the circuit to be tested to generate a test signal within a test time corresponding to the line material characteristics of the at least one line, thereby allowing the detection circuit to obtain quantifiable data from the circuit to be tested and complete the test within the corresponding test time.

本發明之一目的,在於提供一種檢測電路,其藉由一探針元件耦接一待測電路,並提供一測試電源至該待測電路之一輸入端,以讓該待測電路之一輸出端產生一測試訊號至該探針元件,以在一測試時間內取得對應之測試訊號,且該測試時間對應於該待測電路之一線路材料特性,因而可從待測待測電路取得可量化數據並可在對應之測試時間中完成測試。One purpose of the present invention is to provide a detection circuit, which is coupled to a circuit to be tested by a probe element, and provides a test power supply to an input terminal of the circuit to be tested, so that an output terminal of the circuit to be tested generates a test signal to the probe element, so as to obtain a corresponding test signal within a test time, and the test time corresponds to a line material property of the circuit to be tested, so that quantifiable data can be obtained from the circuit to be tested and the test can be completed within the corresponding test time.

針對上述之目的,本發明提供一種檢測電路之檢測方法,其應用於檢測一待測電路,該待測電路上設有至少一線路。In view of the above-mentioned purpose, the present invention provides a detection method for a detection circuit, which is applied to detect a circuit to be tested, wherein the circuit to be tested has at least one circuit.

本發明進一步提供一實施例,其在於當該測試訊號於一升壓階段且該降壓數值大於一第一門檻值時,該測試訊號為對應於該待測電路之一第一異常狀態,當該測試訊號於一飽和階段且該降壓數值大於一第二門檻值時,該測試訊號為對應於該待測電路之一第二異常狀態。The present invention further provides an embodiment, wherein when the test signal is in a boost phase and the voltage reduction value is greater than a first threshold value, the test signal corresponds to a first abnormal state of the circuit to be tested, and when the test signal is in a saturation phase and the voltage reduction value is greater than a second threshold value, the test signal corresponds to a second abnormal state of the circuit to be tested.

本發明進一步提供一實施例,其在於該測試訊號於一第一異常狀態之一第一測試阻抗值大於該測試訊號於一第二異常狀態之一第二測試阻抗值。The present invention further provides an embodiment, wherein a first test impedance value of the test signal in a first abnormal state is greater than a second test impedance value of the test signal in a second abnormal state.

本發明進一步提供一實施例,其在於該第一測試阻抗值與該第二測試阻抗值大於該測試訊號於一正常狀態之一第三測試阻抗值The present invention further provides an embodiment, wherein the first test impedance value and the second test impedance value are greater than a third test impedance value of the test signal in a normal state.

本發明進一步提供一實施例,其在於該第一測試阻抗值為100歐姆至10k歐姆。The present invention further provides an embodiment, wherein the first test impedance value is 100 ohms to 10k ohms.

本發明進一步提供一實施例,其在於該測試電源為100伏特至350伏特。The present invention further provides an embodiment, wherein the test power source is 100 volts to 350 volts.

本發明進一步提供一實施例,其在於該測試時間大於該待測電路之一極化反應時間。The present invention further provides an embodiment, wherein the test time is greater than a polarization reaction time of the circuit to be tested.

本發明進一步提供一實施例,其在於該線路材料特性具有一極化參數,該極化參數對應於該極化反應時間。The present invention further provides an embodiment, wherein the circuit material characteristic has a polarization parameter, and the polarization parameter corresponds to the polarization reaction time.

本發明進一步提供一實施例,其在於該測試電源為一電流源,該測試電流為5毫安培至20毫安培。The present invention further provides an embodiment, wherein the test power source is a current source, and the test current is 5 mA to 20 mA.

本發明進一步提供一實施例,其在於該至少一線路更耦接一電子元件。The present invention further provides an embodiment, wherein the at least one circuit is further coupled to an electronic component.

為使 貴審查委員對本發明之特徵及所達成之功效有更進一步之瞭解與認識,謹佐以較佳之實施例及配合詳細之說明,說明如後:In order to enable you to have a deeper understanding and knowledge of the features and effects of the present invention, we would like to provide you with a better embodiment and detailed description, as follows:

在說明書及請求項當中使用了某些詞彙指稱特定的元件,然,所屬本發明技術領域中具有通常知識者應可理解,同一個元件可能會用不同的名詞稱呼,而且,本說明書及請求項並不以名稱的差異作為區分元件的方式,而是以元件在整體技術上的差異作為區分的準則。在通篇說明書及請求項當中所提及的「包含」為一開放式用語,故應解釋成「包含但不限定於」。再者,「耦接」一詞在此包含任何直接及間接的連接手段。因此,若文中描述一第一裝置耦接一第二裝置,則代表第一裝置可直接連接第二裝置,或可透過其他裝置或其他連接手段間接地連接至第二裝置。Certain terms are used in the specification and claims to refer to specific components. However, those with ordinary knowledge in the art of the present invention should understand that the same component may be referred to by different terms. Moreover, the specification and claims do not use the difference in name as a way to distinguish components, but use the difference in the overall technology of the components as the criterion for distinction. The term "including" mentioned throughout the specification and claims is an open term and should be interpreted as "including but not limited to". Furthermore, the term "coupled" includes any direct and indirect means of connection. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly connected to the second device, or can be indirectly connected to the second device through other devices or other means of connection.

有鑑於上述先前技術中,自動化檢測裝置並未能提供可量化之檢測數據,因而無法提供可量化數值讓使用者直觀地了解電路檢測狀況。In view of the above-mentioned prior art, the automated testing device cannot provide quantifiable testing data, and thus cannot provide quantifiable values for users to intuitively understand the circuit testing status.

在下文中,將藉由圖式來說明本發明之各種實施例來詳細描述本發明。然而本發明之概念可能以許多不同型式來體現,且不應解釋為限於本文中所闡述之例示性實施例。Hereinafter, the present invention will be described in detail by illustrating various embodiments of the present invention with reference to the drawings. However, the concept of the present invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments described herein.

首先,請參閱第1圖,其為本發明之一實施例之流程圖。如圖所示,本發明之檢測電路之檢測方法之步驟包含:First, please refer to FIG. 1, which is a flow chart of an embodiment of the present invention. As shown in the figure, the steps of the detection method of the detection circuit of the present invention include:

步驟S10:提供測試電源傳導至待測電路之線路之輸入端;Step S10: providing a test power source to be transmitted to the input end of the line of the circuit to be tested;

步驟S20: 利用探針元件耦接待測電路之線路之輸出端;以及Step S20: using a probe element to couple the output end of the line of the circuit to be tested; and

步驟S30: 待測電路於測試時間內經由探針元件耦接並產生測試訊號。Step S30: The circuit to be tested is coupled via the probe element during the test time and generates a test signal.

請一併參閱第2圖,其為本發明之一實施例之系統示意圖。如圖所示,本發明之一實施例之檢測電路10為包含一感測電路12與一電源量測單元14,本實施例之檢測電路10為用於檢測一待測電路30,例如:檢測印刷電路板上的待測電路、晶圓上的積體電路等,待測電路30包含一電子元件32與一線路34,電子元件32設置於線路34上,又或者待測電路30上僅有線路34,其中線路34包含一輸入端342與一輸出端344,因而讓輸入端342用於耦接電源量測單元14之一輸出元件142,且輸出端344用於耦接感測電路12之一探針元件122。此外,本實施例之檢測電路10更進一步包含一控制處理單元20,其耦接感測電路12以及電源量測單元14,因而接收來自於感測電路12之感測訊號SEN,以及經由一控制訊號CTRL控制電源量測單元14。Please refer to FIG. 2, which is a schematic diagram of a system of an embodiment of the present invention. As shown in the figure, the detection circuit 10 of an embodiment of the present invention includes a sensing circuit 12 and a power measurement unit 14. The detection circuit 10 of the present embodiment is used to detect a circuit to be tested 30, for example: to detect a circuit to be tested on a printed circuit board, an integrated circuit on a wafer, etc. The circuit to be tested 30 includes an electronic component 32 and a line 34, and the electronic component 32 is arranged on the line 34, or there is only the line 34 on the circuit to be tested 30, wherein the line 34 includes an input terminal 342 and an output terminal 344, so that the input terminal 342 is used to couple an output component 142 of the power measurement unit 14, and the output terminal 344 is used to couple a probe component 122 of the sensing circuit 12. In addition, the detection circuit 10 of the present embodiment further includes a control processing unit 20, which is coupled to the sensing circuit 12 and the power measurement unit 14, so as to receive the sensing signal SEN from the sensing circuit 12 and control the power measurement unit 14 via a control signal CTRL.

復參閱第1圖,本發明之檢測方法先執行步驟S10,於步驟S10中,如第2圖所示,電源量測單元14提供一測試電源P經輸出元件142與輸入端342傳輸至待測電路30,接續執行步驟S20,探針元件122為耦接於輸出端344,用於讓感測電路12經由探針元件122感測輸出端344之訊號。Referring back to FIG. 1, the detection method of the present invention first executes step S10. In step S10, as shown in FIG. 2, the power measurement unit 14 provides a test power P which is transmitted to the circuit under test 30 via the output element 142 and the input terminal 342. Then, step S20 is executed. The probe element 122 is coupled to the output terminal 344 so that the sensing circuit 12 senses the signal of the output terminal 344 via the probe element 122.

接續於步驟S30中,如第2圖至第3B圖所示,待測電路30於一測試時間T S內接收到致能電位(ON)之測試電源P,並對應產生一測試訊號124,也就是控制處理單元20控制電源量測單元14於測試時間T S內致能測試電源P,因而讓待測電路30產生測試訊號124,並經輸出端344傳導至探針元件122,以傳送測試訊號124至感測電路12,因而產生感測訊號SEN至控制處理單元20,控制處理單元20即依據感測訊號SEN取得待測電路30之一異常狀態或一正常狀態。 Continuing in step S30, as shown in FIGS. 2 to 3B, the circuit under test 30 receives the test power P at an enable potential (ON) within a test time TS , and generates a test signal 124 accordingly, that is, the control processing unit 20 controls the power measurement unit 14 to enable the test power P within the test time TS , so that the circuit under test 30 generates the test signal 124, and transmits the test signal 124 to the probe element 122 through the output terminal 344 to transmit the test signal 124 to the sensing circuit 12, thereby generating a sensing signal SEN to the control processing unit 20, and the control processing unit 20 obtains an abnormal state or a normal state of the circuit under test 30 according to the sensing signal SEN.

其中,檢測電路10之測試時間T S對應於待測電路30之線路34之一線路材料特性,特別是一極化反應時間對應之一極化參數,也就是在古典電磁學裏,當給線路34施加一個電場時,線路34內部正負電荷會相對位移,因而會產生電偶極,這現象稱為電極化(electric polarization)。本實施例之測試電源P在提供至線路34的過程中,相當於測試電源P之電場施加於線路34上,此時,線路34響應外電場而極化的程度,可以用電極化率(electric susceptibility,χ e)來衡量,電極化率又可以用來計算物質的電容率,因此本實施例所述之極化參數即為電極化率,由於一般線路34之材料為選自於金屬,例如:金、銀、鎳、錫、鋁、鎵、銦或其組合,因此線路34即會依據其極化參數與測試電源P而出現電極化之現象,線路34於測試電源P通過且超過該極化反應時間後,即受到電場之影響而發生極化。 The test time TS of the detection circuit 10 corresponds to a line material property of the line 34 of the circuit 30 to be tested, in particular, a polarization parameter corresponding to a polarization reaction time. That is, in classical electromagnetics, when an electric field is applied to the line 34, the positive and negative charges inside the line 34 will be relatively displaced, thereby generating an electric dipole. This phenomenon is called electric polarization. In the process of providing the test power source P of this embodiment to the line 34, it is equivalent to applying the electric field of the test power source P to the line 34. At this time, the degree of polarization of the line 34 in response to the external electric field can be expressed by the electric susceptibility (χ e ) is used to measure, and the polarization rate can be used to calculate the capacitance of a material. Therefore, the polarization parameter described in this embodiment is the polarization rate. Since the material of the general line 34 is selected from metals, such as gold, silver, nickel, tin, aluminum, gallium, indium or a combination thereof, the line 34 will be polarized according to its polarization parameter and the test power source P. After the test power source P passes through and exceeds the polarization reaction time, the line 34 is affected by the electric field and polarized.

本實施例之測試訊號124分為電壓訊號V S與電流訊號I S,而本實施例之測試電源P於正常狀態下為100伏特至350伏特之電壓(即充壓飽和穩態後),當感測電路12感測到異常時,電源量測單元14即切換測試電源P為一電流源,該電流源為一定電流,該定電流為1毫安培至30毫安培之間之一定值。 The test signal 124 of the present embodiment is divided into a voltage signal VS and a current signal IS . The test power source P of the present embodiment is a voltage of 100 volts to 350 volts under normal conditions (i.e., after being fully charged and stabilized). When the sensing circuit 12 senses an abnormality, the power measurement unit 14 switches the test power source P to a current source, which is a constant current, and the constant current is a constant value between 1 mA and 30 mA.

測試電源P提供至待測電路30之方式可區分為直接施加定電壓至待測電路30,或提供升壓至待測電路30,而逐步升壓至上限值。The test power source P is provided to the circuit under test 30 in two ways: directly applying a constant voltage to the circuit under test 30, or providing a boosted voltage to the circuit under test 30 and gradually boosting the voltage to an upper limit value.

待測電路30於正常狀態下,如第3A圖所示,電壓訊號V S與電流訊號I S於正常狀態下,不會出現起伏,即相當於定電壓與定電流之情況,即使出現起伏,但電壓訊號V S之電位下降值並未超出或等於一第一門檻值TH1,而電流訊號I S之電流上升值並未超出或等於一第二門檻值TH2。 When the circuit to be tested 30 is in a normal state, as shown in FIG. 3A , the voltage signal VS and the current signal IS will not fluctuate, which is equivalent to a constant voltage and a constant current situation. Even if fluctuations occur, the potential drop value of the voltage signal VS does not exceed or equal to a first threshold value TH1, and the current rise value of the current signal IS does not exceed or equal to a second threshold value TH2.

待測電路30於一異常狀態下,如第3B圖所示,電壓訊號V S與電流訊號I S於異常狀態下,會出現超出或等於第一門檻值TH1與第二門檻值TH2之起伏,當電壓訊號V S之電位下降值超出或等於第一門檻值TH1時,電流訊號I S之電流上升值會超出或等於一第二門檻值TH2,即當電壓訊號V S降低至一第一下降值V D1而超出第一門檻值TH1時,電流訊號I S會上升至一第一上升值I D1而超出第二門檻值TH2,如此即表示測試訊號124處於第一異常狀態。 When the circuit to be tested 30 is in an abnormal state, as shown in FIG. 3B , the voltage signal VS and the current signal IS will fluctuate beyond or equal to the first threshold value TH1 and the second threshold value TH2. When the potential drop value of the voltage signal VS exceeds or equals the first threshold value TH1, the current rise value of the current signal IS will exceed or equal to a second threshold value TH2. That is, when the voltage signal VS decreases to a first drop value V D1 and exceeds the first threshold value TH1, the current signal IS will rise to a first rise value ID1 and exceed the second threshold value TH2. This indicates that the test signal 124 is in the first abnormal state.

另外,如第3B圖所示,電壓訊號V S會出現一第二下降值V D2,第二下降值V D2會小於第一下降值V D2,電流訊號I S對應出現之一第二上升值I D2亦是小於第一上升值I D1,同時第二下降值V D2會等於第一門檻值TH1,而第二上升值I D2會等於第二門檻值TH2,即當電壓訊號V S降低至第二下降值V D2而等於第一門檻值TH1時,電流訊號I S會上升至第二上升值I D2而等於第二門檻值TH2,如此即表示測試訊號124處於第二異常狀態,因此電壓訊號V S於出現第一下降值V D1或第二下降值V D2,電流訊號I S會相對應出現第一上升值I D1或第二上升值I D2。本實施例中,線路34於測試電源P通過且超過該極化反應時間後,因而讓測試訊號124出現第二下降值V D2與第二上升值I D2,也就是說本實施例之測試時間TS大於線路34之極化反應時間,因而讓感測電路12測得第二下降值V D2與第二上升值I D2In addition, as shown in FIG. 3B , the voltage signal VS will have a second decreasing value V D2 , which will be smaller than the first decreasing value V D2 , and the current signal IS will have a corresponding second increasing value ID2 which is also smaller than the first increasing value ID1 . Meanwhile, the second decreasing value V D2 will be equal to the first threshold value TH1 , and the second increasing value ID2 will be equal to the second threshold value TH2 , that is, when the voltage signal VS decreases to the second decreasing value V D2 and is equal to the first threshold value TH1 , the current signal IS will increase to the second increasing value ID2 and be equal to the second threshold value TH2 , which indicates that the test signal 124 is in the second abnormal state , therefore , when the voltage signal VS has the first decreasing value V D1 or the second decreasing value V D2 , the current signal IS will have the first increasing value ID1 or the second increasing value ID2 correspondingly . In this embodiment, after the test power P passes through the line 34 and exceeds the polarization response time, the test signal 124 shows a second decreasing value V D2 and a second increasing value I D2 . That is to say, the test time TS of this embodiment is greater than the polarization response time of the line 34 , so the sensing circuit 12 measures the second decreasing value V D2 and the second increasing value I D2 .

其中,電流訊號I S為表示漏電流,基於電阻為電壓除以電流,會如下式(一)。 式(一) Among them, the current signal IS represents the leakage current. Based on the fact that resistance is voltage divided by current, it will be as follows (1). Formula (I)

第一下降值V D1與第一上升值I D1即求得一第一測試阻抗值R D1,第二下降值V D2與第二上升值I D2即求得一第二測試阻抗值R D2,藉此第一測試阻抗值R D1大於第二測試阻抗值R D2,且因正常狀態並不會出現漏電流與下降值,因此令測試訊號124於正常狀態時為對應一第三測試阻抗值R,第一測試阻抗值R D1與第二測試阻抗值R D2皆會大於第三測試阻抗值R,而第一測試阻抗值R D1即對應於測試訊號124之第一異常狀態,第二測試阻抗值R D2即對應於測試訊號124之第二異常狀態,其中第一測試阻抗值R D1為100歐姆(Ω)至10千歐姆(kΩ),第二測試阻抗值R D2為100歐姆(Ω)至1千歐姆(kΩ)。 The first drop value V D1 and the first rise value I D1 are used to obtain a first test impedance value R D1 , and the second drop value V D2 and the second rise value I D2 are used to obtain a second test impedance value R D2 , whereby the first test impedance value R D1 is greater than the second test impedance value R D2 , and since leakage current and drop value do not occur in a normal state, the test signal 124 corresponds to a third test impedance value R in a normal state, and both the first test impedance value R D1 and the second test impedance value R D2 are greater than the third test impedance value R, and the first test impedance value R D1 corresponds to a first abnormal state of the test signal 124, and the second test impedance value R D2 corresponds to a second abnormal state of the test signal 124, wherein the first test impedance value R D1 is 100 ohms (Ω) to 10 kilo ohms (kΩ), and the second test impedance value R D2 is 100 ohms (Ω) to 1 kiloohm (kΩ).

一併參閱第2圖、第4A圖與第4B圖,其為本發明之一實施例之檢測電路檢測待測電路之電路示意圖以及另一實施例之正常狀態與異常狀態之訊號曲線圖。如圖所示,檢測電路10更可讓電源量測單元14以升壓之測試電源P提供至待測電路30,進一步參閱第4A圖,以升壓之測試電源P提供至待測電路30的情況下,當感測電路12測得之電壓訊號V S與電流訊號I S於正常狀態時,不會出現訊號振盪起伏。而進一步參閱第4B圖,當待測電路30有異常狀態時,感測電路12即會透過探針元件122測得之測試訊號124之電壓訊號V S與電流訊號I S具有異常訊號,例如:一第一異常電壓值DV1、一第二異常電壓值DV2、一第一漏電流值DI1與一第二漏電流值DI2。 Referring to FIG. 2, FIG. 4A and FIG. 4B together, they are schematic diagrams of a detection circuit detecting a circuit to be tested according to one embodiment of the present invention and signal curves of a normal state and an abnormal state according to another embodiment. As shown in the figure, the detection circuit 10 can allow the power measurement unit 14 to provide the circuit to be tested 30 with a boosted test power P. Further referring to FIG. 4A, when the boosted test power P is provided to the circuit to be tested 30, when the voltage signal VS and the current signal IS measured by the sensing circuit 12 are in a normal state, there will be no signal oscillation. Further referring to FIG. 4B , when the circuit to be tested 30 has an abnormal state, the voltage signal VS and the current signal IS of the test signal 124 measured by the sensing circuit 12 through the probe element 122 have abnormal signals, for example: a first abnormal voltage value DV1, a second abnormal voltage value DV2, a first leakage current value DI1 and a second leakage current value DI2.

其中,第一異常電壓DV1與第一漏電流值DI1會出現在電壓訊號V S處於升壓階段,第二異常電壓值DV2與第二漏電流值DI2會出現在電壓訊號V S於飽和階段,也就是當測試電源P升壓至上限值時,相當於施加定電壓至待測電路30時會出現第二異常電壓值DV2與第二漏電流值DI2。 Among them, the first abnormal voltage DV1 and the first leakage current value DI1 will appear when the voltage signal VS is in the boost stage, and the second abnormal voltage value DV2 and the second leakage current value DI2 will appear when the voltage signal VS is in the saturation stage, that is, when the test power source P is boosted to the upper limit value, which is equivalent to applying a constant voltage to the circuit to be tested 30, the second abnormal voltage value DV2 and the second leakage current value DI2 will appear.

如第2圖所示,上述之實施例為控制處理單元20直接控制電源量測單元14,除此之外,本發明之檢測電路10更可進一步結合控制開關模組16,以控制測試電源P是否提供至待測電路30。As shown in FIG. 2 , in the above embodiment, the control processing unit 20 directly controls the power measurement unit 14 . In addition, the detection circuit 10 of the present invention can be further combined with a control switch module 16 to control whether the test power P is provided to the circuit under test 30 .

請參閱第5圖與第6圖,其為本發明之另一實施例之開關模組開路與開關模組導通之電路示意圖。如第5圖所示,當該開關模組16為開路時,該電源量測單元14並未能提供測試電源P至該待測電路30,而如第6圖所示,當開關模組16導通時,與該電源量測單元14即可將測試電源P提供至待測電路30,因此一併參閱第1圖,於步驟S30中,該電源量測單元14提供測試電源P,經輸出元件142供電至該待測電路30而對應產生測試訊號124至探針元件122,因而傳導至感測電路12,藉此傳導感測訊號SEN至控制處理單元20。Please refer to FIG. 5 and FIG. 6, which are circuit diagrams of the switch module open circuit and the switch module conductive circuit of another embodiment of the present invention. As shown in FIG. 5, when the switch module 16 is open circuit, the power measurement unit 14 cannot provide the test power P to the circuit to be tested 30, and as shown in FIG. 6, when the switch module 16 is conductive, the power measurement unit 14 can provide the test power P to the circuit to be tested 30. Therefore, referring to FIG. 1, in step S30, the power measurement unit 14 provides the test power P, which is supplied to the circuit to be tested 30 through the output element 142 and correspondingly generates a test signal 124 to the probe element 122, and then is transmitted to the sensing circuit 12, thereby transmitting the sensing signal SEN to the control processing unit 20.

其中,本實施例之開關模組16為一電晶體開關元件或複數個電晶體開關元件,例如:場效電晶體(FET)、雙極性電晶體(BJT)或介面場效電晶體(JFET),開關模組16為依據待測電路30之輸入端342與輸出端344之數量決定電晶體開關元件之數量。Among them, the switch module 16 of this embodiment is a transistor switch element or a plurality of transistor switch elements, such as: field effect transistor (FET), bipolar junction transistor (BJT) or joint field effect transistor (JFET), and the switch module 16 determines the number of transistor switch elements according to the number of input terminals 342 and output terminals 344 of the circuit 30 to be tested.

在測試電源P為定電壓且待測電路30為正常狀態的情況下,如第7A圖所示,測試電源P之高準位(ON)即在待測電路30之測試時間T S內,而開關控制訊號SW即表示開關模組16之切換期間,ON即表示開關模組16導通,OFF即表示開關模組16開路而截止,電壓訊號V S即表示感測電路12所取得之電壓準位,當出現正常阻值R時該電源量測單元14會將該測試電源P切換至一電壓源(例如:100V至350V電壓源),此時電壓訊號V S即未出現任何下降電位,其對應於待測電路30之一正常狀態。在測試電源P為定電壓且待測電路30為異常狀態的情況下,如第7B圖所示,當電壓訊號V S出現第一下降值V D1或第二下降值V D2以及電流訊號I S相對應出現第一上升值I D1或第二上升值I D2時,電源量測單元14將該測試電源P切換至一電流源,經輸出元件142供電至待測電路30。 When the test power source P is a constant voltage and the circuit to be tested 30 is in a normal state, as shown in FIG. 7A , the high level (ON) of the test power source P is within the test time TS of the circuit to be tested 30, and the switch control signal SW indicates the switching period of the switch module 16, ON indicates that the switch module 16 is turned on, and OFF indicates that the switch module 16 is open and cut off, and the voltage signal VS indicates the voltage level obtained by the sensing circuit 12. When the normal resistance R appears, the power measurement unit 14 will switch the test power source P to a voltage source (for example: a 100V to 350V voltage source). At this time, the voltage signal VS does not show any drop in potential, which corresponds to a normal state of the circuit to be tested 30. When the test power source P is a constant voltage and the circuit under test 30 is in an abnormal state, as shown in FIG. 7B , when the voltage signal VS shows a first decreasing value V D1 or a second decreasing value V D2 and the current signal IS shows a first increasing value ID1 or a second increasing value ID2 correspondingly, the power measurement unit 14 switches the test power source P to a current source, which supplies power to the circuit under test 30 through the output element 142.

在測試電源P為升壓電源且待測電路30為正常狀態的情況下,如第8A圖所示,在開關控制訊號SW之導通(ON)期間內,電壓訊號V S即未出現任何下降電位。在測試電源P為升壓電源且待測電路30為異常狀態的情況下,如第8B圖所示,當電壓訊號V S出現第一異常電壓值DV1或第二異常電壓值DV2時,電源量測單元14將該測試電源P切換至一電流源,經輸出元件142供電至待測電路30。 When the test power source P is a boost power source and the circuit under test 30 is in a normal state, as shown in FIG. 8A , during the conduction (ON) period of the switch control signal SW, the voltage signal VS does not show any drop in potential. When the test power source P is a boost power source and the circuit under test 30 is in an abnormal state, as shown in FIG. 8B , when the voltage signal VS shows a first abnormal voltage value DV1 or a second abnormal voltage value DV2, the power measurement unit 14 switches the test power source P to a current source, which supplies power to the circuit under test 30 via the output element 142.

因此由以上所述之實施例可知,本發明藉由在待測電路之至少一線路之一線路材料特性對應之一測試時間內完成測試,因而測得對應之測試訊號124,即取得對應之電壓訊號V S與電流訊號I S,因而避免測試時間短於待測電路之至少一線路之極化反應時間,也就是避免漏測線路受外電場而極化的情況下發生電位變化及對應之電流變化,因而讓測試時間可大於極化反應時間。 Therefore, it can be known from the embodiments described above that the present invention completes the test within a test time corresponding to a line material characteristic of at least one line of the circuit to be tested, thereby measuring the corresponding test signal 124, that is, obtaining the corresponding voltage signal VS and current signal IS , thereby avoiding the test time being shorter than the polarization reaction time of at least one line of the circuit to be tested, that is, avoiding the occurrence of potential changes and corresponding current changes when the missed test line is polarized by an external electric field, thereby allowing the test time to be greater than the polarization reaction time.

綜上所述,本發明提供一種檢測電路之檢測方法,其藉由提供一測試電源至一待測電路並將一探針元件耦接至待測電路,並於待測電路之線路的一線路材料特性對應之測試時間內取得一測試訊號,藉此取得待測電路之可量化數據並在待測電路對應之測試時間內完成測試,因而避免誤差或錯誤。In summary, the present invention provides a testing method for a testing circuit, which provides a testing power supply to a circuit to be tested and couples a probe element to the circuit to be tested, and obtains a testing signal within a testing time corresponding to a line material characteristic of the line of the circuit to be tested, thereby obtaining quantifiable data of the circuit to be tested and completing the test within the testing time corresponding to the circuit to be tested, thereby avoiding errors or mistakes.

故本發明實為一具有新穎性、進步性及可供產業上利用者,應符合我國專利法專利申請要件無疑,爰依法提出發明專利申請,祈  鈞局早日賜准專利,至感為禱。Therefore, this invention is novel, progressive and can be used in the industry. It should undoubtedly meet the patent application requirements of the Patent Law of our country. Therefore, we have filed an invention patent application in accordance with the law and pray that the Bureau will approve the patent as soon as possible. I am deeply grateful.

惟以上所述者,僅為本發明之較佳實施例而已,並非用來限定本發明實施之範圍,舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾,均應包括於本發明之申請專利範圍內。However, the above is only a preferred embodiment of the present invention and is not intended to limit the scope of implementation of the present invention. All equivalent changes and modifications made according to the shape, structure, features and spirit described in the patent application scope of the present invention should be included in the patent application scope of the present invention.

10:檢測電路 12:感測電路 122:探針元件 124:測試訊號 14:電源量測單元 142:輸出元件 16:開關模組 20:處理單元 30:待測電路 32:電子元件 34:線路 342:輸入端 344:輸出端 CTRL:控制訊號 DI1:第一漏電流值 DI2:第二漏電流值 DV1:第一異常電壓值 DV2:第二異常電壓值 I D1:第一上升值 I D2:第二上升值 I S:電流訊號 P:測試電源 SEN:感測訊號 SW:切換控制訊號 TH1:第一門檻值 TH2:第二門檻值 V D1:第一下降值 V D2:第二下降值 V S:電壓訊號 10: Detection circuit 12: Sensing circuit 122: Probe element 124: Test signal 14: Power measurement unit 142: Output element 16: Switch module 20: Processing unit 30: Circuit to be tested 32: Electronic element 34: Line 342: Input end 344: Output end CTRL: Control signal DI1: First leakage current value DI2: Second leakage current value DV1: First abnormal voltage value DV2: Second abnormal voltage value ID1 : First rising value ID2 : Second rising value IS : Current signal P: Test power SEN: Sensing signal SW: Switching control signal TH1: First threshold value TH2: Second threshold value VD1 : First falling value VD2 : Second falling value VS : Voltage signal

第1圖:其為本發明之一實施例之流程圖; 第2圖:其為本發明之一實施例之檢測電路檢測待測電路之電路示意圖; 第3A圖:其為本發明之一實施例之正常狀態之訊號曲線圖; 第3B圖:其為本發明之一實施例之異常狀態之訊號曲線圖; 第4A圖:其為本發明之另一實施例之正常狀態之訊號曲線圖; 第4B圖:其為本發明之另一實施例之異常狀態之訊號曲線圖; 第5圖:其為本發明之另一實施例之開關模組開路之示意圖; 第6圖:其為本發明之另一實施例之開關模組導通之示意圖; 第7A圖:其為本發明之另一實施例之正常狀態之訊號曲線圖; 第7B圖:其為本發明之另一實施例之異常狀態之訊號曲線圖; 第8A圖:其為本發明之另一實施例之正常狀態之訊號曲線圖;以及 第8B圖:其為本發明之另一實施例之異常狀態之訊號曲線圖。 Figure 1: It is a flow chart of one embodiment of the present invention; Figure 2: It is a schematic diagram of a detection circuit of one embodiment of the present invention detecting a circuit to be tested; Figure 3A: It is a signal curve diagram of a normal state of one embodiment of the present invention; Figure 3B: It is a signal curve diagram of an abnormal state of one embodiment of the present invention; Figure 4A: It is a signal curve diagram of a normal state of another embodiment of the present invention; Figure 4B: It is a signal curve diagram of an abnormal state of another embodiment of the present invention; Figure 5: It is a schematic diagram of an open circuit of a switch module of another embodiment of the present invention; Figure 6: It is a schematic diagram of a conductive switch module of another embodiment of the present invention; Figure 7A: It is a signal curve diagram of a normal state of another embodiment of the present invention; Figure 7B: It is a signal curve diagram of an abnormal state of another embodiment of the present invention; Figure 8A: It is a signal curve diagram of a normal state of another embodiment of the present invention; and Figure 8B: It is a signal curve diagram of an abnormal state of another embodiment of the present invention.

10:檢測電路 10: Detection circuit

12:感測電路 12: Sensing circuit

122:探針元件 122: Probe element

124:測試訊號 124: Test signal

14:電源量測單元 14: Power measurement unit

142:輸出元件 142: Output element

20:處理單元 20: Processing unit

30:待測電路 30: Circuit to be tested

32:電子元件 32: Electronic components

34:線路 34: Line

342:輸入端 342: Input port

344:輸出端 344: Output terminal

CTRL:控制訊號 CTRL: control signal

P:測試電源 P: Test power supply

SEN:感測訊號 SEN: Sensing signal

Claims (10)

一種檢測電路之檢測方法,其應用於檢測一待測電路,該待測電路上設有至少一線路,該檢測電路之檢測方法包含: 提供一測試電源傳導至該待測電路之該至少一線路之一輸入端; 利用至少一探針元件耦接該待測電路之該至少一線路之一輸出端; 該待測電路於一測試時間內經由該至少一探針元件耦接並產生一測試訊號; 其中,該測試時間對應於該至少一線路之一線路材料特性。 A detection method for a detection circuit is applied to detect a circuit to be tested, wherein the circuit to be tested has at least one line, and the detection method for the detection circuit comprises: Providing a test power source to transmit to an input end of the at least one line of the circuit to be tested; Using at least one probe element to couple an output end of the at least one line of the circuit to be tested; The circuit to be tested is coupled by the at least one probe element within a test time and generates a test signal; Wherein, the test time corresponds to a line material characteristic of the at least one line. 如請求項1所述之檢測電路之檢測方法,其中當該測試訊號於一升壓階段且該降壓數值大於一第一門檻值時,該測試訊號為對應於該待測電路之一第一異常狀態,當該測試訊號於一飽和階段且該降壓數值大於一第二門檻值時,該測試訊號為對應於該待測電路之一第二異常狀態。A detection method for a detection circuit as described in claim 1, wherein when the test signal is in a boost phase and the voltage drop value is greater than a first threshold value, the test signal corresponds to a first abnormal state of the circuit to be tested, and when the test signal is in a saturation phase and the voltage drop value is greater than a second threshold value, the test signal corresponds to a second abnormal state of the circuit to be tested. 如請求項2所述之檢測電路之檢測方法,其中該測試訊號於一第一異常狀態之一第一測試阻抗值大於該測試訊號於一第二異常狀態之一第二測試阻抗值。A detection method for a detection circuit as described in claim 2, wherein a first test impedance value of the test signal in a first abnormal state is greater than a second test impedance value of the test signal in a second abnormal state. 如請求項2所述之檢測電路之檢測方法,其中該第一測試阻抗值與該第二測試阻抗值大於該測試訊號於一正常狀態之一第三測試阻抗值。A detection method for a detection circuit as described in claim 2, wherein the first test impedance value and the second test impedance value are greater than a third test impedance value of the test signal in a normal state. 如請求項3或4所述之檢測電路之檢測方法,其中該第一測試阻抗值為100歐姆至10千歐姆。A detection method for a detection circuit as described in claim 3 or 4, wherein the first test impedance value is 100 ohms to 10 kiloohms. 如請求項1所述之檢測電路之檢測方法,其中該測試電源為100伏特至350伏特。A method for testing a test circuit as described in claim 1, wherein the test power source is 100 volts to 350 volts. 如請求項1所述之檢測電路之檢測方法,其中該測試時間大於該待測電路之一極化反應時間。A method for testing a test circuit as described in claim 1, wherein the test time is greater than a polarization reaction time of the circuit to be tested. 如請求項7所述之檢測電路之檢測方法,其中該線路材料特性具有一極化參數,該極化參數對應於該極化反應時間。A detection method for a detection circuit as described in claim 7, wherein the circuit material characteristic has a polarization parameter, and the polarization parameter corresponds to the polarization reaction time. 如請求項1所述之檢測電路之檢測方法,其中該測試電源為一電流源,該測試電流為5毫安培至20毫安培。A detection method for a detection circuit as described in claim 1, wherein the test power source is a current source, and the test current is 5 mA to 20 mA. 如請求項1所述之檢測電路之檢測方法,其中該至少一線路更耦接一電子元件。A detection method for a detection circuit as described in claim 1, wherein the at least one circuit is further coupled to an electronic component.
TW112100188A 2023-01-04 Method for detecting of detection circuit TWI848501B (en)

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TWI848501B TWI848501B (en) 2024-07-11
TW202429087A true TW202429087A (en) 2024-07-16

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