TW202425072A - 基板積層體的製造方法及半導體裝置 - Google Patents

基板積層體的製造方法及半導體裝置 Download PDF

Info

Publication number
TW202425072A
TW202425072A TW112128219A TW112128219A TW202425072A TW 202425072 A TW202425072 A TW 202425072A TW 112128219 A TW112128219 A TW 112128219A TW 112128219 A TW112128219 A TW 112128219A TW 202425072 A TW202425072 A TW 202425072A
Authority
TW
Taiwan
Prior art keywords
substrate
substrate laminate
organic material
layer
material layer
Prior art date
Application number
TW112128219A
Other languages
English (en)
Chinese (zh)
Inventor
茅場靖剛
岡太航
中村雄三
高村一夫
四釜拓生
田村佳保里
古正力亜
Original Assignee
日商三井化學股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商三井化學股份有限公司 filed Critical 日商三井化學股份有限公司
Publication of TW202425072A publication Critical patent/TW202425072A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6684—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H10P14/6686—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01351—Changing the shapes of die-attach connectors
    • H10W72/01359—Changing the shapes of die-attach connectors by planarisation, e.g. chemical-mechanical polishing [CMP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01951—Changing the shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Landscapes

  • Laminated Bodies (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Geometry (AREA)
  • Spectroscopy & Molecular Physics (AREA)
TW112128219A 2022-08-01 2023-07-27 基板積層體的製造方法及半導體裝置 TW202425072A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2022-122934 2022-08-01
JP2022122934 2022-08-01
JP2023-018757 2023-02-09
JP2023018757 2023-02-09

Publications (1)

Publication Number Publication Date
TW202425072A true TW202425072A (zh) 2024-06-16

Family

ID=89848955

Family Applications (1)

Application Number Title Priority Date Filing Date
TW112128219A TW202425072A (zh) 2022-08-01 2023-07-27 基板積層體的製造方法及半導體裝置

Country Status (5)

Country Link
JP (1) JPWO2024029390A1 (https=)
KR (1) KR20250031210A (https=)
CN (1) CN119654696A (https=)
TW (1) TW202425072A (https=)
WO (1) WO2024029390A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2025005084A1 (https=) * 2023-06-28 2025-01-02
WO2025204961A1 (ja) * 2024-03-29 2025-10-02 Jsr株式会社 電子装置の製造方法及び電子装置
WO2025229932A1 (ja) * 2024-04-30 2025-11-06 三井化学株式会社 構造体の製造方法及び構造体、積層体の製造方法
WO2026078823A1 (ja) * 2024-10-09 2026-04-16 株式会社レゾナック 半導体装置の製造方法
WO2026078856A1 (ja) * 2024-10-10 2026-04-16 株式会社レゾナック 半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57113231A (en) * 1980-12-29 1982-07-14 Seiko Epson Corp Semiconductor device
JPS6130059A (ja) * 1984-07-20 1986-02-12 Nec Corp 半導体装置の製造方法
JPS63102265A (ja) * 1986-10-20 1988-05-07 Agency Of Ind Science & Technol 半導体装置の製造方法
JP2018195656A (ja) * 2017-05-16 2018-12-06 ソニーセミコンダクタソリューションズ株式会社 半導体装置の製造方法及び半導体装置
IT201700053902A1 (it) * 2017-05-18 2018-11-18 Lfoundry Srl Metodo di bonding ibrido per wafer a semiconduttore e relativo dispositivo integrato tridimensionale
US11289421B2 (en) * 2019-09-26 2022-03-29 Intel Corporation Methods and structures for improved electrical contact between bonded integrated circuit interfaces

Also Published As

Publication number Publication date
WO2024029390A1 (ja) 2024-02-08
CN119654696A (zh) 2025-03-18
JPWO2024029390A1 (https=) 2024-02-08
KR20250031210A (ko) 2025-03-06

Similar Documents

Publication Publication Date Title
TWI856982B (zh) 基板積層體的製造方法及積層體
TW202425072A (zh) 基板積層體的製造方法及半導體裝置
JP7351019B2 (ja) 組成物、積層体及び積層体の製造方法
JP7772806B2 (ja) 半導体用の膜を形成するための組成物、積層体及び基板積層体
JP7761656B2 (ja) 半導体用の膜を形成するための組成物、積層体及び基板積層体
JP7833546B2 (ja) 基板積層体の製造方法及び基板積層体
JP2023177917A (ja) 半導体装置およびその製造方法
TW202438303A (zh) 基板積層體的製造方法
KR20250139320A (ko) 수지층 구비 반도체 칩의 제조 방법 및 기판 적층체의 제조 방법
JP2025064295A (ja) 基板積層体の製造方法
WO2024172044A1 (ja) 基板積層体の製造方法、積層体、及び基板積層体
TW202501550A (zh) 基板積層體
TW202450057A (zh) 半導體結構體及其製造方法
TW202433619A (zh) 半導體結構體及其製造方法
TW202503996A (zh) 半導體結構體及其製造方法