CN119654696A - 基板层叠体的制造方法及半导体装置 - Google Patents

基板层叠体的制造方法及半导体装置 Download PDF

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Publication number
CN119654696A
CN119654696A CN202380056974.9A CN202380056974A CN119654696A CN 119654696 A CN119654696 A CN 119654696A CN 202380056974 A CN202380056974 A CN 202380056974A CN 119654696 A CN119654696 A CN 119654696A
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CN
China
Prior art keywords
substrate
organic material
layer
material layer
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202380056974.9A
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English (en)
Chinese (zh)
Inventor
茅场靖刚
冈太航
中村雄三
高村一夫
四釜拓生
田村佳保里
古正力亚
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Mitsui Chemicals Inc
Original Assignee
Mitsui Chemicals Inc
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Filing date
Publication date
Application filed by Mitsui Chemicals Inc filed Critical Mitsui Chemicals Inc
Publication of CN119654696A publication Critical patent/CN119654696A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6684—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H10P14/6686—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01351—Changing the shapes of die-attach connectors
    • H10W72/01359—Changing the shapes of die-attach connectors by planarisation, e.g. chemical-mechanical polishing [CMP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01951—Changing the shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Landscapes

  • Laminated Bodies (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Geometry (AREA)
  • Spectroscopy & Molecular Physics (AREA)
CN202380056974.9A 2022-08-01 2023-07-24 基板层叠体的制造方法及半导体装置 Pending CN119654696A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2022-122934 2022-08-01
JP2022122934 2022-08-01
JP2023-018757 2023-02-09
JP2023018757 2023-02-09
PCT/JP2023/027080 WO2024029390A1 (ja) 2022-08-01 2023-07-24 基板積層体の製造方法及び半導体装置

Publications (1)

Publication Number Publication Date
CN119654696A true CN119654696A (zh) 2025-03-18

Family

ID=89848955

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202380056974.9A Pending CN119654696A (zh) 2022-08-01 2023-07-24 基板层叠体的制造方法及半导体装置

Country Status (5)

Country Link
JP (1) JPWO2024029390A1 (https=)
KR (1) KR20250031210A (https=)
CN (1) CN119654696A (https=)
TW (1) TW202425072A (https=)
WO (1) WO2024029390A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2025005084A1 (https=) * 2023-06-28 2025-01-02
WO2025204961A1 (ja) * 2024-03-29 2025-10-02 Jsr株式会社 電子装置の製造方法及び電子装置
WO2025229932A1 (ja) * 2024-04-30 2025-11-06 三井化学株式会社 構造体の製造方法及び構造体、積層体の製造方法
WO2026078823A1 (ja) * 2024-10-09 2026-04-16 株式会社レゾナック 半導体装置の製造方法
WO2026078856A1 (ja) * 2024-10-10 2026-04-16 株式会社レゾナック 半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57113231A (en) * 1980-12-29 1982-07-14 Seiko Epson Corp Semiconductor device
JPS6130059A (ja) * 1984-07-20 1986-02-12 Nec Corp 半導体装置の製造方法
JPS63102265A (ja) * 1986-10-20 1988-05-07 Agency Of Ind Science & Technol 半導体装置の製造方法
JP2018195656A (ja) * 2017-05-16 2018-12-06 ソニーセミコンダクタソリューションズ株式会社 半導体装置の製造方法及び半導体装置
IT201700053902A1 (it) * 2017-05-18 2018-11-18 Lfoundry Srl Metodo di bonding ibrido per wafer a semiconduttore e relativo dispositivo integrato tridimensionale
US11289421B2 (en) * 2019-09-26 2022-03-29 Intel Corporation Methods and structures for improved electrical contact between bonded integrated circuit interfaces

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Publication number Publication date
WO2024029390A1 (ja) 2024-02-08
JPWO2024029390A1 (https=) 2024-02-08
TW202425072A (zh) 2024-06-16
KR20250031210A (ko) 2025-03-06

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