TW202416120A - Method and computer program product and apparatus for scheduling and executing host data-update commands - Google Patents
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Description
本發明涉及儲存裝置,尤指一種排程和執行主機資料更新命令的方法、電腦程式產品及裝置。The present invention relates to a storage device, and more particularly to a method, a computer program product and a device for scheduling and executing host data update commands.
閃存通常分為NOR閃存與NAND閃存。NOR閃存為隨機存取裝置,主機端(Host Side)可於位址腳位上提供任何存取NOR閃存的位址,並及時地從NOR閃存的資料腳位上獲得儲存於該位址上的資料。相反地,NAND閃存並非隨機存取,而是序列存取。NAND閃存無法像NOR閃存一樣,可以存取任何隨機位址,主機端反而需要寫入序列的位元組(Bytes)的值到NAND閃存中,用於定義請求命令(Command)的類型(如,讀取、寫入、丟棄、抹除等),以及用在此命令上的位址。位址可指向一個頁面(閃存中寫入作業的最小資料塊)或一個區塊(閃存中抹除作業的最小資料塊)。然而,為了提昇閃存模組的資料更新效能,主機資料更新命令的執行順序可能和主機端發出的用於更新資料的相應主機命令的順序不同,因而可能發生髒寫入(Dirty Write)的情況。本發明提出一種排程和執行主機資料更新命令的方法、電腦程式產品及裝置,用於避免髒寫入的錯誤。Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The host side can provide any address to access the NOR flash memory on the address pins and obtain the data stored at the address from the data pins of the NOR flash memory in a timely manner. In contrast, NAND flash memory is not randomly accessed, but sequentially accessed. NAND flash memory cannot access any random address like NOR flash memory. Instead, the host side needs to write the value of the sequence of bytes into the NAND flash memory to define the type of request command (such as read, write, discard, erase, etc.) and the address used in this command. The address can point to a page (the smallest data block for writing operations in flash memory) or a block (the smallest data block for erasing operations in flash memory). However, in order to improve the data update performance of the flash memory module, the execution order of the host data update command may be different from the order of the corresponding host command issued by the host end for updating data, so dirty writes may occur. The present invention provides a method, a computer program product and a device for scheduling and executing host data update commands to avoid dirty write errors.
有鑑於此,如何減輕或消除上述相關領域的缺失,實為有待解決的問題。In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related areas is indeed a problem to be solved.
本說明書涉及一種排程和執行主機資料更新命令的方法,由處理單元執行,包含:依據從主機端接收的用於更新資料的主機命令的類型和參數,產生第三主機資料更新命令,並且標記為第一類型的主機資料更新命令;因應第三主機資料更新命令中的第三邏輯位址相同於第一佇列中的多個第一主機資料更新命令中的一個的第一邏輯位址的情況,將重複的第一邏輯位址從匹配的第一主機資料更新命令中移除;因應第三主機資料更新命令中的第三邏輯位址相同於第二佇列中的多個第二主機資料更新命令中的一個的第二邏輯位址的情況,將重複的第二邏輯位址從匹配的第二主機資料更新命令中移除;以及將第三主機更新命令推入第一佇列。The present invention relates to a method for scheduling and executing a host data update command, which is executed by a processing unit and includes: generating a third host data update command according to the type and parameters of a host command for updating data received from a host end, and marking the third host data update command as a host data update command of the first type; in response to a third logical address in the third host data update command being the same as one of the plurality of first host data update commands in the first queue; In response to a situation where the third logical address in the third host data update command is the same as the second logical address of one of the plurality of second host data update commands in the second queue, the duplicate second logical address is removed from the matching second host data update command; and the third host update command is pushed into the first queue.
本說明書另涉及一種電腦程式產品,包含程式碼。當處理單元執行所述程式碼時,實施如上所述的排程和執行主機資料更新命令的方法。The present specification also relates to a computer program product, comprising program codes. When a processing unit executes the program codes, the method of scheduling and executing host data update commands as described above is implemented.
本說明書還另涉及一種排程和執行主機資料更新命令的裝置,包含:隨機存取記憶體,配置空間給第一佇列和第二佇列;以及處理單元,耦接隨機存取記憶體。處理單元用於依據從主機端接收的用於更新資料的主機命令的類型和參數,產生第三主機資料更新命令,並且標記為第一類型的主機資料更新命令;因應第三主機資料更新命令中的第三邏輯位址相同於第一佇列中的多個第一主機資料更新命令中的一個的第一邏輯位址的情況,將重複的第一邏輯位址從匹配的第一主機資料更新命令中移除;因應第三主機資料更新命令中的第三邏輯位址相同於第二佇列中的多個第二主機資料更新命令中的一個的第二邏輯位址的情況,將重複的第二邏輯位址從匹配的第二主機資料更新命令中移除;以及將第三主機更新命令推入第一佇列。The present specification also relates to a device for scheduling and executing host data update commands, including: a random access memory, which allocates space for a first queue and a second queue; and a processing unit, which is coupled to the random access memory. The processing unit is used to generate a third host data update command according to the type and parameters of the host command for updating data received from the host end, and mark it as a host data update command of the first type; in response to the situation that the third logical address in the third host data update command is the same as the first logical address of one of the multiple first host data update commands in the first queue, remove the duplicate first logical address from the matching first host data update command; in response to the situation that the third logical address in the third host data update command is the same as the second logical address of one of the multiple second host data update commands in the second queue, remove the duplicate second logical address from the matching second host data update command; and push the third host update command into the first queue.
上述實施例的優點之一,通過如上所述的排程和執行主機資料更新命令的方法,可避免因為主機資料更新命令的執行順序和主機端發出的用於更新資料的相應主機命令的順序不同,而發生髒寫入的錯誤。One of the advantages of the above embodiment is that, by scheduling and executing the host data update command as described above, dirty write errors can be avoided due to the difference between the execution order of the host data update command and the order of the corresponding host commands issued by the host end for updating data.
本發明的其他優點將搭配以下的說明和圖式進行更詳細的解說。Other advantages of the present invention will be explained in more detail with the following description and drawings.
以下說明為完成發明的較佳實現方式,其目的在於描述本發明的基本精神,但並不用以限定本發明。實際的發明內容必須參考之後的權利要求範圍。The following description is a preferred implementation of the invention, and its purpose is to describe the basic spirit of the invention, but it is not intended to limit the invention. The actual content of the invention must refer to the scope of the following claims.
必須了解的是,使用於本說明書中的「包含」、「包括」等詞,用以表示存在特定的技術特徵、數值、方法步驟、作業處理、元件以及/或組件,但並不排除可加上更多的技術特徵、數值、方法步驟、作業處理、元件、組件,或以上的任意組合。It must be understood that the words "comprise", "include" and the like used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, operation processes, elements and/or components, but do not exclude the addition of more technical features, numerical values, method steps, operation processes, elements, components, or any combination thereof.
於權利要求中使用如「第一」、「第二」、「第三」等詞是用來修飾權利要求中的元件,並非用來表示之間具有優先順序,前置關係,或者是一個元件先於另一個元件,或者是執行方法步驟時的時間先後順序,僅用來區別具有相同名字的元件。The terms "first", "second", "third", etc. used in the claims are used to modify the elements in the claims, and are not used to indicate a priority order, a preceding relationship, or that one element precedes another element, or a temporal sequence in performing method steps. They are only used to distinguish elements with the same name.
必須了解的是,當元件描述為「連接」或「耦接」至另一元件時,可以是直接連結、或耦接至其他元件,可能出現中間元件。相反地,當元件描述為「直接連接」或「直接耦接」至另一元件時,其中不存在任何中間元件。使用來描述元件之間關係的其他語詞也可類似方式解讀,例如「介於」相對於「直接介於」,或者是「鄰接」相對於「直接鄰接」等等。It should be understood that when an element is described as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, and there may be intervening elements. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements may also be interpreted in a similar manner, such as "between" versus "directly between", or "adjacent" versus "directly adjacent", etc.
參考圖1。電子裝置10包含主機端(Host Side)110、閃存控制器130及閃存模組150,並且閃存控制器130及閃存模組150可合稱為裝置端(Device Side)。電子裝置10可實施於個人電腦、筆記型電腦(Laptop PC)、平板電腦、手機、數位相機、數位攝影機、智慧電視、智慧電冰箱等電子產品之中。主機端110與閃存控制器130的主機介面(Host Interface)137可以通用序列匯流排(Universal Serial Bus,USB)、先進技術附著(advanced technology attachment,ATA)、序列先進技術附著(serial advanced technology attachment,SATA)、快速周邊元件互聯(peripheral component interconnect express,PCI-E)、通用快閃記憶儲存(Universal Flash Storage,UFS)、嵌入式多媒體卡(Embedded Multi-Media Card,eMMC)等通訊協定彼此溝通。閃存控制器130的閃存介面(Flash Interface)139與閃存模組150可以雙倍資料率(Double Data Rate,DDR)通訊協定彼此溝通,例如,開放NAND快閃(Open NAND Flash Interface,ONFI)、雙倍資料率開關(DDR Toggle)或其他通訊協定。閃存控制器130包含處理單元134,可使用多種方式實施,如使用通用硬體(例如,單一處理器、具平行處理能力的多處理器、圖形處理器或其他具運算能力的處理器),並且在執行軟體以及/或韌體指令時,提供之後描述的功能。處理單元134通過主機介面131接收主機命令,例如寫入命令(Write Command)、丟棄命令(Discard Command)、抹寫命令(Erase Command)等,依據主機命令的類型和其中攜帶參數產生主機資料更新命令(Host Data-update Command),排程並執行這些命令。閃存控制器130另包含隨機存取記憶體(Random Access Memory, RAM)136,可實施為動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)、靜態隨機存取記憶體(Static Random Access Memory,SRAM)或上述兩者的結合,用於配置空間作為資料緩衝區,儲存從主機端110讀取並即將寫入閃存模組150的使用者資料(也可稱為主機資料),以及從閃存模組150讀取並即將輸出給主機端110的使用者資料。隨機存取記憶體136另可儲存執行過程中需要的資料,例如,變數、資料表、主機-閃存對照表(Host-to-Flash/H2F Table)、閃存-主機對照表(Flash-to-Host/F2H Table)等。閃存介面139包含NAND閃存控制器(NAND Flash Controller,NFC),提供存取閃存模組150時需要的功能,例如命令序列器(Command Sequencer)、低密度奇偶校驗(Low Density Parity Check,LDPC)等。Referring to FIG. 1 , the
閃存控制器130中可配置匯流排架構(Bus Architecture)132,用於讓元件之間彼此耦接以傳遞資料、位址、控制訊號等,這些元件包含主機介面131、處理單元134、RAM 136、直接記憶體存取(Direct Memory Access,DMA)控制器138、閃存介面139等。DMA控制器138可依據處理單元134的指令,通過匯流排架構132在元件間遷移資料,例如,將主機介面131或閃存介面139中特定資料緩存器(Data Buffer)的資料搬到RAM 136中的特定位址,將RAM 136中特定位址的資料搬到將主機介面131或閃存介面139中的特定資料緩存器等。The
閃存模組150提供大量的儲存空間,通常是數百個千兆位元組(Gigabytes,GB),甚至是數個萬億位元組(Terabytes,TB),用於儲存大量的使用者資料,例如高解析度圖片、影片等。閃存模組150中包含控制電路以及記憶體陣列,記憶體陣列中的記憶單元可組態為單層式單元(Single Level Cells, SLCs)、多層式單元(Multiple Level Cells, MLCs)三層式單元(Triple Level Cells, TLCs)、四層式單元(Quad-Level Cells QLCs)或上述的任意組合。處理單元134通過閃存介面139寫入使用者資料到閃存模組150中的指定位址(目的位址),以及從閃存模組150中的指定位址(來源位址)讀取使用者資料。閃存介面139使用數個電子訊號來協調閃存控制器130與閃存模組150間的資料與命令傳遞,包含資料線(Data Line)、時脈訊號(Clock Signal)與控制訊號(Control Signal)。資料線可用於傳遞命令、位址、讀出及寫入的資料;控制訊號線可用於傳遞晶片致能(Chip Enable,CE)、位址提取致能(Address Latch Enable,ALE)、命令提取致能(Command Latch Enable,CLE)、寫入致能(Write Enable,WE)等控制訊號。The
參考圖2,閃存模組150中的介面151可包含四個輸出入通道(I/O channels,以下簡稱通道)CH#0至CH#3,每一個通道連接四個NAND閃存單元,例如,通道CH#0連接NAND閃存單元153#0、153#4、153#8及153#12。每個NAND閃存單元可封裝為獨立的芯片(die)。閃存介面139可通過介面151發出致能訊號CE#0至CE#3中的一個來致能NAND閃存單元153#0至153#3、153#4至153#7、153#8至153#11、或153#12至153#15,接著以並行的方式從致能的NAND閃存單元讀取使用者資料,或者寫入使用者資料至致能的NAND閃存單元。2, the
為了提升資料更新的效率,閃存控制器130可將資料更新的長而連續的主機命令和短而分散的主機命令分開排程及執行。閃存控制器130依據主機命令的類型和其中攜帶參數產生主機資料更新命令,並且主機資料更新命令可表示為以下的資料結構:{SN, LA, Len, PA},其中,SN代表主機命令的序號,LA代表開始邏輯位址,Len代表邏輯位址的長度,PA代表開始實體位址。主機命令的序號可代表主機命令到達閃存控制器130的時間順序,數字越小代表越早到達閃存控制器130。邏輯位址可為邏輯區塊位址(Logical Block Address,LBA)、主機頁面編號(Host Page Number)等。一個邏輯區塊位址可指向512K位元組的資料,而一個主機頁面可指向八個連續的邏輯區塊位址(也就是4K位元組)的資料。實體位址可包含通道編號、邏輯單位號(Logical Unit Number,LUN)、頁面編號、區段編號,或者以上的任意組合的資訊,能夠讓閃存介面139解譯來和閃存模組150進行一系列的訊號交互,完成特定的資料寫入操作。當實體位址為全“0”(也就是空值NULL)時,代表此資料更新命令是根據主機丟棄命令或者主機抹寫命令所產生的。當實體位址能夠被閃存介面139解譯出時,代表此資料更新命令是根據主機寫入命令所產生的。舉例來說,根據LBA#100~LBA#115的主機寫入命令,可產生主機資料更新命令{1, 100, 16, PA={CH#0, LUN#1, P#0~P#1}},其中的實體位址可由閃存控制器130依據閃存模組150的實體設置和預設的規則來指派。根據LBA#100~LBA#115的主機丟棄或者抹寫命令,可產生資料更新命令{2, 100, 16, PA=NULL}。In order to improve the efficiency of data update, the
參考圖3,RAM 136配置空間給順序更新命令佇列(Sequential-update Command Queue,SCQ)310,用於依照到達閃存控制器130的時間順序儲存主機端110發送的順序主機資料更新命令,例如邏輯區塊位址長度(Logical Block Address,LBA Length)大於1的主機資料更新命令。RAM 136還配置空間給隨機更新命令佇列(Random-update Command Queue,RCQ)330,用於依照到達閃存控制器130的時間順序儲存主機端110發送的隨機主機資料更新命令,例如LBA長度等於1的主機資料更新命令。順序更新命令佇列310和隨機更新命令佇列330中的任何一個可儲存數百或者數千筆的主機資料更新命令。順序更新命令佇列310和隨機更新命令佇列330可為循環式佇列(Cyclical Queue),其操作基本原則是由結束位置(如指標T所指的位置)新增主機資料更新命令(可稱為入列),並且由開始位置(如指標H所指的位置)移出主機資料更新命令(可稱為出列)。也就是說,第一個新增至佇列的命令,也將會是第一個被移出和處理的,符合先進先出(First-In First-Out,FIFO)的原則。3 , the
舉例來說,處理單元134在執行韌體轉換層(Firmware Translation Layer,FTL)的程式碼時,完成如下的主機資料更新命令的產生和入列:首先,通過主機介面131依序收到5個主機寫入命令:W1={LBA#200~215,D1};W2={LBA#300,D2}:W3={LBA#400~415,D3}:W4={LBA#300~315,D4}:W5={LBA#200}。主機寫入命令W1指示寫入邏輯位址LBA#200~215的資料D1,主機寫入命令W2指示寫入邏輯位址LBA#300的資料D2,主機寫入命令W3指示寫入邏輯位址LBA#400~415的資料D3,主機寫入命令W4指示寫入邏輯位址LBA#300~315的資料D4,主機寫入命令W5指示寫入邏輯位址LBA#200的資料D5。接著,分別為主機寫入命令W1至W5產生主機資料更新命令DU1={1, 200, 16, PA#1};DU2={2, 300, 1, PA#2};DU3={3, 400, 16, PA#3};DU4={4, 300, 16, PA#4};DU5={5, 200, 1, PA#5}。經過更新類型的判斷,依序將主機資料更新命令DU1、DU3、DU4(可稱為順序更新命令,Sequential Update Command,SUC)推入順序更新命令佇列310,將主機資料更新命令DU2、DU5(可稱為隨機更新命令,Random Update Command,RUC)推入隨機更新命令佇列330。For example, when the processing unit 134 executes the firmware translation layer (FTL) code, it completes the generation and enqueue of the following host data update command: First, five host write commands are received in sequence through the host interface 131: W1={LBA#200~215,D1}; W2={LBA#300,D2}: W3={LBA#400~415,D3}: W4={LBA#300~315,D4}: W5={LBA#200}. The host write command W1 instructs writing data D1 to the logical address LBA#200~215, the host write command W2 instructs writing data D2 to the logical address LBA#300, the host write command W3 instructs writing data D3 to the logical address LBA#400~415, the host write command W4 instructs writing data D4 to the logical address LBA#300~315, and the host write command W5 instructs writing data D5 to the logical address LBA#200. Then, host data update commands DU1={1, 200, 16, PA#1}; DU2={2, 300, 1, PA#2}; DU3={3, 400, 16, PA#3}; DU4={4, 300, 16, PA#4}; DU5={5, 200, 1, PA#5} are generated for host write commands W1 to W5 respectively. After determining the update type, host data update commands DU1, DU3, and DU4 (which may be referred to as sequential update commands, SUC) are pushed into sequential
主機資料更新命令DU2={2, 300, 1, PA#2}和主機資料更新命令DU4={4, 300, 16, PA#4}中含有相同的邏輯位址LBA#300,而且DU2必須早於DU4被執行。主機資料更新命令DU1={1, 200, 16, PA#1}和主機資料更新命令DU5={5, 200, 1, PA#5}中含有相同的邏輯位址LBA#200,而且DU1必須早於DU5被執行。The host data update command DU2={2, 300, 1, PA#2} and the host data update command DU4={4, 300, 16, PA#4} contain the same logical address LBA#300, and DU2 must be executed before DU4. The host data update command DU1={1, 200, 16, PA#1} and the host data update command DU5={5, 200, 1, PA#5} contain the same logical address LBA#200, and DU1 must be executed before DU5.
在一些實施方式中,閃存控制器130可採取順序更新優先(Sequential-update First)的原則來移出和處理順序更新命令佇列310和隨機更新命令佇列330中的主機資料更新命令。也就是說,閃存控制器130先執行完主機資料更新命令DU1、DU3、DU4之後,再執行主機資料更新命令DU2、DU5。然而,因為DU2的執行晚於DU4,造成邏輯位址LBA#300的最終更新結果並不是主機端110期望的執行完主機資料更新命令DU4的結果,發生髒寫入的情況。In some implementations, the
在另一些實施方式中,閃存控制器130可採取隨機更新(Random-update First)優先的原則來移出和處理順序更新命令佇列310和隨機更新命令佇列330中的主機資料更新命令。也就是說,閃存控制器130先執行完主機資料更新命令DU2、DU5之後,再執行主機資料更新命令DU1、DU3、DU4。然而,因為DU1的執行晚於DU5,造成邏輯位址LBA#200的最終更新結果並不是主機端110期望的執行完主機資料更新命令DU5的結果,發生髒寫入的情況。In other embodiments, the
為了解決如上所述實施方式所產生的髒寫入的問題,本發明實施例提出一種主機資料更新命令的排程機制。參考圖4所示的方法流程圖,此方法由處理單元134在載入和執行FTL時執行,不斷地從主機端110接收資料更新的主機命令,根據主機命令的類型和其中攜帶的參數產生主機資料更新命令,並且使用順序更新命令佇列310和隨機更新命令佇列330來排程這些主機資料更新命令,並且使用預設的規則來執行這些主機資料更新命令。詳細說明如下:In order to solve the problem of dirty writing generated by the above-mentioned implementation method, the embodiment of the present invention proposes a scheduling mechanism for host data update commands. Referring to the method flow chart shown in FIG4 , the method is executed by the processing unit 134 when loading and executing the FTL, continuously receiving host commands for data update from the
步驟S412:判斷是否通過主機介面131從主機端110接收到資料更新的主機命令,例如主機寫入、丟棄、抹寫命令等。如果是,流程繼續進行步驟S422的處理;否則,流程繼續進行步驟S414的處理。Step S412: Determine whether a host command for data update, such as a host write, discard, or erase command, is received from the
步驟S414:如果目前沒有待處理的資料更新的主機命令時,等待一段預設的時間。Step S414: If there is no host command to be processed for data update, wait for a preset time.
步驟S422:獲取資料更新的主機命令的內容。Step S422: Obtain the content of the host command for data update.
步驟S424:根據主機命令的類型和其中攜帶的參數產生主機資料更新命令,並且依據主機命令中攜帶的邏輯位址長度將此主機資料更新命令標記為順序更新命令(SUC)或者隨機更新命令(RUC)。主機資料更新命令的資料結構和產生細節,以及標記為SUC或者RUC的判斷細節,可參考如上段落的說明,為求簡明不再贅述。Step S424: Generate a host data update command according to the type of the host command and the parameters carried therein, and mark the host data update command as a sequential update command (SUC) or a random update command (RUC) according to the length of the logical address carried in the host command. The data structure and generation details of the host data update command, as well as the judgment details of marking as SUC or RUC, can be referred to the description in the above paragraph, and will not be repeated for the sake of brevity.
步驟S432:判斷此主機資料更新命令是否為SUC且SCQ 310已經滿了,或者此主機資料更新命令中的邏輯位址是否已經存在於SCQ 310的其他主機資料更新命令之中。如果是,流程繼續進行步驟S434的處理;否則,流程繼續進行步驟S442的處理。Step S432: Determine whether the host data update command is a SUC and the
步驟S434:依序推出和執行SCQ 310中的所有SUC。例如,針對一個或多個寫入資料的SUC,處理單元134可從RAM 136的緩衝區讀取待寫入的主機資料,驅動閃存介面139以將主機資料寫入特定實體位址,接著,更新F2H表和H2F表中的相應紀錄以反映已執行的資料寫入操作。針對一個或多個丟棄資料的SUC,處理單元134可從RAM 136的暫存H2F中刪除特定邏輯位址的紀錄。針對一個或多個抹寫資料的SUC,處理單元134可驅動閃存介面139以抹寫特定實體位址,接著,更新H2F表中的相應紀錄以反映已執行的資料抹寫操作。步驟S434可確保SCQ 310中具有全部或者部分相同邏輯位址的SUC的執行早於此主機資料更新命令的執行。Step S434: All SUCs in the
步驟S442:判斷此主機資料更新命令是否為RUC且RCQ 330已經滿了,或者此主機資料更新命令中的邏輯位址是否已經存在於RCQ 330的其他主機資料更新命令之中。如果是,流程繼續進行步驟S444的處理;否則,流程繼續進行步驟S452的處理。Step S442: Determine whether the host data update command is a RUC and the
步驟S444:依序推出和執行RCQ 330中的所有RUC。例如,針對一個或多個寫入資料的RUC,處理單元134可從RAM 136的緩衝區讀取待寫入的主機資料,驅動閃存介面139以將主機資料寫入特定實體位址,接著,更新F2H表和/或H2F表中的相應紀錄以反映已執行的資料寫入操作。針對一個或多個丟棄資料的RUC,處理單元134可從RAM 136的暫存H2F中刪除特定邏輯位址的紀錄。針對一個或多個抹寫資料的RUC,處理單元134可驅動閃存介面139以抹寫特定實體位址,接著,更新H2F表中的相應紀錄以反映已執行的資料抹寫操作。步驟S434可確保RCQ 330中具有全部或者部分相同邏輯位址的RUC的執行早於此主機資料更新命令的執行。Step S444: All RUCs in
步驟S452:判斷此主機資料更新命令是否為SUC且其中的邏輯位址已經存在於RCQ 330的其他主機資料更新命令之中,或者此主機資料更新命令是否為RUC且其中的邏輯位址已經存在於SCQ 310的其他主機資料更新命令之中。如果是,流程繼續進行步驟S454的處理;否則,流程繼續進行步驟S462的處理。Step S452: Determine whether the host data update command is a SUC and the logical address therein already exists in other host data update commands of
步驟S454:依序推出和執行SCQ 310中的所有SUC,以及RCQ 330中的所有RUC。執行SUC和RUC的技術細節可參考步驟S434和S444的說明,為求簡明不再贅述。步驟S454可確保SCQ 310或RCQ 330中具有全部或者部分相同邏輯位址的SUC或RUC的執行早於此主機資料更新命令的執行。Step S454: All SUCs in
步驟S462:將此主機資料更新命令推入SCQ 310和RCQ 330中的相應一個。如果此主機資料更新命令為SUC,則推入SCQ 310。如果此主機資料更新命令為RUC,則推入RCQ 330。Step S462: Push the host data update command into the corresponding one of the
以下舉實例來說明圖4的方法執行。一開始,SCQ 310和RCQ 330為空的佇列。The following example is used to illustrate the execution of the method of Figure 4. Initially,
處理單元134在時間點t1收到主機寫入命令W1={LBA#200~215,D1}(步驟S422),根據W1的內容產生主機更新命令DU1={1, 200, 16, PA#1}並標記為SUC(步驟S424)。因為三個判斷都不符合,主機更新命令DU1={1, 200, 16, PA#1}推入SCQ 310,此時SCQ 310包含{DU1},而RCQ 330為空佇列(步驟S462)。The processing unit 134 receives the host write command W1={LBA#200~215,D1} at time t1 (step S422), generates the host update command DU1={1, 200, 16, PA#1} according to the content of W1 and marks it as SUC (step S424). Because none of the three judgments are met, the host update command DU1={1, 200, 16, PA#1} is pushed into the
處理單元134在時間點t2收到主機寫入命令W2={LBA#300,D2}(步驟S422),根據W2的內容產生主機更新命令DU2={2, 300, 1, PA#2}並標記為RUC(步驟S424)。因為三個判斷都不符合,主機更新命令DU2={2, 300, 1, PA#2}推入RCQ 330,此時SCQ 310包含{DU1},而RCQ 330包含{DU2}(步驟S462)。The processing unit 134 receives the host write command W2={LBA#300,D2} at time t2 (step S422), generates the host update command DU2={2, 300, 1, PA#2} according to the content of W2 and marks it as RUC (step S424). Because none of the three judgments are met, the host update command DU2={2, 300, 1, PA#2} is pushed into the
處理單元134在時間點t3收到主機寫入命令W3={LBA#400~415,D3}(步驟S422),根據W3的內容產生主機更新命令DU3={3, 400, 16, PA#3}並標記為SUC(步驟S424)。因為三個判斷都不符合,主機更新命令DU3={3, 400, 16, PA#3}推入SCQ 310,此時SCQ 310包含{DU1, DU3},而RCQ 330包含{DU2}(步驟S462)。The processing unit 134 receives the host write command W3={LBA#400~415,D3} at time t3 (step S422), generates the host update command DU3={3, 400, 16, PA#3} according to the content of W3 and marks it as SUC (step S424). Because none of the three judgments are met, the host update command DU3={3, 400, 16, PA#3} is pushed into the
處理單元134在時間點t4收到主機寫入命令W4={LBA#300~315,D4}(步驟S422),根據W4的內容產生主機更新命令DU4={4, 300, 16, PA#4}並標記為SUC(步驟S424)。因為主機更新命令DU4中的邏輯位址LBA#300部分相同於RCQ 330中的DU2中的邏輯位址LBA#300~315(步驟S452中”是”的路徑),依序推出和執行SCQ 310中的主機更新命令DU1和DU3,以及RCQ 330中的主機更新命令DU2(步驟S454)。接著,將主機更新命令DU4={4, 300, 16, PA#4}推入SCQ 310,此時SCQ 310包含{DU4},而RCQ 330為空佇列(步驟S462)。Processing unit 134 receives host write command W4={LBA#300~315,D4} at time t4 (step S422), generates host update command DU4={4, 300, 16, PA#4} according to the content of W4 and marks it as SUC (step S424). Because the logical address LBA#300 in host update command DU4 is the same as the logical address LBA#300~315 in DU2 in RCQ 330 (the path of "yes" in step S452), host update commands DU1 and DU3 in
處理單元134在時間點t5收到主機寫入命令W5={LBA#200}(步驟S422),根據W5的內容產生主機更新命令DU5={5, 200, 1, PA#5}並標記為RUC(步驟S424)。因為三個判斷都不符合,主機更新命令DU5={5, 200, 1, PA#5}推入RCQ 330,此時SCQ 310包含{DU4},而RCQ 330包含{DU5}(步驟S462)。The processing unit 134 receives the host write command W5={LBA#200} at time t5 (step S422), generates the host update command DU5={5, 200, 1, PA#5} according to the content of W5 and marks it as RUC (step S424). Because none of the three judgments are met, the host update command DU5={5, 200, 1, PA#5} is pushed into the
為了解決如上所述實施方式所產生的髒寫入的問題,本發明實施例提出另一種主機資料更新命令的排程機制。參考圖5所示的方法流程圖,此方法由處理單元134在載入和執行FTL時執行,不斷地從主機端110接收資料更新的主機命令,根據主機命令的類型和其中攜帶的參數產生主機資料更新命令,並且使用順序更新命令佇列310和隨機更新命令佇列330來排程這些主機資料更新命令,並且使用預設的規則來執行這些主機資料更新命令。詳細說明如下:In order to solve the problem of dirty writing generated by the above-mentioned implementation method, the embodiment of the present invention proposes another scheduling mechanism for host data update commands. Referring to the method flow chart shown in FIG5 , the method is executed by the processing unit 134 when loading and executing the FTL, continuously receiving host commands for data update from the
步驟S512、S514、S522、S524的技術內容分別類似於步驟S412、S414、S422、S424,為求簡明,不再贅述。The technical contents of steps S512, S514, S522, and S524 are similar to those of steps S412, S414, S422, and S424, respectively, and will not be described in detail for the sake of brevity.
步驟S532:判斷SCQ 310是否已經滿了。如果是,流程繼續進行步驟S534的處理;否則,流程繼續進行步驟S542的處理。Step S532: Determine whether
步驟S534的技術內容類似於步驟S434,為求簡明,不再贅述。The technical content of step S534 is similar to that of step S434, and will not be described in detail for the sake of brevity.
步驟S542:判斷RCQ 330是否已經滿了。如果是,流程繼續進行步驟S544的處理;否則,流程繼續進行步驟S552的處理。Step S542: Determine whether
步驟S544的技術內容類似於步驟S444,為求簡明,不再贅述。The technical content of step S544 is similar to that of step S444, and will not be described in detail for the sake of brevity.
步驟S552:判斷此主機資料更新命令中的邏輯位址是否和SCQ 310和RCQ 330中的任何SUC或RUC的邏輯位址相同。如果是,流程繼續進行步驟S554的處理;否則,流程繼續進行步驟S562的處理。Step S552: Determine whether the logical address in the host data update command is the same as the logical address of any SUC or RUC in
步驟S554:將重複的邏輯位址從SCQ 310和RCQ 330中的相應主機資料更新命令刪除。Step S554: Delete the duplicate logical addresses from the corresponding host data update commands in
步驟S562的技術內容類似於步驟S462,為求簡明,不再贅述。The technical content of step S562 is similar to that of step S462, and will not be described in detail for the sake of brevity.
以下舉實例來說明圖5的方法執行。一開始,SCQ 310和RCQ 330為空的佇列。處理單元134分別在時間點t1、t2、t3收到主機寫入命令W1={LBA#200~215,D1}、W2={LBA#300,D2}、W3={LBA#400~415,D3}(步驟S522),分別根據W1、W2、W3的內容產生主機更新命令DU1={1, 200, 16, PA#1}、DU2={2, 300, 1, PA#2}、DU3={3, 400, 16, PA#3},並分別標記為SUC、RUC、SUC(步驟S424)。因為主機更新命令DU1、DU2、DU3都無法通過三個判斷,主機更新命令DU1、DU3推入SCQ 310,主機更新命令DU2推入RCQ 330(步驟S462)。在主機寫入命令W3處理完後,SCQ 310包含{DU1, DU3},而RCQ 330包含{DU2}。The following example is used to illustrate the execution of the method of FIG. 5 . Initially,
處理單元134在時間點t4收到主機寫入命令W4={LBA#300~315,D4}(步驟S522),根據W4的內容產生主機更新命令DU4={4, 300, 16, PA#4}並標記為SUC(步驟S524)。因為主機更新命令DU4中的邏輯位址LBA#300相同於RCQ 330中的DU2中的邏輯位址LBA#300~315(步驟S552中”是”的路徑),將重複的邏輯位址從RCQ 330中的DU2刪除,使得原本的主機更新命令DU2={2, 300, 1, PA#2},改變成為DU2’={2, NULL, 0, NULL}(步驟S554)。接著,將主機更新命令DU4={4, 300, 16, PA#4}推入SCQ 310,此時SCQ 310包含{DU1, DU3, DU4},而RCQ 330包含{DU2’}(步驟S562)。在這裡需要注意的是,由於主機更新命令DU2’的邏輯位址為NULL,此命令將來從RCQ 330推出後,並不會被執行。The processing unit 134 receives the host write command W4={LBA#300~315,D4} at time t4 (step S522), and generates the host update command DU4={4, 300, 16, PA#4} according to the content of W4 and marks it as SUC (step S524). Because the logical address LBA#300 in the host update command DU4 is the same as the logical address LBA#300~315 in DU2 in RCQ 330 (the "yes" path in step S552), the duplicate logical address is deleted from DU2 in
處理單元134在時間點t5收到主機寫入命令W5={LBA#200}(步驟S522),根據W5的內容產生主機更新命令DU5={5, 200, 1, PA#5}並標記為RUC(步驟S524)。因為主機更新命令DU5中的邏輯位址LBA#200部分相同於RCQ 330中的DU1中的邏輯位址LBA#200~215(步驟S552中”是”的路徑),將重複的邏輯位址從SCQ 310中的DU1刪除,使得原本的主機更新命令DU1={1, 200, 16, PA#1},改變成為DU1’={1, 201, 15, PA#1’}(步驟S554)。接著,將主機更新命令DU5={5, 200, 1, PA#5}推入RCQ 330,此時SCQ 310包含{DU1’, DU3, DU4},而RCQ 330包含{DU2’,DU5}(步驟S562)。Processing unit 134 receives host write command W5={LBA#200} at time t5 (step S522), generates host update command DU5={5, 200, 1, PA#5} based on the content of W5 and marks it as RUC (step S524). Because the logical address LBA#200 in host update command DU5 is the same as the logical address LBA#200~215 in DU1 in RCQ 330 (the path of "yes" in step S552), the duplicated logical address is deleted from DU1 in
邏輯位址的更新操作和主機資料更新命令的入列操作會不斷的執行,直到SCQ 310或RCQ 330滿了。一旦SCQ 310滿了(步驟S532中“是”的路徑),依序推出和執行SCQ 310中的所有主機更新命令(步驟S534)。一旦RCQ 330滿了(步驟S542中“是”的路徑),依序推出和執行RCQ 330中的所有主機更新命令(步驟S544)。The logical address update operation and the host data update command enqueue operation are continuously executed until the
本發明所述的方法中的全部或部分步驟可以計算機指令實現,例如儲存裝置中的韌體轉換層(Firmware Translation Layer,FTL)、特定硬體的驅動程式等。此外,也可實現於其他類型程式。所屬技術領域具有通常知識者可將本發明實施例的方法撰寫成計算機指令,為求簡潔不再加以描述。依據本發明實施例方法實施的計算機指令可儲存於適當的電腦可讀取媒體,例如DVD、CD-ROM、USB碟、硬碟,亦可置於可通過網路(例如,網際網路,或其他適當載具)存取的網路伺服器。All or part of the steps in the method described in the present invention can be implemented by computer instructions, such as the firmware translation layer (FTL) in the storage device, the driver of the specific hardware, etc. In addition, it can also be implemented in other types of programs. A person with ordinary knowledge in the relevant technical field can write the method of the embodiment of the present invention into computer instructions, and for the sake of brevity, it will not be described again. The computer instructions implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer-readable medium, such as a DVD, CD-ROM, USB disk, hard disk, or can be placed in a network server that can be accessed through a network (for example, the Internet, or other appropriate carriers).
雖然圖1、圖2中包含了以上描述的元件,但不排除在不違反發明的精神下,使用更多其他的附加元件,已達成更佳的技術效果。此外,雖然圖4至圖5的流程圖採用指定的順序來執行,但是在不違反發明精神的情況下,熟習此技藝人士可以在達到相同效果的前提下,修改這些步驟間的順序,所以,本發明並不侷限於僅使用如上所述的順序。此外,熟習此技藝人士亦可以將若干步驟整合為一個步驟,或者是除了這些步驟外,循序或平行地執行更多步驟,本發明亦不因此而侷限。Although FIG. 1 and FIG. 2 include the components described above, it is not excluded that more additional components may be used to achieve better technical effects without violating the spirit of the invention. In addition, although the flowcharts of FIG. 4 to FIG. 5 are executed in a specified sequence, a person skilled in the art may modify the sequence of these steps without violating the spirit of the invention, so the present invention is not limited to the sequence described above. In addition, a person skilled in the art may also integrate several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention is not limited thereto.
雖然本發明使用以上實施例進行說明,但需要注意的是,這些描述並非用以限縮本發明。相反地,此發明涵蓋了熟習此技藝人士顯而易見的修改與相似設置。所以,申請權利要求範圍須以最寬廣的方式解釋來包含所有顯而易見的修改與相似設置。Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, the present invention covers modifications and similar arrangements that are obvious to those skilled in the art. Therefore, the scope of the claims should be interpreted in the broadest manner to include all obvious modifications and similar arrangements.
10:電子裝置
110:主機端
130:閃存控制器
131:主機介面
132:匯流排
134:處理單元
136:隨機存取記憶體
138:直接記憶體存取控制器
139:閃存介面
150:閃存模組
151:介面
153#0~153#15:NAND閃存單元
CH#0~CH#3:通道
CE#0~CE#3:致能訊號
310:順序更新命令佇列
330:隨機更新命令佇列
S412~S462:方法步驟
S512~S562:方法步驟
10: electronic device
110: host side
130: flash memory controller
131: host interface
132: bus
134: processing unit
136: random access memory
138: direct memory access controller
139: flash memory interface
150: flash memory module
151:
圖1為依據本發明實施例的電子裝置的系統架構圖。FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the present invention.
圖2為依據本發明實施例的閃存模組的示意圖。FIG. 2 is a schematic diagram of a flash memory module according to an embodiment of the present invention.
圖3為依據本發明實施例的隨機寫入命令佇列和連續寫入命令佇列的示意圖。FIG. 3 is a schematic diagram of a random write command queue and a continuous write command queue according to an embodiment of the present invention.
圖4為依據本發明實施例的排程和執行主機資料更新命令方法的流程圖。FIG. 4 is a flow chart of a method for scheduling and executing host data update commands according to an embodiment of the present invention.
圖5為依據本發明實施例的排程和執行主機資料更新命令方法的流程圖。FIG. 5 is a flow chart of a method for scheduling and executing host data update commands according to an embodiment of the present invention.
S512~S562:方法步驟 S512~S562: Method steps
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