TW202349591A - Semiconductor package - Google Patents

Abstract

A semiconductor package includes a first redistribution substrate, a semiconductor chip on the first redistribution substrate, and vertical conductive structures spaced apart from a side surface of the semiconductor chip. Each of the vertical conductive structures includes a wire, and a metal layer covering a side surface of the wire. A top surface of the wire is exposed from the metal layer.

Description

Semiconductor packaging

[Cross-reference to related applications]

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2022-0071704 filed with the Korean Intellectual Property Office on June 13, 2022, the entire contents of which are incorporated by reference. are incorporated into this article.

The present disclosure relates to a semiconductor package.

Integrated circuit wafers can be implemented in the form of semiconductor packages for proper application in electronic products. In a typical semiconductor package, a semiconductor die may be mounted on a printed circuit board and may be electrically connected to the printed circuit board via wires or bumps. As the electronics industry develops, various technologies for improving the reliability of semiconductor packages and for miniaturizing semiconductor packages have been studied.

Embodiments of the inventive concept may provide a semiconductor package with improved reliability.

Embodiments of the inventive concept may also provide a method of manufacturing a semiconductor package that can increase the strength of the vertical conductive structures of the semiconductor package while reducing the number of processes for forming the vertical conductive structures.

In one aspect, a semiconductor package may include: a first redistribution substrate; a semiconductor die located on the first redistribution substrate; and a vertical conductive structure spaced apart from a side surface of the semiconductor die. Each of the vertical conductive structures may include a conductive wire and a metal layer covering side surfaces of the conductive wire. The top surface of the conductor may be exposed from the metal layer.

In one aspect, a semiconductor package may include: a first redistribution substrate; a semiconductor chip located on the first redistribution substrate; and a vertical conductive structure disposed on the first redistribution substrate and in contact with a side surface of the semiconductor chip Spaced out. Each of the vertical conductive structures may include a conductive wire and a metal layer covering side surfaces of the conductive wire. The level of the top surface of the conductor may be substantially the same as the level of the top surface of the metal layer.

In one aspect, a semiconductor package may include a first package and a second package located on the first package. The first package may include: a first redistribution substrate; a first semiconductor chip and a vertical conductive structure on the first redistribution substrate, each of the vertical conductive structures including a wire and a metal layer covering a side surface of the wire; a second redistribution substrate spaced apart from the first redistribution substrate with the first semiconductor chip and the vertical conductive structure interposed therebetween; and a first molding component disposed between the first redistribution substrate and the second redistribution substrate and covers the top surface and side surface of the first semiconductor chip and the side surface of the metal layer. The second package may include: a packaging substrate; a second semiconductor chip located on the packaging substrate; and a second molding component covering a top surface of the packaging substrate and top and side surfaces of the second semiconductor chip. The conductor may include a first portion and a second portion disposed at an end of the first portion. The first portion may have a substantially constant line shape with a width that increases with a height in a first direction perpendicular to the top surface of the first redistribution substrate, and the second portion may have a width that increases with a height in the first direction. Reduced shape. The other end of the first part may be in contact with the second redistribution substrate, and the second part may be in contact with the first redistribution substrate.

Embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings. Similar numbers refer to similar elements throughout.

FIG. 1 is a plan view illustrating a semiconductor package according to an exemplary embodiment of the inventive concept. FIG. 2 is a cross-sectional view taken along line II' of FIG. 1 .

Referring to FIGS. 1 and 2 , the semiconductor package 1 may include a first semiconductor package PK1 and a second semiconductor package PK2 located on the first semiconductor package PK1 . The semiconductor package 1 may have a package-on-package (PoP) structure.

The first semiconductor package PK1 may include a first redistribution substrate 1000, a first semiconductor chip 700, a second redistribution substrate 2000, a vertical conductive structure 300, and a first mold part 950.

The first redistribution substrate 1000 may have a first surface 1000a and a second surface 1000b opposite to each other. A direction parallel to the first surface 1000a of the first redistribution substrate 1000 may be defined as the first direction D1. A direction parallel to the first surface 1000a and perpendicular to the first direction D1 may be defined as the second direction D2. A direction perpendicular to the first surface 1000a of the first redistribution substrate 1000 may be defined as the third direction D3.

The first redistribution substrate 1000 may include a first redistribution pattern 10, a first insulation layer 20, and an under-bump pattern 70. The first rewiring pattern 10 and the under-bump pattern 70 may be disposed in the first insulation layer 20 . For example, at least one of the first redistribution patterns 10 may be disposed in a corresponding one of the first insulation layers 20 . Different from Figure 2, in some embodiments, the first insulating layer 20 may be a single insulating layer. The first insulation layer 20 may include photosensitive insulation material. For example, the first insulating layer 20 may include at least one of photosensitive polyimide, polybenzoxazole, phenol polymer or benzocyclobutene polymer.

The under-bump pattern 70 may be disposed at the second surface 1000b of the first redistribution substrate 1000. The bottom surface of each of the under-bump patterns 70 may be exposed from the first insulation layer 20 . For example, the bottom surface of each of the under-bump patterns 70 may be coplanar with the bottom surface of the lowermost first insulation layer 20 . Under-bump pattern 70 may include copper or aluminum.

The first rewiring pattern 10 may be stacked on the under-bump pattern 70 . Each of the first redistribution patterns 10 may include a first conductive pattern 12 and a first seed/barrier pattern 14. For example, the first conductive pattern 12 may include copper, and the first seed/barrier pattern 14 may include copper/titanium.

The first seed/barrier pattern 14 may be partially disposed on the bottom surface of the first conductive pattern 12 . Each of the first rewiring patterns 10 may include a via portion V1 and an interconnection portion L1 connected to each other in one body. For example, the via portion V1 and the interconnection portion L1 may be materially continuous with each other.

As used herein, the term "material continuity" may refer to structures, patterns and/or layers formed simultaneously and from the same material without interruption in the continuity of the materials forming the structures, patterns and/or layers. As an example, "materially continuous" structures, patterns and/or layers may be homogeneous monolithic structures. As used herein, the term "contact" refers to direct connection (ie, touch) unless the context indicates otherwise. For example, when an element "touches" or is "in contact with" another element, there are no intervening elements at the point of contact.

The via portion V1 of the first redistribution pattern 10 can fill the via hole VH of the first insulation layer 20 and can be connected to the interconnection portion L1 of another first redistribution pattern 10 thereunder or under the bump thereunder. Pattern 70.

The first upper pad 82 and the second upper pad 84 may be disposed on the uppermost first rewiring pattern 10 of the first rewiring pattern 10 . The first upper pad 82 and the second upper pad 84 may have substantially the same components as the first rewiring pattern 10 . In other words, each of the first upper pad 82 and the second upper pad 84 may include the first conductive pattern 12 and the first seed/barrier pattern 14 .

The first semiconductor chip 700 may be disposed on the first redistribution substrate 1000 . For example, the first semiconductor chip 700 may be a logic chip or a memory chip. The first semiconductor wafer 700 may be disposed on the first redistribution substrate 1000 in such a manner that the first wafer pad 705 of the first semiconductor wafer 700 faces the first redistribution substrate 1000 .

The connection terminal 708 may be in contact with the first upper pad 82 and the first wafer pad 705 and may be electrically connected to the first wafer pad 705 and the first upper pad 82 . The first semiconductor chip 700 may be electrically connected to the first redistribution substrate 1000 via the connection terminals 708 . The connection terminals 708 may include at least one of solder, posts, or bumps. The connection terminal 708 may include a conductive material such as tin (Sn) or silver (Ag).

The vertical conductive structure 300 may be disposed on the first surface 1000a of the first redistribution substrate 1000 and may be spaced apart from the side surface of the first semiconductor chip 700 in the first direction D1 and/or the second direction D2. The vertical conductive structures 300 may be configured in the first direction D1 and the second direction D2 and may be spaced apart from each other. Vertical conductive structure 300 will be described in greater detail subsequently.

The second redistribution substrate 2000 may be disposed on the top surface of the first molding part 950 and the top surface of the vertical conductive structure 300 .

The second redistribution substrate 2000 may include a second insulation layer 40 and a second redistribution pattern 30 . The second insulating layer 40 may include a plurality of second insulating layers 40 and the second rewiring patterns 30 may include a plurality of second rewiring patterns 30 , wherein at least one of the plurality of second rewiring patterns 30 is disposed on a plurality of in each of the second insulating layers 40 . The vertical conductive structure 300 may be connected to the second rewiring pattern 30 . For example, the lowermost second redistribution pattern 30 may contact the upper surface of the vertical conductive structure 300 . The second insulation layer 40 may be the same/similar photosensitive insulation layer as the first insulation layer 20 . In exemplary embodiments, the second insulating layer 40 may include a photosensitive insulating material. For example, the second insulating layer 40 may include at least one of photosensitive polyimide, polybenzoxazole, phenol polymer, or benzocyclobutene polymer.

The second redistribution pattern 30 may include a second conductive pattern 32 and a second seed/barrier pattern 34. The second conductive pattern 32 and the second seed/barrier pattern 34 may include the same/similar materials as the first conductive pattern 12 and the first seed/barrier pattern 14 respectively. For example, the second conductive pattern 32 may include copper, and the second seed/barrier pattern 34 may include copper/titanium. Like the first rewiring pattern 10, the second rewiring pattern 30 may have the via portion V1 and the interconnection portion L1 connected thereto. For example, the via portion V1 and the interconnection portion L1 of the second redistribution pattern 30 may be materially continuous with each other.

The second semiconductor package PK2 may be disposed on the second redistribution substrate 2000 . The second semiconductor package PK2 may include a package substrate 810, a second semiconductor die 800, and a second mold part 850. The packaging substrate 810 may be a printed circuit board or a rewiring substrate. Metal pads 815 and 817 may be disposed on both surfaces of the packaging substrate 810 . For example, the metal pad 815 may be disposed on the upper surface of the packaging substrate 810 , and the metal pad 817 may be disposed on the lower surface of the packaging substrate 810 . The second semiconductor wafer 800 may be a memory wafer such as a DRAM wafer or a NAND flash wafer. Alternatively, the second semiconductor die 800 may be a logic die. The second semiconductor wafer 800 may be a type of semiconductor wafer different from that of the first semiconductor wafer 700 . For example, the second chip pad 805 disposed on one surface of the second semiconductor chip 800 may be connected to the metal pad 815 of the packaging substrate 810 through a wire bonding method.

The package connection terminal 808 may be disposed between the first semiconductor package PK1 and the second semiconductor package PK2. The package connection terminal 808 may be in contact with the uppermost second rewiring pattern 30 of the second rewiring pattern 30 and the metal pad 817 . The package connection terminal 808 may be electrically connected to the second rewiring pattern 30 and the metal pad 817 . Therefore, the second semiconductor package PK2 may be electrically connected to the first semiconductor die 700 and the external connection terminals 908 via the package connection terminals 808 , the second redistribution substrate 2000 , the vertical conductive structure 300 and the first redistribution substrate 1000 .

The vertical conductive structure 300 may be disposed on the second upper pad 84 so as to contact an upper surface of the second upper pad 84 . Each of the vertical conductive structures 300 may include a conductive wire 310 and a metal layer 320 extending longitudinally in the third direction D3. The metal layer 320 may cover the side surface of the conductor 310, thereby contacting the side surface of the conductor 310. The conductive wire 310 and the metal layer 320 may include a first metal material and a second metal material respectively. The first metal material and the second metal material can be different metal materials or the same metal material. For some examples, the first metallic material can include at least one of gold, silver, or aluminum, and the second metallic material can include copper. For some examples, the first metallic material and the second metallic material may include copper. In embodiments in which the wire 310 and the metal layer 320 include the same metal material, the particle size and crystal orientation of the wire 310 may be different from the particle size and crystal orientation of the metal layer 320 . As described later, this may be because the wire 310 is elongated in one direction during the formation process and the metal layer 320 is formed by the electroplating process.

The wire 310 may include a first portion 311 and a second portion 312 connected to an end of the first portion 311 . The first part 311 may have a line shape, and the second part 312 may have a hemispherical shape or a hemispherical-like shape. Alternatively, the second portion 312 may have a shape whose width decreases as the vertical height from the first surface 1000a of the first redistribution substrate 1000 increases. The width of the first portion 311 may be substantially constant as the height in the third direction D3 increases. The diameter of the second portion 312 may be greater than the width of the first portion 311 .

3 is a plan view showing the top surface of the vertical conductive structure of FIG. 2 .

Referring to FIGS. 2 and 3 , the top surface of the vertical conductive structure 300 may be exposed from the top surface 950 a of the first molding part 950 . In addition, the top surface 310a of the wire 310 may be exposed from the top surface 320a of the metal layer 320. Due to the materials (eg, Au and Cu ) and crystallinity of the wires 310 , the electrical properties (eg, conductivity) of the wires 310 may be better than those of the metal layer 320 . The wires 310 may be directly connected to the first redistribution pattern 10 and the second redistribution pattern 30 , and thus may improve the electrical characteristics (eg, conductivity) of the semiconductor package 1 . The top surface 950a of the first mold part 950, the top surface 310a of the wire 310, and the top surface 320a of the metal layer 320 may be substantially coplanar with each other. For example, the level of the top surface 310a of the conductive line 310 may be substantially the same as the level of the top surface 320a of the metal layer 320. The height of the wire 310 may be substantially equal to the height of the metal layer 320 . The height of the wire 310 and the height of the metal layer 320 may mean the length in the third direction D3 from the top surface of the second upper pad 84 .

The top surface of the vertical conductive structure 300 exposed from the first mold part 950 may have a circular shape or a circular-like shape. The exposed top surface 310a of the wire 310 may have a circular shape or a circular-like shape. The exposed top surface 320a of the metal layer 320 may have a ring shape.

When viewed in plan view, the diameter R1 of the vertical conductive structure 300 may range from 80 microns to 120 microns. When viewed in plan view, the diameter R2 of the wire 310 may be in the range of 40 microns to 60 microns. The diameter R2 of the wire 310 may correspond to the width of the first portion 311 of the wire 310 .

When viewed in plan view, the width T1 of the metal layer 320 may be in the range of 40 microns to 60 microns. The diameter R2 of the wire 310 and the width T1 of the metal layer 320 can be adjusted differently according to the design.

Figure 4 is an enlarged view of part "aa" in Figure 2 .

Referring to FIGS. 2 and 4 , the second portion 312 of the wire 310 may be in contact with the first conductive pattern 12 of the second upper pad 84 . The metal layer 320 may also be in contact with the first conductive pattern 12 of the second upper pad 84 . For example, the upper surface of the first conductive pattern 12 of the second upper pad 84 may contact the entire lower surface of the second portion 312 of the conductive line 310 and the entire lower surface of the metal layer 320 . The metal layer 320 and the first conductive pattern 12 may include the same metal material. For example, the metal layer 320 and the first conductive pattern 12 may include copper.

In some embodiments, a metal pattern (not shown) for improving diffusion prevention and adhesion strength may be additionally disposed between the first conductive pattern 12 of the second upper pad 84 and the second portion 312 of the conductor 310 and between the first conductive pattern 12 and the metal layer 320 of the second upper pad 84 . The metal pattern may include at least one of gold or nickel.

The metal layer 320 may include an extension portion 321 covering the first portion 311 of the conductor 310 and a protruding portion 322 covering the second portion 312 of the conductor 310 . The protruding portion 322 may be provided at an end of the extending portion 321 and may have a shape protruding from the extending portion 321 in the first direction D1 and the second direction D2.

In some embodiments, the surface of the extension 321 and the surface of the protrusion 322 may have a cross-section similar to the cross-sections of the surfaces of the first portion 311 and the second portion 312 of the wire 310 , respectively.

The thickness U1 of the extension portion 321 of the metal layer 320 may be smaller than, equal to, or greater than the thickness U2 of the protruding portion 322 . On the other hand, the diameter X1 of the first portion 311 of the wire 310 may always be smaller than the diameter X2 of the second portion 312 . The difference between the thickness U1 of the extension portion 321 of the metal layer 320 and the thickness U2 of the protruding portion 322 may be smaller than the difference between the diameter X1 of the first portion 311 and the diameter X2 of the second portion 312 of the wire 310 . The diameter X1 of the first portion 311 of the wire 310 may correspond to the diameter R2 of the exposed top surface 310a of the wire 310, and the thickness U1 of the extension 321 of the metal layer 320 may correspond to the width of the exposed top surface 320a of the metal layer 320 of FIG. 3 T1.

FIG. 5 is an enlarged view corresponding to part "aa" in FIG. 2 .

Referring to FIGS. 2 and 5 , the seed pattern 16 may be disposed between the first conductive pattern 12 of the second upper pad 84 and the second portion 312 of the conductor 310 and between the first conductive pattern 12 of the second upper pad 84 and between metal layers 320. Seed pattern 16 may include copper. The bottom surface of the second portion 312 of the conductive line 310 and the bottom surface of the metal layer 320 may be in contact with the top surface of the seed pattern 16 .

FIG. 6 is an enlarged view corresponding to part "aa" in FIG. 2 .

Referring to FIGS. 2 and 6 , the second portion 312 of the conductive line 310 may be in contact with the top surface of the first conductive pattern 12 of the second upper pad 84 . The seed pattern 16 may be disposed between the metal layer 320 and the first conductive pattern 12 of the second upper pad 84 . The seed pattern 16 may be in contact with the side surface of the second portion 312 of the wire 310 . The lowermost portion of conductive line 310 may be disposed below the uppermost portion of seed pattern 16 .

Referring again to FIG. 2 , the thickness of the first semiconductor wafer 700 should have a specific value or be greater than the specific value to improve the heat dissipation characteristics of the semiconductor package 1 or the first semiconductor package PK1 . In this case, the vertical conductive structure 300 may be required to have a height greater than the thickness of the first semiconductor wafer 700 .

According to an embodiment of the inventive concept, the vertical conductive structure 300 may include a conductive wire 310 and a metal layer 320 covering a side surface of the conductive wire 310 . A wire control device may be used to adjust the length of the wire 310 to have a large height, and the metal layer 320 may reinforce the strength of the wire 310. Therefore, even if the thickness of the first semiconductor chip 700 is increased, the strength of the vertical conductive structure 300 can be increased while the height of the vertical conductive structure 300 can be easily increased, and thus the reliability of the semiconductor package can be improved.

7A to 7L are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept. Hereinafter, for the purpose of simplicity and convenience of explanation, description of the same features as mentioned above with reference to FIGS. 1 to 6 will be omitted.

Referring to FIG. 7A , a carrier substrate CR having a surface on which an adhesive layer AD is formed may be provided. The seed/barrier layer 14a may be formed on the carrier substrate CR to cover the top surface of the adhesive layer AD. A deposition process may be used to form seed/barrier layer 14a. For example, the seed/barrier layer 14a may include copper/titanium (Cu/Ti). Adhesion layer AD can adhere the seed/barrier layer 14a to the top surface of the carrier substrate CR.

The first mask pattern PM1 may be formed on the top surface of the seed/barrier layer 14a. The first mask pattern PM1 may include an opening defining a space where the under-bump pattern 70 is to be formed. The first mask pattern PM1 may be formed through a process of forming a photoresist layer, an exposure process, and a development process. A portion of the seed/barrier layer 14a may be exposed by the first mask pattern PM1. Under-bump pattern 70 may be formed by a plating process using the seed/barrier layer 14a in the opening as an electrode.

Referring to FIG. 7B, the first photomask pattern PM1 can be removed. Next, the first insulation layer 20 may be formed to cover the under-bump pattern 70 . The first insulating layer 20 may be formed by, for example, a spin coating process, and may subsequently be patterned by an exposure process and a development process to have openings exposing at least a portion of the top surface of each of the under-bump patterns 70 . Subsequently, a hardening process of the first insulating layer 20 may be performed. The seed/barrier layer 14a can be formed on the first insulating layer 20 again. A second mask pattern PM2 including openings may be formed on the seed/barrier layer 14a. Next, the first conductive pattern 12 may be formed on the seed/barrier layer 14a through an electroplating process using the seed/barrier layer 14a as an electrode.

Referring to FIG. 7C, the second photomask pattern PM2 can be removed. Next, a portion of the seed/barrier layer 14 a exposed from the first conductive pattern 12 may be removed to form the first seed/barrier pattern 14 . For example, portions of the seed/barrier layer 14a not covered by the first conductive pattern 12 may be removed. Therefore, the first redistribution pattern 10 including the first conductive pattern 12 and the first seed/barrier pattern 14 can be formed.

Referring to FIG. 7D , the foregoing method of forming the first insulating layer 20 and the first rewiring pattern 10 may be repeatedly performed to sequentially stack the first insulating layer 20 and the first rewiring pattern 10 . The first upper pad 82 and the second upper pad 84 can be formed by the same method as the first rewiring pattern 10 .

Referring to Figures 7E and 7F, a wire bonding process can be performed. As in FIG. 7E , wires 310 may be disposed on the second upper pad 84 . The wire 310 may be disposed on the second upper pad 84 by a wire control device 400 that is movable and capable of adjusting the length of the wire 310 .

The wire control device 400 may include a wire spool, a wire tensioner system (not shown), a wire clamp 420, a capillary tube 410, and an electric-flame-off (EFO) (not shown). Wire control device 400 may be a known wire control device.

The wire 310 may pass through the central portion of the capillary tube 410 to form a tail protruding from the capillary tube 410, and a strong spark may be applied to the tail from the EFO to form a spherical shape 310S at the end of the wire 310. The diameter of the ball shape 310S may be larger than the width of the wire 310 .

As in Figure 7F, the ball shape 310S of the wire 310 can be adhered to the top surface of the second upper pad 84, and external force can be applied thereto. The shape of the spherical 310S can be adjusted by a combination of external force, heat and ultrasound. The capillary 410 can be used again to adjust the wire 310 length, and the wire 310 can then be cut. Therefore, the wire 310 may be formed to have a first portion 311 extending in the vertical direction and a second portion 312 connected to an end of the first portion 311 .

Referring to FIG. 7G , a wire bonding process may be performed sequentially on the second upper pad 84 disposed on the top surface 1000 a of the first redistribution substrate 1000 . An electrode substrate EP including a plurality of holes HL may be disposed on the wire 310 . The upper portions of the conductive wires 310 may be respectively disposed in the holes HL of the electrode substrate EP, and the conductive wires 310 may directly contact or be electrically connected to the electrode substrate EP.

Referring to FIG. 7H , the wire 310 can be electroplated with a metal material by using the electrode base EP as an electrode. For example, the metallic material may be copper. Therefore, the metal layer 320 covering the side surface of the conductive wire 310 may be formed, and the vertical conductive structure 300 including the conductive wire 310 and the metal layer 320 may be formed. The metal layer 320 may be uniformly formed on the side surface of the conductor 310 , but in some embodiments, the thickness of the metal layer 320 on the first portion 311 of the conductor 310 may be different from the thickness of the metal layer on the second portion 312 of the conductor 310 320 thickness. The top surface of wire 310 may or may not be exposed from metal layer 320 .

Referring to FIG. 7I , the electrode substrate EP can be removed, and the first semiconductor wafer 700 can be mounted on the first redistribution substrate 1000 in such a manner that the first wafer pad 705 of the first semiconductor wafer 700 faces the first redistribution substrate 1000 . The process of mounting the first semiconductor wafer 700 on the first rewiring substrate 1000 may be performed using a thermal pressing process.

Referring to FIG. 7J , the first molding part 950 may be formed to cover the top surface 1000a of the first redistribution substrate 1000 and the top and side surfaces of the first semiconductor wafer 700 and to fill the bottom surface of the first semiconductor wafer 700 and the first layer. The space between the wiring substrates 1000. The first mold part 950 may be formed to cover the top surface 310a of the conductor 310 and the top surface 320a of the metal layer 320.

Referring to Figure 7K, a planarization process may be performed on first molded component 950. The planarization process may be performed until the top surface 310a of the conductor 310 and the top surface 320a of the metal layer 320 are exposed. Through the planarization process, the top surface of the first molding part 950, the top surface 310a of the conductive wire 310, and the top surface 320a of the metal layer 320 may be substantially coplanar with each other. The molded component 950 may be spaced apart from the conductive wire 310 in the first direction D1 and the second direction D2. For example, metal layer 320 may be disposed between conductive wire 310 and molded component 950 .

Referring to FIG. 7L, the second redistribution substrate 2000 may be formed on the first mold part 950 and the vertical conductive structure 300. The second redistribution substrate 2000 may be formed by substantially the same method as the aforementioned method of forming the first redistribution substrate 1000 . The second rewiring pattern 30 may be formed to be connected to the vertical conductive structure 300 . The singulation process may be performed along the saw line SL in the third direction D3 to form the first semiconductor package PK1. Next, the carrier substrate CR, adhesion layer AD and seed/barrier layer 14a can be removed. Removal of the seed/barrier layer 14a may be performed using an etching process. Under-bump pattern 70 can be exposed by removing seed/barrier layer 14a.

Referring to FIG. 2 again, external connection terminals 908 may be formed on the exposed under-bump pattern 70 to manufacture the first semiconductor package PK1. Next, the second semiconductor package PK2 may be mounted on the first semiconductor package PK1.

8 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept.

Referring to Figures 7H and 8, during the electroplating process, depending on the contact method, the metal layer 320 may cover the top surface 310a of the wire 310. The subsequent process may be the same as described above, and the planarization process of FIG. 7K may be performed until the top surface 310a of the wire 310 is exposed.

9A to 9D are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept.

Referring to FIGS. 7D and 9A , a seed layer 16a may be formed on the top surface 1000a of the first redistribution substrate 1000. The seed layer 16 a may cover the top surface 1000 a of the first redistribution substrate 1000 , the top and side surfaces of the first upper pad 82 , and the top and side surfaces of the second upper pad 84 . Next, the third mask pattern PM3 may be formed to include the opening OP exposing the top surface of the second upper pad 84 . The third photomask pattern PM3 may cover the seed layer 16a that does not vertically overlap the first and second upper pads 82 and 84 . The thickness of the third mask pattern PM3 may be a thickness capable of covering the top surface of the first upper pad 82 .

Referring to FIG. 9B , a wire bonding process may be performed on the seed layer 16 a disposed on the top surface of the second upper pad 84 . The second portion 312 of the wire 310 may contact the seed layer 16a. The wire bonding process may be the same as that discussed in connection with Figures 7E and 7F.

Referring to FIG. 9C , the metal layer 320 covering the top surface 310 a and side surfaces of the wire 310 may be formed using the seed layer 16 a as an electrode. Metal layer 320 may be locally and selectively formed on top surface 310a and side surfaces of conductor 310.

Referring to FIG. 9D , the third photomask pattern PM3 can be removed. An etching process may be used to remove seed layer 16a to form seed pattern 16 (see Figure 5). Next, the processes of FIGS. 7J-7L and 2 may be performed to manufacture the semiconductor package.

10A and 10B are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept.

Referring to FIGS. 7D and 10A , the wire bonding process may be performed directly on the second upper pad 84 . The wire bonding process may be the same as that discussed in connection with Figures 7E and 7F. Next, a seed layer 16 a may be formed to cover the top surface 1000 a of the first redistribution substrate 1000 , a portion of the top surface and side surfaces of the second upper pad 84 exposed from the conductive lines 310 , and the top of the first upper pad 82 surface and side surfaces. Next, the third photomask pattern PM3 may be formed to include an opening exposing the top surface of the seed layer 16 a vertically overlapping each of the second upper pads 84 .

Referring to FIG. 10B , the metal layer 320 covering the top and side surfaces of the wire 310 may be formed using the seed layer 16 a as an electrode. The third photomask pattern PM3 may be removed, and an etching process may be used to remove the seed layer 16a to form the seed pattern 16 (see FIG. 6). Next, the processes of Figures 7J-7L may be performed to fabricate the semiconductor package.

For typical vertical conductive structures, the height may be difficult to increase. For example, if an electroplating process is used to form typical vertical conductive structures without wires, a thick photoresist layer can be used as a mask pattern to define the spaces where typical vertical conductive structures will be formed. Alternatively, the height of a typical vertical conductive structure may be increased by a process using multiple photoresist layers, such as a process of forming a first mask pattern, a process of forming a first vertical conductive structure, a process of forming an exposed first vertical conductive structure A process of forming a second mask pattern of structures and forming a second vertical conductive structure connected to the first vertical conductive structure. In such processes, the formation time of typical vertical conductive structures can be increased and their manufacturing costs can be increased.

In contrast, according to embodiments of the inventive concept, wires can be used to easily increase the height of the vertical conductive structure in the process, and a metal layer can be used to reinforce the strength of the wires. In some embodiments, the metal layer may be formed by an electroplating process using wires as electrodes, and therefore the metal layer may be formed without the use of photoresist. In some embodiments, where a seed layer is used to form a metal layer, the wires and the seed layer can be connected to each other to serve as electrodes, and thus the metal layer can be formed to a desired height by using a thin photoresist.

According to embodiments of the inventive concept, the vertical conductive structure may include a conductive wire and a metal layer covering a side surface of the conductive wire. The length of the wire can be adjusted during the process, and the metal layer reinforces the wire's strength. Therefore, when the thickness of the semiconductor die in the package is increased to improve heat dissipation characteristics, the height of the vertical conductive structures can be easily increased to improve the reliability of the semiconductor package.

Although the embodiments of the inventive concepts have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims. change.

1:Semiconductor packaging 10: First rewiring pattern 12: First conductive pattern 14: First seed/barrier pattern 14a: Seed/barrier layer 16: Seed pattern 16a:Seed layer 20: First insulation layer 30: Second layer wiring pattern 32: Second conductive pattern 34: Second seed/barrier pattern 40: Second insulation layer 70: Pattern under bump 82: First upper pad 84: Second upper pad 300: Vertical conductive structure 310:Wire 310a: Top surface of wire 310 310S: ball shape 311:Part One 312:Part 2 320:Metal layer 320a: Top surface of metal layer 320 321:Extension 322:Protrusion 400: Wire control equipment 410:Capillary tube 420:Wire clamp 700: First semiconductor chip 705: First wafer pad 708:Connection terminal 800: Second semiconductor chip 805: Second wafer pad 808: Package connection terminal 810:Packaging substrate 815, 817: Metal gasket 850: Second molded part 908:External connection terminal 950: First molded part 950a: Top surface of first molded part 950 1000: First rewiring base 1000a: first surface of first redistribution substrate 1000 1000b: second surface of first redistribution substrate 1000 2000: The second rewiring base aa: part AD:adhesive layer CR: carrier base D1: first direction D2: second direction D3: Third direction EP: electrode base HL: hole I-I': line L1: interconnection part OP: Open your mouth PK1: The first semiconductor package PK2: Second semiconductor package PM1: first mask pattern PM2: Second mask pattern PM3: The third mask pattern R1, R2, X1, X2: diameter SL: sawing line T1:width U1, U2: thickness V1:Through hole part VH: via hole

FIG. 1 is a plan view illustrating a semiconductor package according to an exemplary embodiment of the inventive concept. FIG. 2 is a cross-sectional view taken along line II' of FIG. 1 . 3 is a plan view showing the top surface of the vertical conductive structure of FIG. 2 . Figure 4 is an enlarged view of part "aa" in Figure 2 . FIG. 5 is an enlarged view of part “aa” in FIG. 2 . FIG. 6 is an enlarged view of part “aa” in FIG. 2 . 7A to 7L are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept. 8 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept. 9A to 9D are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept. 10A and 10B are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept.

1:Semiconductor packaging

10: First rewiring pattern

12: First conductive pattern

14: First seed/barrier pattern

20: First insulation layer

30: Second layer wiring pattern

32: Second conductive pattern

34: Second seed/barrier pattern

40: Second insulation layer

70: Pattern under bump

82: First upper pad

84: Second upper pad

300: Vertical conductive structure

310: Wire

310a: Top surface of wire 310

311:Part One

312:Part 2

320:Metal layer

320a: Top surface of metal layer 320

700: First semiconductor chip

705: First wafer pad

708:Connection terminal

800: Second semiconductor chip

805: Second wafer pad

808: Package connection terminal

810:Packaging substrate

815, 817: Metal gasket

850: Second molded part

908:External connection terminal

950: First molded part

950a: Top surface of first molded part 950

1000: First rewiring base

1000a: first surface of first redistribution substrate 1000

1000b: second surface of first redistribution substrate 1000

2000: The second rewiring base

aa: part

D1: first direction

D2: second direction

D3: Third direction

L1: interconnection part

PK1: The first semiconductor package

PK2: Second semiconductor package

V1:Through hole part

VH: via hole

Claims (20)

A semiconductor package including: First rewiring base; a semiconductor wafer located on the first redistribution substrate; and vertical conductive structures spaced apart from the side surfaces of the semiconductor wafer, Wherein each of the vertical conductive structures includes: conductors; and a metal layer covering the side surface of the conductor, wherein a top surface of the conductor is exposed from the metal layer. The semiconductor package of claim 1, wherein the wire and the metal layer include different metal materials. The semiconductor package of claim 2, wherein the wire includes at least one of silver, gold, or aluminum, and the metal layer includes copper. A semiconductor package as claimed in claim 1, wherein the conductor includes a first metallic material, wherein the metal layer includes a second metal material, wherein the first metal material and the second metal material comprise the same material, and The particle size and crystal orientation of the first metal material are different from the particle size and crystal orientation of the second metal material. A semiconductor package as claimed in claim 1, wherein the conductor includes: a first part; and a second part disposed at an end of the first part and having a hemispherical shape, and wherein the diameter of the hemispherical shape is greater than the width of the first portion. A semiconductor package as claimed in claim 1, wherein the first redistribution substrate includes: an upper pad disposed on a top surface of the first redistribution substrate, wherein the conductive wire and the metal layer are in contact with the upper pad, and Wherein the metal layer and the upper liner comprise the same metal material. The semiconductor package as described in claim 1 further includes: seed pattern, The seed crystal pattern is in contact with the bottom surface of the conductor and the bottom surface of the metal layer. The semiconductor package as described in claim 1 further includes: seed pattern, wherein the seed pattern is in contact with and spaced apart from the bottom surface of the metal layer and the side surface of the lower portion of the conductor. The semiconductor package as described in claim 1 further includes: a molded component covering the top surface and side surfaces of the semiconductor wafer and the side surfaces of the metal layer, Wherein the molded part is spaced apart from the conductors. The semiconductor package as described in claim 9 further includes: a second rewiring substrate located on the molded component, wherein the first rewiring substrate includes: a first insulating layer; and a first rewiring pattern located in the first insulating layer, wherein the second rewiring substrate includes: a second insulating layer; and a second rewiring pattern located in the second insulating layer, and wherein each of the vertical conductive structures is connected to the first redistribution pattern and the second redistribution pattern. The semiconductor package as described in claim 1 further includes: a molded component covering the top and side surfaces of the semiconductor wafer and the side surfaces of each of the vertical conductive structures, wherein a top surface of each of the vertical conductive structures is exposed from the molded component. A semiconductor package including: First rewiring base; a semiconductor wafer located on the first redistribution substrate; and a vertical conductive structure disposed on the first redistribution substrate and spaced apart from a side surface of the semiconductor wafer, Wherein each of the vertical conductive structures includes: wires; and a metal layer covering the side surface of the conductor, Wherein the level of the top surface of the conductor is substantially the same as the level of the top surface of the metal layer. The semiconductor package as described in claim 12 further includes: a second redistribution substrate vertically spaced apart from the first redistribution substrate, with the semiconductor die interposed therebetween, wherein the conductor includes: a first part extending in a linear shape; and a second part disposed at an end of the first part and having a hemispherical shape, and wherein the first portion is connected to the second redistribution substrate, and the second portion is connected to the first redistribution substrate. The semiconductor package of claim 12, wherein the height of the wire is substantially equal to the height of the metal layer. A semiconductor package as claimed in claim 12, wherein said first redistribution substrate includes an upper pad, wherein the conductive wire and the metal layer are in contact with the upper pad, and Wherein the metal layer and the upper liner comprise the same metal material. The semiconductor package as described in claim 12 further includes: seed pattern, wherein the first redistribution substrate includes an upper pad, and Wherein the conductive lines and the metal layer are spaced apart from the upper pad, with the seed pattern interposed therebetween. The semiconductor package as described in claim 12 further includes: seed pattern, wherein said first redistribution substrate includes an upper pad, wherein the metal layer is spaced apart from the upper pad, with the seed pattern interposed therebetween, and The lowermost portion of the conductive line is disposed below the uppermost portion of the seed pattern. A semiconductor package including: first package; and a second package located on said first package, The first package includes: First rewiring base; A first semiconductor chip and a vertical conductive structure located on the first redistribution substrate, each of the vertical conductive structures including a conductor and a metal layer covering a side surface of the conductor; a second redistribution substrate spaced apart from the first redistribution substrate, with the first semiconductor die and the vertical conductive structure interposed therebetween; and a first molding component disposed between the first redistribution substrate and the second redistribution substrate and covering the top surface and side surface of the first semiconductor chip and the side surface of the metal layer, The second package includes: packaging substrate; a second semiconductor chip located on the packaging substrate; and a second molding component covering the top surface of the packaging substrate and the top surface and side surfaces of the second semiconductor chip, wherein the conductor includes: a first part; and a second part disposed at an end of the first part, wherein the first portion has a substantially constant line shape with a width that increases with height in a first direction perpendicular to the top surface of the first redistribution substrate, and the second portion has a width that varies with the height of the first redistribution substrate A shape whose height decreases as it increases in one direction, and The other end of the first part is in contact with the second redistribution substrate, and the second part is in contact with the first redistribution substrate. The semiconductor package of claim 18, wherein the diameter of the second portion is greater than the width of the first portion. The semiconductor package of claim 18, wherein the wires include at least one of silver, gold, or aluminum, and the metal layer includes copper.