CN117524994A - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same Download PDF

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Publication number
CN117524994A
CN117524994A CN202310807708.7A CN202310807708A CN117524994A CN 117524994 A CN117524994 A CN 117524994A CN 202310807708 A CN202310807708 A CN 202310807708A CN 117524994 A CN117524994 A CN 117524994A
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CN
China
Prior art keywords
substrate
underfill
semiconductor package
pattern
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310807708.7A
Other languages
Chinese (zh)
Inventor
朴钟淏
姜圭浩
朴成根
裵晟训
郑载穆
崔朱逸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020220137589A external-priority patent/KR20240020260A/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN117524994A publication Critical patent/CN117524994A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout

Abstract

The present disclosure relates to a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a first substrate; a semiconductor chip on the first substrate; a second substrate spaced apart from the first substrate; a lead spaced apart from a side surface of the semiconductor chip and connecting the first substrate to the second substrate; a molding structure on the top surface of the semiconductor chip, the side surfaces of the semiconductor chip, and the side surfaces of the leads; and an underfill pattern on a side surface of the lead and between the lead and the molded structure.

Description

Semiconductor package and method of manufacturing the same
Technical Field
The present disclosure relates to a semiconductor package and a method of manufacturing the same.
Background
A semiconductor package is provided to implement an integrated circuit chip to qualify for use in an electronic product. Semiconductor packages are typically configured such that a semiconductor chip is mounted on a printed circuit board and wirebonds or bumps are used to electrically connect the semiconductor chip to the printed circuit board. With the development of the electronic industry, various researches have been conducted to improve reliability and durability of semiconductor packages.
Disclosure of Invention
One or more example embodiments provide a semiconductor package having increased reliability and a method of manufacturing a semiconductor package having increased reliability.
According to an aspect of an example embodiment, a semiconductor package includes: a first substrate; a semiconductor chip on the first substrate; a second substrate spaced apart from the first substrate; leads spaced apart from the side surfaces of the semiconductor chip, wherein the leads connect the first substrate to the second substrate; a molded structure on the top surface of the semiconductor chip, the side surfaces of the semiconductor chip, and the side surfaces of the leads; and an underfill pattern on a side surface of the leads and between the leads and the molded structure.
According to an aspect of an example embodiment, a semiconductor package includes: a first sub-semiconductor package; and a second sub-semiconductor package on the first sub-semiconductor package, wherein the first sub-semiconductor package comprises: a lower substrate; a first semiconductor chip on the lower substrate; an upper substrate spaced apart from the lower substrate; a plurality of leads horizontally spaced apart from a side surface of the first semiconductor chip, wherein the leads extend vertically from the lower substrate toward the upper substrate; and a plurality of first underfill patterns covering the side surfaces of the leads, wherein the first underfill patterns are spaced apart from the first semiconductor chip.
According to an aspect of an example embodiment, a semiconductor package includes: a first sub-package; and a second sub-package on the first sub-package, wherein the first sub-package comprises: a lower substrate; a first semiconductor chip and a plurality of leads on a lower substrate; at least one underfill pattern covering a side surface of the lead; an upper substrate spaced apart from the lower substrate; and a first molding structure between the lower substrate and the upper substrate, wherein the first molding structure is disposed on top and side surfaces of the first semiconductor chip and side surfaces of the underfill pattern, wherein the second sub-package includes: packaging a substrate; a second semiconductor chip on the package substrate; and a second molding structure on the top surface of the package substrate and the top and side surfaces of the second semiconductor chip, wherein the top surface of the underfill pattern is at a level higher than that of the top surface of the first semiconductor chip.
According to an aspect of an example embodiment, a method of manufacturing a semiconductor package includes: preparing a first substrate including a first upper pad and a second upper pad spaced apart from each other; attaching bonding wires to corresponding first upper pads; forming an underfill pattern on the bonding wire; mounting a semiconductor chip on the first substrate to vertically overlap the second upper pad; and forming a molding structure on the underfill pattern and the semiconductor chip.
Drawings
The above and other aspects and features will become more apparent from the following description of exemplary embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 illustrates a plan view showing a semiconductor package according to some embodiments of the inventive concept.
Fig. 2 shows a cross-sectional view taken along line I-I' of fig. 1.
Fig. 3 shows an enlarged view of the portion aa showing fig. 2.
Fig. 4 illustrates a plan view showing a semiconductor package according to some embodiments of the inventive concept.
Fig. 5 shows a cross-sectional view taken along line II-II' of fig. 4.
Fig. 6 shows an enlarged view showing a portion bb of fig. 5.
Fig. 7A to 7L illustrate cross-sectional views showing methods of manufacturing a semiconductor package according to some embodiments of the inventive concept.
Fig. 8A to 8D illustrate cross-sectional views showing methods of manufacturing a semiconductor package according to some embodiments of the inventive concept.
Detailed Description
Example embodiments will be described more fully with reference to the accompanying drawings, in which example embodiments are shown. The embodiments described herein are provided as examples, and thus, the present disclosure is not limited thereto and may be implemented in various other forms. Each embodiment provided in the following description does not preclude the association with one or more features of another example or another embodiment also provided or not provided herein but consistent with the present disclosure. It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. A phrase such as "at least one of … …" when following a column of elements, modifies the entire column of elements without modifying individual elements of the list. For example, the expression "at least one of a, b and c" should be understood to include a only a, b only, c only, both a and b, both a and c, both b and c, or all of a, b and c.
Fig. 1 illustrates a plan view showing a semiconductor package according to some embodiments. Fig. 2 shows a cross-sectional view taken along line I-I' of fig. 1. Fig. 3 shows an enlarged view of the portion aa showing fig. 2.
Referring to fig. 1 and 2, the semiconductor package 1 may include a first sub-semiconductor package PK1 and a second sub-semiconductor package PK2 on the first sub-semiconductor package PK1. The semiconductor package 1 may have a package-on-package structure.
The first sub-semiconductor package PK1 may include a first substrate 1000, a first semiconductor chip 700, a second substrate 2000, a lead 300, and a first molding structure 950. The first and second substrates 1000 and 2000 may be referred to as a lower substrate 1000 and an upper substrate 2000, respectively.
The first substrate 1000 may have a first surface 1000a and a second surface 1000b facing the first surface 1000a such that the first surface 1000a and the second surface 1000b face each other. The first direction D1 is defined to mean a direction parallel to the first surface 1000a of the first substrate 1000. The second direction D2 is defined to mean a direction parallel to the first surface 1000a and perpendicular to the first direction D1. The third direction D3 is defined to mean a direction perpendicular to the first surface 1000a of the first substrate 1000.
The first substrate 1000 may be a Printed Circuit Board (PCB) or a redistribution substrate.
When the first substrate 1000 is a redistribution substrate, as shown in fig. 2, the first substrate 1000 may include a first redistribution pattern 10, a first dielectric layer 20, and an under bump pattern 70. The first redistribution pattern 10 and the under bump pattern 70 may be disposed in the first dielectric layer 20. As shown in fig. 2, in one embodiment, there may be a plurality of first dielectric layers 20. In other embodiments, the first dielectric layer 20 may be considered a dielectric layer other than that shown. The first dielectric layer 20 may comprise a photoimageable dielectric material. For example, the first dielectric layer 20 may include at least one selected from a photosensitive polyimide, a polybenzoxazole, a phenolic polymer, and a benzocyclobutene polymer.
The under bump pattern 70 may be disposed on the second surface 1000b of the first substrate 1000. The bottom surface of each under bump pattern 70 may be exposed from the first dielectric layer 20. The under bump pattern 70 may include at least one of copper or aluminum, for example.
The first re-distribution pattern 10 may be stacked on the under bump pattern 70. Each redistribution pattern 10 may include a first conductive pattern 12 and a first seed/barrier pattern 14. For example, the first conductive pattern 12 may include copper, and the first seed/barrier pattern 14 may include copper/titanium.
The first seed/barrier pattern 14 may be provided locally on the bottom surface of the first conductive pattern 12. Each first reconfiguration pattern 10 may include a via portion V1 and a line portion L1, the via portion V1 and the line portion L1 being connected to form a single integral piece. The via portion V1 of the first re-distribution pattern 10 may fill the via hole VH of the first dielectric layer 20 and may be connected to the under bump pattern 70 or the line portion L1 of another first re-distribution pattern 10 under the first re-distribution pattern 10.
The first and second upper pads 82 and 84 may be provided on the uppermost first redistribution pattern 10 in the first redistribution pattern 10. The first upper pad 82 and the second upper pad 84 may have substantially the same configuration as the first re-distribution pattern 10. For example, each of the first and second upper pads 82 and 84 may include the first conductive pattern 12 and the first seed/barrier pattern 14.
The first semiconductor chip 700 may be provided on the first substrate 1000. The first semiconductor chip 700 may be, for example, a logic chip or a memory chip such as a DRAM or a NAND flash memory. The first semiconductor chip 700 may be disposed on the first substrate 1000 to allow the first chip pad 705 of the first semiconductor chip 700 to face the first substrate 1000.
The connection terminal 708 may contact and be electrically connected to the first upper pad 82 and the first chip pad 705. The first semiconductor chip 700 may be electrically connected to the connection terminal 708 and electrically connected to the first substrate 1000 through the connection terminal 708. The connection terminal 708 may include at least one selected from the group consisting of solder, a post, and a bump. The connection terminal 708 may include a conductive material such as tin (Sn) or silver (Ag).
The leads 300 may be disposed on the first surface 1000a of the first substrate 1000 and spaced apart from the side surface of the first semiconductor chip 700. The underfill pattern 400 may be disposed on and cover a side surface of the lead 300. The wire 300 may be referred to as a bonding wire 300. The underfill pattern 400 may be referred to as a first underfill pattern 400. The leads 300 and the first underfill pattern 400 will be discussed in further detail below.
The second substrate 2000 may be disposed on the top surface 950a of the first mold structure 950, the top surface 300a of the lead 300, and the top surface of the first underfill pattern 400. The second substrate 2000 may be a redistribution substrate.
The second substrate 2000 may include a second dielectric layer 40 and a second redistribution pattern 30. The second dielectric layer 40 may be the same or similar photoimageable dielectric layer as the first dielectric layer 20. The second redistribution pattern 30 may include a second conductive pattern 32 and a second seed/barrier pattern 34. The second conductive pattern 32 and the second seed/barrier pattern 34 may include the same or similar materials as those of the first conductive pattern 12 and the first seed/barrier pattern 14, respectively. Like the first redistribution pattern 10, the second redistribution pattern 30 may have a via portion V1 and a line portion L1 connected to the via portion V1.
The second sub-semiconductor package PK2 may be provided on the second substrate 2000. The second sub-semiconductor package PK2 may include a package substrate 810, a second semiconductor chip 800, and a second mold structure 850. The package substrate 810 may be a printed circuit board or a redistribution substrate. The package substrate 810 may be provided with metal pads 815 and 817 on opposite surfaces thereof. The second semiconductor chip 800 may be, for example, a memory chip or a logic chip. The second semiconductor chip 800 may be of a different type from the first semiconductor chip 700. For example, the second semiconductor chip 800 may have a second chip pad 805 on one surface thereof, the second chip pad 805 being wire-bonded to a metal pad 815 of the package substrate 810.
The package bonding terminals 808 may be disposed between the first and second sub-semiconductor packages PK1 and PK2. The package bonding terminals 808 may be in contact with the metal pads 817 and the uppermost second redistribution patterns 30 among the second redistribution patterns 30. The package bonding terminals 808 may be electrically connected to the second redistribution pattern 30 and the metal pads 817. Accordingly, the second sub-semiconductor package PK2 may be electrically connected to the first semiconductor chip 700 and the external bonding terminals 908 through the package bonding terminals 808, the second substrate 2000, the leads 300, and the first substrate 1000.
The lead 300 may connect the first substrate 1000 to the second substrate 2000. The leads 300 may be arranged such that they are spaced apart from each other along the first direction D1 and the second direction D2. The lead 300 may be disposed on the second upper pad 84. Each of the leads 300 may extend along the third direction D3.
The lead 300 may include a metal material. The lead 300 may include at least one selected from gold, silver, copper, and aluminum, for example. As shown in fig. 3, the lead 300 may include a first portion 311, a second portion 312, and a third portion 313. The second portion 312 may be interposed between the first portion 311 and the third portion 313. According to some embodiments, the second portion 312 may be omitted, and the first portion 311 and the third portion 313 may be directly connected to each other. The first portion 311 may have a linear shape with a length of about 10 times the width when viewed in a vertical cross-section, and the second portion 312 may have a rectangular or square shape. In an embodiment, the first portion 311 may have a linear shape with a length that is 10 times or more the width. The third portion 313 may have an oval shape.
The length of the first portion 311 in the third direction D3 may be greater than the length of the second portion 312 in the third direction D3 and the length of the third portion 313 in the third direction D3. The length of the first portion 311 in the third direction D3 may be greater than the sum of the lengths of the second portion 312 and the third portion 313 in the third direction D3.
The first, second and third portions 311, 312 and 313 may have first, second and third diameters, respectively, in the first direction D1. The third diameter may be greater than the second diameter, and the second diameter may be greater than the first diameter. The first diameter may be substantially constant along the third direction D3. The third diameter may have a maximum near a substantial center of the third portion 313 in the third direction D3. In an embodiment, the third diameter may decrease away from the vertical center along a third direction D3. For example, in an embodiment, the third diameter may decrease along a third direction D3 perpendicular away from the first surface 1000a of the first substrate 1000.
The first underfill pattern 400 may include a dielectric material. The first underfill pattern 400 may include, for example, epoxy.
The first underfill patterns 400 may be spaced apart from each other while making one-to-one contact with the leads 300. The first underfill pattern 400 may expose the top surface 300a of the lead 300 while being disposed on the side surface of the lead 300 and covering the side surface of the lead 300. As shown in fig. 3, the first underfill pattern 400 may be in contact with the side surfaces of the first portion 311, the second portion 312, the third portion 313, and the top surface of the second upper pad 84. The distance between opposite side surfaces of the first underfill pattern 400 or the width in the first direction D1 may increase in a direction from the first portion 311 toward the third portion 313.
An interface may be provided between the first underfill pattern 400 and the first mold structure 950. The first underfill pattern 400 and the first molding structure 950 may each include epoxy and silicon dioxide (SiO 2 ). The first underfill pattern 400 and the first molding structure 950 may further include different materials other than epoxy and silicon dioxide. For example, unlike the first underfill pattern 400, the first molding structure 950 may also include carbon black and/or a mold release agent.
The first underfill pattern 400 may not contact the first semiconductor chip 700. The first underfill pattern 400 may be spaced apart from an active surface of the first semiconductor chip 700 on which the first chip pad 705 is disposed.
The second underfill pattern 600 may be interposed between the active surface of the first semiconductor chip 700 and the first surface 1000a of the first substrate 1000. The second underfill pattern 600 may be disposed on and cover a side surface of the connection terminal 708. According to some embodiments, the second underfill pattern 600 may include the same material as that of the first underfill pattern 400. The first and second underfill patterns 400 and 600 may be spaced apart from each other. According to some embodiments, the second underfill pattern 600 may be omitted. In this case, the first mold structure 950 may be disposed on and cover a side surface of the connection terminal 708 while filling a space between the first substrate 1000 and the active surface of the first semiconductor chip 700.
Referring back to fig. 1 and 2, the top surface 300a of the lead 300 may be exposed from the top surface 950a of the first mold structure 950. In addition, the top surface 300a of the lead 300 may be exposed from the top surface of the first underfill pattern 400. Coplanarity may exist between the top surface 950a of the first molding structure 950, the top surface 300a of the lead 300, and the top surface of the first underfill pattern 400. The top surface 300a of the lead 300 may be located at substantially the same level as that of the top surface of the first underfill pattern 400. The lead 300 may have a height substantially the same as that of the first underfill pattern 400. The height of each of the lead 300 and the first underfill pattern 400 may represent a length in the third direction D3 from the top surface of the second upper pad 84.
As shown in fig. 1, the lead 300 may have a circular or almost circular shape at the top surface 300a exposed from the first molding structure 950. The first underfill pattern 400 may have a ring shape at an exposed top surface thereof.
In an embodiment, in order to improve heat radiation characteristics of the semiconductor package 1 or the first sub-semiconductor package PK1, the first semiconductor chip 700 may have a thickness equal to or greater than a specific value. In this case, there may be a connection mechanism by which the lower substrate 1000 and the upper substrate 2000 are connected to each other, and the connection mechanism may be formed to have a height greater than the thickness of the first semiconductor chip 700. In the inventive concept, the lead 300 may be used as a connection mechanism so that the lead 300 (or the connection mechanism) may be easily increased. In addition, the rigidity of the leads can be enhanced by the underfill, and thus the semiconductor package can be increased in reliability. Further, the leads may be formed with a fine pitch therebetween, and thus the leads may be arranged with a fine pitch.
Fig. 4 illustrates a plan view showing a semiconductor package according to some embodiments. Fig. 5 shows a cross-sectional view taken along line II-II' of fig. 4. Fig. 6 shows an enlarged view showing a portion bb of fig. 5. A description repeated with the descriptions discussed with reference to fig. 1 to 3 will be omitted except for the following description.
Referring to fig. 4 and 5, the semiconductor package 2 may be provided, wherein the first underfill patterns 400 may each extend along the first direction D1, and wherein the first underfill patterns 400 may be spaced apart from each other along the second direction D2. Each of the first underfill patterns 400 may have a linear shape extending along the first direction D1 when viewed in a plan view. The single first underfill pattern 400 may be in contact with side surfaces of the plurality of leads 300 adjacent to each other along the first direction D1. For example, the underfill pattern 400 may be in one-to-many contact with the lead 300.
Referring to fig. 6, the first underfill pattern 400 may fill at least a portion of the gap between adjacent second upper pads 84. The first underfill pattern 400 may contact the side surface of the second upper pad 84. The first underfill pattern 400 may contact the uppermost first dielectric layer 20 of the first substrate 1000.
Fig. 7A to 7L illustrate cross-sectional views showing methods of manufacturing a semiconductor package according to some embodiments.
Referring to fig. 7A, a carrier substrate CR may be provided having an adhesive layer AD formed on one surface thereof. A seed/barrier layer 14a may be formed on the carrier substrate CR to cover the top surface of the adhesive layer AD. The seed/barrier layer 14a may be formed by a deposition process. For example, the seed/barrier layer 14a may include copper/titanium (Cu/Ti). The adhesive layer AD may attach the seed/barrier layer 14a to the top surface of the carrier substrate CR.
The first photomask pattern PM1 may be formed on the top surface of the seed/barrier layer 14a. The first photomask pattern PM1 may include openings defining spaces in which the under bump patterns 70 are formed. The first photomask pattern PM1 may be formed by forming a photoresist layer, exposing the photoresist layer, and developing the photoresist layer. The first photomask pattern PM1 may expose a portion of the seed/barrier layer 14a. The under bump pattern 70 may be formed in the opening by performing an electroplating process in which the seed/barrier layer 14a serves as an electrode.
Referring to fig. 7B, the first photomask pattern PM1 may be removed. The first dielectric layer 20 may be formed to cover the under bump pattern 70. The first dielectric layer 20 may be formed through a process such as spin coating, and then an exposure and development process may be performed to pattern the first dielectric layer 20 so as to have an opening exposing the top surface of the under bump pattern 70. Thereafter, a curing process may be performed on the first dielectric layer 20. The seed/barrier layer 14a may again be formed on the first dielectric layer 20. The second photomask pattern PM2 including openings may be formed on the seed/barrier layer 14a. An electroplating process in which the seed/barrier layer 14a serves as an electrode may be performed to form the first conductive pattern 12 on the seed/barrier layer 14a.
Referring to fig. 7C, the second photomask pattern PM2 may be removed. The first seed/barrier pattern 14 may be formed by removing the seed/barrier layer 14a on the region exposed from the first conductive pattern 12. A first redistribution pattern 10 including a first conductive pattern 12 and a first seed/barrier pattern 14 may be formed.
Referring to fig. 7D, similar to the method for forming the first dielectric layer 20 and the first redistribution pattern 10, another first dielectric layer 20 and another first redistribution pattern 10 may be sequentially and repeatedly stacked. After stacking the uppermost first redistribution pattern 10, the first dielectric layer 20 may be formed to partially expose the uppermost first redistribution pattern 10. The uppermost first dielectric layer 20 may be formed by spin coating, exposure, development, and curing processes. A seed/barrier layer 14a may be formed on the uppermost first dielectric layer 20. After that, a third photomask pattern PM3 including openings may be formed. An electroplating process in which the seed/barrier layer 14a serves as an electrode may be performed to form the first conductive pattern 12 on the seed/barrier layer 14a. The seed/barrier layer 14a and the first conductive pattern 12 may constitute a first preliminary upper pad 82P and a second preliminary upper pad 84P.
Referring to fig. 7E, a wire bonding process may be performed. The lead 300 may be disposed on the second preliminary upper pad 84P. A wire control machine 500 capable of moving and adjusting the length may be used to place the wire 300 on the second initial upper pad 84P.
The lead control machine 500 may include a lead spool, a lead tensioning system, a lead clamp 510, a capillary 520, and an electric-flag-off (EPO). The wire control machine 500 may be a typical wire control machine.
The lead 300 may include a wire portion having a large length and a bonding portion having a small length and a large width. The lead 300 may pass through the capillary 520 to form a tail portion slightly protruding from the capillary 520, so that the bonding portion may be exposed from the capillary 520. The EPO may provide a spark to the joint to form a bulb at one end of the joint.
The ball-shaped portion of the lead 300 may be attached to the top surface of the second preliminary upper pad 84P, and an external force may be applied. The shape of the spherical portion may be adjusted by a combination of external force, heat and/or ultrasound. Capillary 520 may again be used to adjust the length of wire 300 and then wire 300 may be cut. Accordingly, the wire portion, the joint portion, and the ball portion may be formed as the first portion 311, the second portion 312, and the third portion 313 of fig. 3, respectively.
Referring to fig. 7F and 7G, each of the leads 300 may be provided with an uncured underfill material 400P thereon so as to be disposed on and cover the top and side surfaces of the leads 300. The underfill material 400P may be introduced or flowed from the nozzle 400S, and the flow rate may be adjusted by the diameter of the nozzle 400S. The underfill material 400P may be introduced to each of the leads 300 individually.
Thereafter, as shown in fig. 7G, the underfill material 400P may be cured to form a first underfill pattern 400.
Referring to fig. 7H, the third photomask pattern MP3 may be removed. Thereafter, the first seed/barrier pattern 14 may be formed by removing the seed/barrier layer 14a that does not overlap the first conductive pattern 12. Accordingly, the first and second preliminary upper pads 82P and 84P may be formed as the first and second upper pads 82 and 84, respectively. Meanwhile, the first substrate 1000 may also be formed.
The first semiconductor chip 700 may be mounted on the first substrate 1000 to allow the first chip pad 705 of the first semiconductor chip 700 to face the first substrate 1000. A hot pressing process may be performed to place the first semiconductor chip 700 on the first substrate 1000. The first upper pad 82 may be correspondingly attached thereto, and the connection terminal 708 is attached to the first chip pad 705. The second underfill pattern 600 may be formed by introducing and curing an underfill material. According to some embodiments, the formation of the second underfill pattern 600 may be omitted.
Referring to fig. 7I, a first molding structure 950 may be formed to cover top and side surfaces of the first underfill pattern 400, the first surface 1000a of the first substrate 1000, and top and side surfaces of the first semiconductor chip 700. The first molding structure 950 may be formed by introducing and solidifying a molding material in a molten state. The molding material may include, for example, a melted Epoxy Molding Compound (EMC).
According to an embodiment, the underfill pattern 400 may fix the leads 300 when the molding material is introduced. Therefore, even when the molding material is introduced, the lead 300 can be prevented from being swept, and even after the molding material is introduced, the lead 300 can maintain its shape extending in the third direction D3 without being inclined.
When the formation of the second underfill pattern 600 is omitted, the first mold structure 950 may be formed to be disposed on and cover the first surface 1000a and the top and side surfaces of the first semiconductor chip 700 and to fill the space between the bottom surface of the first semiconductor chip 700 and the first surface 1000a of the first substrate 1000. The first mold structure 950 may be formed to seal the lead 300 and the first underfill pattern 400.
Referring to fig. 7J, a planarization process may be performed on the first mold structure 950. The planarization process may continue until the top surface 300a of the lead 300 is exposed. As a result of the planarization process, coplanarity may exist between the top surface 950a of the first molding structure 950, the top surface 300a of the lead 300, and the top surface of the first underfill pattern 400.
Referring to fig. 7K, a second substrate 2000 may be formed on the first mold structure 950 and the lead 300. The second substrate 2000 may be formed by substantially the same method as that used to form the first substrate 1000. The second redistribution pattern 30 may be formed to be connected with the lead 300.
Referring to fig. 7L, a dividing process is performed along the cutting line SL in the third direction D3. Thereafter, the carrier substrate CR, the adhesive layer AD, and the seed/barrier layer 14a may be removed. An etching process may be performed to remove the seed/barrier layer 14a. Removal of the seed/barrier layer 14a may expose the under bump pattern 70.
Referring back to fig. 2, external bonding terminals 908 may be formed on the exposed under bump patterns 70, and thus the first sub-semiconductor package PK1 may be formed. The second sub-semiconductor package PK2 may be mounted on the first sub-semiconductor package PK1. Accordingly, the semiconductor package 1 may be manufactured to have a package-on-package structure in which the second sub-semiconductor package PK2 is stacked on the first sub-semiconductor package PK1.
Fig. 8A to 8D illustrate cross-sectional views showing methods of manufacturing a semiconductor package according to some embodiments.
Referring to fig. 7E and 8A, after the wire bonding process, the third photomask pattern PM3 may be removed. Thereafter, the first seed/barrier pattern 14 may be formed by removing the seed/barrier layer 14a that does not overlap the first conductive pattern 12. Meanwhile, the first upper pad 82, the second upper pad 84, and the first substrate 1000 may be formed.
Referring to fig. 8B, one first underfill pattern 400 may be formed to be disposed on the plurality of leads 300 and cover the plurality of leads 300. The underfill material may be introduced along the first direction D1 to form a first underfill pattern 400 (see fig. 4) having a linear shape. In this embodiment, the first underfill pattern 400 may be formed at a higher speed than that at which the first underfill pattern 400 is formed on each of the leads 300 in the foregoing case. In the embodiment in which the first underfill pattern 400 is formed on each of the leads 300, the side surfaces of the leads 300 may be finely covered as compared to this case (see fig. 7G).
Referring to fig. 8C, a first semiconductor chip 700 may be mounted on the first substrate 1000. The second underfill pattern 600 may be formed by introducing and curing an underfill material, but according to some embodiments, the formation of the second underfill pattern 600 may be omitted. The first molding structure 950 may be formed to cover the top and side surfaces of the first underfill pattern 400, the first surface 1000a of the first substrate 1000, and the top and side surfaces of the first semiconductor chip 700.
Referring to fig. 8D, the first mold structure 950 may undergo a planarization process until the lead 300 is exposed. Accordingly, the first molding structure 950, the lead 300, and the first underfill pattern 400 may have their top surfaces substantially coplanar with each other.
The subsequent process may be the same as the process discussed with reference to fig. 7K, 7L and 2, and as a result, the semiconductor package 2 as shown in fig. 5 may be manufactured.
When the vertical conductive structure is formed as a connection mechanism by which the first substrate and the second substrate are connected to each other, it may be difficult to increase the height of the vertical conductive structure. For example, when a plating process is used to form vertical conductive structures, more than two layers of photoresist patterns may be required to form deep openings. Therefore, the formation of the vertical conductive structure may consume much time and cause an increase in cost.
Embodiments may use leads instead of vertical conductive structures. Since the height of the wire can be easily increased and the wire does not require a plating process, the use of multiple photoresist layers may not be required. For example, an underfill material may be introduced onto the leads and then cured, so that the leads may not bend even when the molding material is provided. As a result, when the second substrate is formed, the lead and the lower pad of the second substrate can be satisfactorily connected to each other without misalignment.
The semiconductor package according to the embodiment may have a Package On Package (POP) structure. The first sub-package located at the bottom side may use the leads as a connection mechanism between the lower substrate and the upper substrate. A plurality of leads may be arranged to have not only easy control of the height thereof but also a fine pitch therebetween. When the semiconductor chip in the semiconductor package has an increased thickness to improve heat radiation characteristics, the height of the leads can be easily increased. In addition, an underfill pattern may be provided between the leads and the molded structure. The underfill pattern may be in contact with the leads. The underfill pattern may enhance the rigidity of the leads, so that when the molded structure is formed, the leads may maintain their shape extending in the vertical direction without being swept. As a result, the leads can be prevented from contacting each other (reducing the risk of short circuits). Further, when the upper substrate is formed on the leads, misalignment between the upper substrate and the leads can be reduced. Accordingly, in one embodiment, the reliability of the semiconductor package and its manufacturing process may be increased.
While aspects of the example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.
The present application claims priority from korean patent application No. 10-2022-0097564 filed on 8 th month 4 of 2022 and korean patent application No. 10-2022-0137589 filed on 10 th month 24 of 2022, the disclosures of which are incorporated herein by reference in their entireties.

Claims (20)

1. A semiconductor package, comprising:
a first substrate;
a semiconductor chip on the first substrate;
a second substrate spaced apart from the first substrate;
a lead spaced apart from a side surface of the semiconductor chip, wherein the lead connects the first substrate to the second substrate;
a molded structure on a top surface of the semiconductor chip, the side surface of the semiconductor chip, and a side surface of the lead; and
an underfill pattern on the side surface of the leads and between the leads and the molded structure.
2. The semiconductor package of claim 1, wherein the leads comprise at least one of silver, gold, and aluminum.
3. The semiconductor package of claim 1, wherein:
the first substrate includes an upper pad on a top surface of the first substrate, an
The underfill pattern contacts the upper pad.
4. The semiconductor package of claim 1, wherein:
the underfill pattern has a ring shape surrounding the leads when viewed in plan view, an
A top surface of the leads is exposed from the underfill pattern.
5. The semiconductor package of claim 1, wherein:
the underfill pattern has a first width in a first direction parallel to the top surface of the first substrate, an
The first width increases with decreasing distance from the first substrate.
6. The semiconductor package of claim 1, wherein a top surface of the leads, a top surface of the underfill pattern, and a top surface of the molded structure are coplanar.
7. The semiconductor package of claim 1, wherein:
the first substrate comprises a printed circuit board
The second substrate includes a redistribution substrate.
8. The semiconductor package of claim 1, wherein each of the first substrate and the second substrate comprises a redistribution substrate.
9. A semiconductor package, comprising:
a first sub-semiconductor package; and
a second sub-semiconductor package on the first sub-semiconductor package,
wherein the first sub-semiconductor package comprises:
a lower substrate;
a first semiconductor chip on the lower substrate;
an upper substrate spaced apart from the lower substrate;
a plurality of leads horizontally spaced apart from a side surface of the first semiconductor chip, wherein the leads extend vertically from the lower substrate toward the upper substrate; and
a plurality of first underfill patterns covering side surfaces of the leads,
wherein the first underfill pattern is spaced apart from the first semiconductor chip.
10. The semiconductor package of claim 9, wherein:
the leads are disposed along a first direction and a second direction parallel to a top surface of the lower substrate, wherein the second direction intersects the first direction,
each of the first underfill patterns extends along the first direction to contact at least one of the leads, and
the first underfill patterns are spaced apart from each other along the second direction.
11. The semiconductor package of claim 10, wherein each of the first underfill patterns has a linear shape extending along the first direction when viewed in a plan view.
12. The semiconductor package of claim 9, wherein each of the first underfill patterns has a ring shape when viewed in plan.
13. The semiconductor package of claim 9, wherein the first sub-semiconductor package further comprises:
a plurality of connection terminals on an active surface of the first semiconductor chip; and
a second underfill pattern covering a side surface of the connection terminal,
wherein the first and second underfill patterns are spaced apart from each other.
14. The semiconductor package of claim 9, wherein:
each of the leads includes a first portion, a second portion and a third portion,
the second portion is between the first portion and the third portion, and
the height of the first portion is greater than the sum of the height of the second portion and the height of the third portion.
15. The semiconductor package of claim 14, wherein:
the first portion having a first diameter, the second portion having a second diameter, the third portion having a third diameter,
the third diameter is larger than the second diameter, and
the second diameter is greater than the first diameter.
16. A method of manufacturing a semiconductor package, the method comprising:
preparing a first substrate including a first upper pad and a second upper pad spaced apart from each other;
attaching bonding wires to corresponding first upper pads;
forming an underfill pattern on the bonding wire;
mounting a semiconductor chip on the first substrate to vertically overlap the second upper pad; and
a molding structure is formed on the underfill pattern and the semiconductor chip.
17. The method of claim 16, wherein forming the underfill pattern comprises:
an underfill material is introduced over each of the bond wires,
wherein the underfill patterns are in one-to-one contact with the bonding wires and the underfill patterns are spaced apart from each other.
18. The method of claim 16, wherein forming the underfill pattern comprises:
an underfill material is introduced over some of the bonding wires, wherein some of the bonding wires are adjacent to each other along a first direction parallel to the top surface of the first substrate,
wherein the underfill pattern is in one-to-many contact with the bond wires.
19. The method of claim 16, wherein forming the molded structure comprises:
introducing a molding material covering the underfill pattern and the semiconductor chip on the first substrate;
curing the molding material; and
the cured molding material and the underfill pattern are planarized until the top surfaces of the bonding wires are exposed.
20. The method of claim 16, further comprising:
forming a second substrate connected to the bonding wires after forming the molded structure; and
a sub-semiconductor package is attached to the second substrate.
CN202310807708.7A 2022-08-04 2023-07-03 Semiconductor package and method of manufacturing the same Pending CN117524994A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR10-2022-0097564 2022-08-04
KR10-2022-0137589 2022-10-24
KR1020220137589A KR20240020260A (en) 2022-08-04 2022-10-24 Semiconductor package and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN117524994A true CN117524994A (en) 2024-02-06

Family

ID=89750108

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310807708.7A Pending CN117524994A (en) 2022-08-04 2023-07-03 Semiconductor package and method of manufacturing the same

Country Status (1)

Country Link
CN (1) CN117524994A (en)

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