TW202335232A - Overlay metrology mark - Google Patents

Abstract

The present application provides an overlay metrology mark for determining an overlay error between two successive layers of a substrate. The overlay metrology mark includes a first axis, a second axis, a target feature, a first alignment feature, and a second alignment feature. The second axis crosses the first axis. The target feature is disposed at an intersection of the first axis and the second axis. The first alignment feature is arranged on the first axis, the second alignment feature is arranged on the second axis, and the first and second alignment features are in pairs.

Description

Overlay measurement marks

This application claims priority to U.S. Patent Application Nos. 17/672,862 and 17/673,155 (that is, the priority date is "February 16, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to an overlay mark for checking alignment accuracy. More particularly, it relates to a stack of measurement marks for aligning different layers of a substrate.

The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced several generations of integrated circuits, each of which is smaller and more complex than the previous generation. Today, semiconductor devices and integrated circuits include multiple multilayer structures with dimensions less than one micron.

As is known in the art, a lithography process is a step in determining critical dimensions during the fabrication of semiconductor integrated circuit devices. An electronic circuit pattern is formed by first transferring a pattern on a reticle to a photoresist layer using a lithography process, and then transferring the pattern from the photoresist layer in a subsequent etching process. to a lower material layer, such as a dielectric layer or a metal layer.

A successful lithography process on a wafer depends on control of critical dimensions and alignment accuracy. As the scale of integrated circuits continues to shrink, especially below 20 nanometers, it has become increasingly difficult to accurately align multiple layers. Therefore, a measurement of accuracy, that is, measurement of overlay error, is critical to the semiconductor manufacturing process. A pair of masks is used as a tool to measure overlay errors and determine whether a photoresist pattern is accurately aligned with the previous layer on a wafer after the lithography process.

If all or part of the overlay mask is not aligned correctly, the resulting features may not align correctly with adjacent layers. This may result in reduced component performance or complete component failure. While existing overlay (gauge) marks have been used to prevent incorrect alignment, this approach is not entirely satisfactory for small size components.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

One embodiment of the present disclosure provides an overlay measurement mark for confirming an overlay error between two consecutive layers of a substrate. The overlay measurement mark includes a first axis, a second axis, a target feature, a first alignment feature and a second alignment feature. The second axis intersects the first axis. The target feature is set at an intersection of the first axis and the second axis. The first alignment feature is disposed on the first axis, the second alignment feature is disposed on the second axis, and the first alignment feature and the second alignment feature are disposed in pairs.

In some embodiments, the first axis, the second axis, the target feature, the first alignment feature, and the second alignment feature are disposed in at least one cutting line of the substrate.

In some embodiments, a shortest distance between the first axis and the second alignment feature is equal to a shortest distance between the second axis and the first alignment feature.

In some embodiments, the target feature is disposed on a first layer of the substrate, and the first axis, the second axis, the first alignment feature, and the second alignment feature are disposed on the first layer. Above or below a second floor.

In some embodiments, the target feature includes a two-line segment, and when the first layer and the second layer are correctly aligned, the first axis and the second axis respectively overlap with the two-line segment.

In some embodiments, the first axis is orthogonal to the second axis.

In some embodiments, the target feature has a cross shape.

In some embodiments, the first alignment feature and the second alignment feature are each composed of a plurality of repetitive micro-structures.

In some embodiments, the first alignment feature and the second alignment feature each have a square outline and are composed of a plurality of square microstructures.

In some embodiments, the microstructures are separated from each other by a pair of vacant regions.

In some embodiments, the vacancy areas have a first width, and the microstructures have a second width, and the second width is greater than the first width.

In some embodiments, the pair of voids includes a horizontal void and a longitudinal void, the first axis extends through the horizontal void of the first alignment feature at the first axis, and the third Two axes extend through the longitudinal void of the second alignment feature located at the second axis.

One embodiment of the present disclosure provides an overlay measurement mark for confirming multiple relative positions of a plurality of consecutive patterned layers of a substrate. The overlay measurement mark includes a first axis, a second axis, a target feature and a plurality of alignment features. The second axis is orthogonal and crosses the first axis. The target feature is set at an intersection of the first axis and the second axis. The plurality of alignment features are disposed along the first axis and the second axis.

In some embodiments, a distance between adjacent pairs of alignment features is fixed.

In some embodiments, the adjacent pairs of alignment features are separated from the intersection of the first axis and the second axis by an equal distance, and the adjacent pairs of alignment features are configured to determine The relative positions of the plurality of consecutive patterned layers.

In some embodiments, the first axis separates the second axis into an upper section and a lower section; the second axis separates the first axis into a left section and a right section; and is provided on the upper section. The plurality of alignment features at the section and the lower section determine the relative positions of the plurality of continuous patterned layers in an array region of the substrate; and providing disposed at the lower section and the upper section The alignment features at the segments determine the relative positions of the consecutive patterned layers in a surrounding region adjacent to the array region.

In some embodiments, fabricating one of the plurality of alignment features proximate the target feature precedes fabricating another of the plurality of alignment features disposed away from the target feature.

In some embodiments, the first axis, the second axis, the target feature, and the plurality of alignment features are disposed in cutting lines of the substrate.

In some embodiments, the first axis and the second axis have a length of approximately 15 nanometers.

In some embodiments, the target feature is disposed on a first structural layer of the substrate, and the first axis, the second axis and the plurality of alignment features are disposed above or below the first structural layer. on a second structural layer.

In some embodiments, the plurality of alignment features are quartered by a pair of vacant areas, and the first axis or the second axis extends through one of the vacant areas.

In some embodiments, the overlay measurement mark has a reflective symmetry or rotational symmetry.

One embodiment of the present disclosure provides a method of identifying a stack alignment error during a semiconductor manufacturing process. The method includes forming a first structural layer on a wafer, the first structural layer including a target feature; forming a second structural layer on the first structural layer, the second structural layer including a first axis, a second axis and a pair of alignment features, wherein the pair of alignment features are disposed at the first axis and the second axis; and using a position of the first axis relative to the target feature and the second axis relative to A relative displacement of the first structural layer and the second structural layer is determined at a position of the target feature.

In some embodiments, the method further includes recording an image of a substrate, the substrate including the wafer, the first structural layer and the second structural layer; wherein the first structural layer and the second structural layer are determined based on the at least one image. the relative displacement of the second structural layer.

In some embodiments, the first axis is formed to bisect one of the pair of alignment features; the second axis intersecting the first axis is formed to bisect the other of the pair of alignment features; and when the The first structural layer and the second structural layer are correctly aligned when an intersection of an axis and the second axis overlaps the target feature.

In some embodiments, the first axis is formed to bisect one of the pair of alignment features; the second axis intersecting the first axis is formed to bisect the other of the pair of alignment features; and when the When an intersection of an axis and the second axis deviates from the target feature, the first structural layer and the second structural layer are not properly aligned.

In some embodiments, when one of the first axis and the second axis deviates from the target feature, the first structural layer and the second structural layer are not properly aligned.

In some embodiments, a photolithography process is used to form the second structural layer.

In some embodiments, the second structural layer includes photoresist material.

In some embodiments, the first axis, the second axis, the pair of alignment features, and the target feature are located in at least one scribe line on the wafer.

Because of the arrangement of the overlapping measurement marks including the first axis and the second axis that intersect with each other and extend through the centers of the alignment features, the process for calibrating the process to align the alignment features can be efficiently and quickly accomplished. The overlay error remains within desired limits for the overlay measurement.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific language will now be used to describe the embodiments or examples of the present disclosure illustrated in the drawings. It should be understood that the scope of the present disclosure is not intended to be limited thereby. Any modifications or improvements to the described embodiments, as well as any further applications of the principles described in this document, are within the realm of ordinary skill in the art. Element numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment even if they share the same element number.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, These elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a "first element", "component", "region", "layer" or "section" discussed below may be referred to as a second device , component, region, layer or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. exists, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

FIG. 1 is a schematic top view illustrating a substrate 10 according to some embodiments of the present disclosure. Referring to FIG. 1 , the substrate 10 includes a plurality of die regions 110 that are separated from each other by a plurality of first cutting lines 120 and a plurality of second cutting lines 130 . The first cutting lines 120 extend along a first direction D1, and the second cutting lines 130 extend along a second direction D2. In some embodiments, the first direction D1 extends in a horizontal direction, and the second direction D2 extends in a vertical direction, and the second direction D2 is substantially orthogonal to the first direction D1.

In addition, each first cutting line 120 intersects the second cutting lines 130 at right angles. Accordingly, the die regions 110 divided by the first cutting lines 120 and the second cutting lines 130 generally have a linear shape and are arranged in a matrix arrangement on the substrate 10 .

The substrate 10 can be subjected to different processes, including film forming, lithography, ion implantation and cleaning, to form a plurality of integrated circuits in the die areas 110, where the integrated circuits are a functional unit, and the The functional unit eventually becomes a single die or chip. In some embodiments, the various features and structural layers used to form the integrated circuits are fabricated in and on a single wafer 140 using multiple processes, including oxidation, deposition, Doping, diffusion, resist application and stripping, exposure, development, etching, metallization, annealing and chemical mechanical polishing, but are not limited to this. The integrated circuit may include doped regions, insulating features, and different layers not individually described that combine to form different microelectronic components, including a logic component (such as a microcontroller) or a Memory device (such as a dynamic random access memory or a non-volatile memory).

Wafer 140 of substrate 10 may include silicon. Alternatively or in addition, wafer 140 may include other semiconductor materials, such as III-V semiconductor materials. Examples of such layers on wafer 140 include dielectric layers, doped layers, and conductive layers including metallic materials. In some embodiments, the first dicing lines 120 and the second dicing lines 130 may have a width of approximately 30 to 100 microns, depending on the conditions fabricated in and on the wafer 140 . The size of the integrated circuits.

After fabrication, the substrate 10 is separated into individual integrated circuits by a technique such as dicing or sawing. Typically, sawing is performed along the first cutting lines 120 and the second cutting lines 130 to separate the grain regions 110 . For example, the individual integrated circuits may be individually packaged. Alternatively, the individual integrated circuits may be packaged in multiple multi-chip modules. In particular, when performing a dividing operation, the area of the wafer along the first cutting lines 120 and the second cutting lines 130 is wasted.

FIG. 2 is an enlarged schematic diagram illustrating area A in FIG. 1 . Referring to FIG. 2 , the die area 110 may include an array area 112 and a surrounding area 114 , and the surrounding area 114 is adjacent to the array area 112 . For example, when the integrated circuit is a dynamic random access memory, a memory cell array (as shown in FIG. 3 ) is provided in the array area 112, which includes a plurality of memories for storing data. Cell 1124, and a plurality of surrounding circuits requiring external inputs and outputs are located in the surrounding area 114.

Referring to FIG. 3 , in some embodiments, the memory cell 1124 is disposed at an intersection of a word line WL and a bit line BL. The peripheral circuitry for accessing the memory cells 1124 may include an address buffer 1142, a column decoder 1144, a plurality of sense amplifiers 1146, a row decoder 1148, an input/output (I /O) buffer 1150 and a clock generator 1152, but is not limited to this. The address buffer 1142 obtains an externally provided address to select one of the memory cells 1124 in the memory cell array 1122 and generates an internal row address and an internal column address in response to the externally provided address. .

A column decoder 1144 that decodes the internal column address to select a column (word line) specified by the internal column address is electrically coupled to the address buffer 1142 and the word lines WL. The sense amplifiers 1146 electrically coupled to the I/O buffer 1150 and the bit lines BL are configured to detect and amplify the connection of the memory cell 1124 to the word line WL selected by the column decoder 1144 material. A row decoder 1148 electrically coupled to the sense amplifiers 1146 uses the internal column address from the address buffer 1142 to select a corresponding row (bit line) in the memory cell array 112 .

The clock generator 1152 is electrically coupled to the address buffer 1142, the sense amplifiers 1146, the row decoder 1148, and the I/O buffer 1150. The clock generator 1152 may be an electronic oscillator that generates a clock signal for synchronizing the operation of the peripheral circuits of the integrated circuit.

During a read operation, one of the sense amplifiers 1146 amplifies a voltage difference generated in a selected bit line based on the stored data of a selected memory cell 1124 and passes it through the I/O buffer 1150 An amplified result is output to an external component as read data. During a write operation, according to the write data input through the I/O buffer 1150, a voltage difference with a predetermined amplitude is generated on the selected bit line, and thereby the write data is stored in a in the selected memory cell 1124.

Referring again to FIG. 2 , according to some embodiments, each array area 112 is surrounded by one of the surrounding areas 114 . Additionally, each surrounding region 114 optionally includes a sealing ring 116 surrounding an individual array region 112 to prevent cracks from propagating into the individual array region 112 of the substrate 10 during separation of the die regions 110 .

Typically, the integrated circuit is confined within the die region 110 and does not extend to or across the first scribe lines 120 and the second scribe lines 130 of the substrate 10 to be sawed. However, some reliability and functional measurement marks are disposed in the first scribe lines 120 and the second scribe lines 130 to measure and characterize structural changes at the wafer level. In some embodiments, the measurement marks are placed in the first dicing lines 120 and the second dicing lines 130 on the plurality of product wafers 140 to obtain information associated with at least one specific process node. Different physical properties and performance indicators.

For example, overlay measurement marks 200 for correcting an alignment in order to maintain overlay errors within desired limits may be formed on the first cutting lines 120 and the second cutting lines 130 This allows overlay measurement marks 200 to be placed on wafer 140 without taking up space on the integrated circuit. In some embodiments, the overlay measurement mark 200 is suitable for an image-based overlay measurement technology. It is worth noting that when the segmentation operation is performed, the overlapping measurement marks 200 in the first cutting lines 120 and the second cutting lines 130 are destroyed.

The overlay measurement mark 200 may include a first axis 210, a second axis 212, a target feature 214, a first alignment feature 215a, and a second alignment feature 215b. The first axis 210 extends in a first direction D1, and the second axis 212 extends in a second direction D2, and the second direction D2 is orthogonal to the first direction D1. The target feature 214 having a cross shape is disposed at an intersection of the first axis 210 and the second axis 212 . The first alignment feature 215a is provided on the first axis 210 and the second alignment feature 215b is provided on the second axis 212.

Furthermore, the first alignment feature 215a and the second alignment feature 215b are paired to determine an overlay error between two consecutive layers of the substrate 10. As depicted in Figure 4, a shortest distance d between the first axis 210 and the second alignment feature 215b is equal to a shortest distance d between the second axis 212 and the first alignment feature 215a.

It is generally believed that the size of the overlay measurement mark 200 should be as large as possible in order to maximize the amount of information used for the overlay measurement. However, the upper limit of the size of the overlay measurement mark 200 may be determined by a field of view of a measurement tool (not shown) used to measure the number of overlaps and/or cutting lines. The field of view typically refers to an optical perimeter defining the image area available for overlay measurement marks 200 captured by the measurement tool, and the number of cutting lines typically refers to the number of cut lines used to place the overlay measurement Mark 200 the available space allowed by the first cutting lines 120 and the second cutting lines 130 . For example, the first axis 210 and the second axis 212 may have a length L that is not greater than 28 microns. In some embodiments, the length L of the first axis 210 and the second axis 212 is approximately 15 microns.

Figure 5 is a top view schematic diagram illustrating alignment features 216 of some embodiments of the present disclosure. The geometry of the alignment features 216 is configured to find an appropriate balance between an image resolution of the metrology tool and the robustness of the process. Referring to Figure 5, the alignment features 216 have a square outline. However, a size and a shape of the alignment features 216 can vary widely. For example, the alignment features 216 may form shapes such as circles, triangles, rectangles, polygons, and the like.

In some embodiments, each alignment feature 216 is divided into four equal parts by a plurality of vacant areas 2162 having a first width W1. In some embodiments, the alignment features 216 are composed of a plurality of square microstructures 2164 separated by a pair of intersecting void regions 2162 . As depicted in FIG. 5 , the microstructures 2164 have a second width W2 that is larger than the first width W1 . It is worth noting that the lower limit of the characteristic size of each microstructure 2164 is determined by the resolution limit of the measurement tool.

FIG. 6 is a top view schematic diagram illustrating overlay measurement marks 200 for aligning different layers on a wafer 140 according to some embodiments of the present disclosure. Referring to FIG. 6 , the overlay measurement mark 200 may include a first axis 210 , a second axis 212 , a target feature 214 and a plurality of alignment features 216 . The first axis 210 extends in the first direction D1, the second axis 212 extends in the second direction D2, and the first axis 210 and the second axis 212 intersect at a right angle. The target feature 214 is disposed at an intersection of the first axis 210 and the second axis 212 .

In some embodiments, the target feature 214 may be composed of two line segments 2142 and 2144 (as shown in FIG. 7 ) that intersect to form an X shape. Referring again to FIG. 6 , the alignment features 216 are disposed along the first axis 210 and the second axis 212 and at an equal distance between adjacent pairs of alignment features 216 . In other words, a distance between adjacent pairs of alignment features is fixed. Referring to FIGS. 6 and 7 , some alignment features 216 are disposed on either side of the line segment 2142 of the target feature 214 , and other alignment features 216 are disposed on either side of the line segment 2144 of the target feature 214 . In some embodiments, the overlay measurement mark 200 has a cross-shaped outline.

Referring to FIG. 6 , for analysis purposes, the overlay measurement mark 200 can be divided into multiple sections. Any number of bins can be used for this analysis of overlap errors. In some embodiments, the overlay measurement mark 200 is divided into four sections. In some embodiments, the first shaft 210 may separate the second shaft 212 into two equal sections, such as an upper section and a lower section. Similarly, the second axis 212 may divide the first axis 210 into two equal sections, such as a left section and a right section.

The alignment features 216 are grouped into a first alignment group 220 and a second alignment group 230 based on their positions. For example, the first alignment group 220 may include the alignment features 216 disposed at the left section of the first axis 210 and at the upper section of the second axis 212, while the second alignment group 230 may include alignment features 216 disposed at the right section of the first shaft 210 and at the lower section of the second shaft 212 .

In some embodiments, the alignment features 216 of the first alignment group 220 may be provided to determine whether overlay errors exist in the array region 112 (as shown in FIG. 8 ), while the second alignment group 230 may be provided. Equally align features 216 to determine if overlay errors exist in surrounding area 114 . The number of alignment features 216 at each section can vary widely. As shown, the number of alignment features 216 at each section is the same as the number of alignment features 216 in other sections; therefore, the overlay measurement mark 200 may have a reflective symmetry (reflectional symmetry) or a rotational symmetry (rotational symmetry).

Referring again to FIG. 6 , the alignment features 216 in the array area 112 or the surrounding area 114 are paired and used to measure overlay errors of different layers of the substrate 10 . In some embodiments, the alignment feature 216 is disposed at the first axis 210 and separated from the second axis 212 by a predetermined distance, and the alignment feature 216 is disposed at the second axis 212 and separated from the second axis 212 by the predetermined distance. The first axis 210 spaced alignment features 216 are paired for overlapping measurements as shown in FIG. 7 . Briefly, the alignment features 216 are paired apart from the intersection of the first and second axes 210 , 212 by the same shortest distance and in the same alignment group to determine the alignment of the substrate 10 The relative position of two consecutive patterned layers.

As described in FIGS. 5 and 7 , the first axis 210 is set to extend through the horizontal vacant area 2162 of the alignment feature 216 disposed at the first axis 210 , and the second axis 212 is designed to extend through the horizontal gap 2162 disposed at the second axis 212 . Align the longitudinal void area 2162 of the feature 216 to aid in the measurement of overlay error.

Referring to FIG. 6 , the first and second alignment groups 220 and 230 respectively include four pairs of alignment features 222a to 222d and 232a to 232d. Notably, the alignment features 216 represented by different shades of gray may represent multiple alignment features 216 disposed at different layers of the substrate 10 . A first pair of alignment features 222a may be provided closest to one of the target features 214 to determine whether an overlay error exists in an active region of the array (eg, an active region in the array region 112); a second pair of alignment features may be provided 222b to determine whether an overlap error exists in each bit line contact point; a third pair of alignment features 222c may be provided to determine whether an overlap error exists in multiple word lines; and the furthest feature 214 from the target may be provided A fourth pair of alignment features 222d to determine whether overlay errors exist in multiple bit lines.

Additionally, a fifth pair of alignment features 232a may be provided that is closest to one of the target features 214 to determine whether an overlay error exists in an array region of the surrounding area 114; a sixth pair of alignment features 232b may be provided to determine whether an overlay error exists Occurs in at least one gate conductor of surrounding area 114; a seventh pair of alignment features 232c may be provided to determine whether an overlay error exists in at least one contact support point; and an eighth pair furthest from the target feature 214 may be provided. Alignment features 232d are aligned to determine whether an overlay error exists in at least one PFET contact point. It can be observed that the alignment features 216 disposed proximal to the target feature 214 are formed on the wafer 140 before the alignment features 216 disposed distal to the target feature 214 .

FIG. 9 is a schematic flowchart illustrating a method 300 for determining overlay errors during a semiconductor manufacturing process according to some embodiments of the present disclosure. FIG. 10 is a schematic cross-sectional view illustrating an intermediate stage in forming overlay measurement marks according to some embodiments of the present disclosure. Referring to FIGS. 9 and 10 , the method 300 for determining overlay errors during a semiconductor process may begin with step S301 , which is depositing a first layer 150 on a wafer 140 . Wafer 140 may typically be a silicon wafer. Wafer 140 may include different doping compositions, depending on design requirements well known in the art. Wafer 140 may also include other elemental semiconductors, such as germanium. Alternatively, wafer 140 may include compound semiconductors and/or alloy semiconductors.

After the first layer 150 is deposited, a photoresist layer 180 is coated on the entire wafer 140 through a spin coating process and then dried using a soft bake process. Then, the photoresist layer 180 including the photosensitive material is exposed and developed to form a characteristic pattern 182 as shown in FIG. 11 , thereby exposing some portions of the first layer 150 . Next, the method 300 then proceeds to step S302 to perform a patterning process to etch the first layer 150 through the feature pattern 182, thereby forming a first structural layer including a target feature 214 (as shown in FIGS. 12 and 13 ). 151. After the target features 214 are created using, for example, an ashing process or a wet etching process, the feature pattern 182 is removed.

Referring to FIG. 12 , the wafer 140 includes a plurality of die areas 110 , and the die areas 110 are separated by a plurality of first cutting lines 120 and a plurality of second cutting lines 130 . Different components including transistors, diodes, capacitors, resistors, fuses or the like are respectively formed in the die regions 110 . The first structural layer 151 used to form the elements includes a plurality of first patterned structures 152 in an array region 112 and target features 214 in the cutting lines 120, 130. Target features 214 are formed in the first scribe lines 120 and the second scribe lines 130 using the same process used to form the first patterned structures 152 in the array region 112 . In other words, target features 214 are formed as part of the process for fabricating first patterned structures 152 , allowing the process to be tested and verified without contaminating or interfering with the production of patterned structures 152 . In some embodiments, the first structural layer 150 may be formed during a front-end-of-line (FEOL) process.

Please refer to FIG. 9 and FIG. 14, and then the method 300 proceeds to step S303, which is to deposit a second layer 160 on the first structural layer 151. In some embodiments, a third layer 170 is selectively deposited on the first structural layer 151 before the second layer 160 is deposited. The second layer 160 may include photoresist material. Next, some portions of the second layer 160 are exposed to radiation (not shown) and then developed to form a second structural layer 162. As shown in Figures 15 and 16, the second structural layer 162 includes a first Shaft 210, a second shaft 212, and a pair of alignment features 216 located in the first and second cutting lines 120, 130. In other words, the second structural layer 162 is formed using a photolithography process. In some embodiments, the second structural layer 160 may be a pattern that will be used to protect a portion of the third layer 170 during etching.

As depicted in FIG. 15 , the first axis 210 intersects the second axis 212 , and the pair of alignment features 216 are provided at the first axis 210 and the second axis 212 . In detail, the first axis 210 extends along a first direction D1, the second axis 212 extends along a second direction D2, and the second direction D2 is substantially perpendicular to the first direction D1. Furthermore, the first axis 210 and the second axis 212 intersect at a right angle. Again, one of the alignment features 216 is disposed at the first axis 210 and the other alignment feature 216 is disposed at the second axis 212 .

The first axis 210 bisects one of the alignment features 216 disposed thereon, and the second axis 212 bisects the other alignment feature 216 disposed thereon. In other words, the first axis 210 and the second axis 212 serve as multiple reference lines for overlapping measurements.

After forming a stack of measurement marks including the first axis 210 , the second axis 212 , the target feature 214 and the pair of alignment features 216 , a measurement tool (not shown) is provided to record the first axis 210 , the target feature 214 and the pair of alignment features 216 . An image of the two axes 212, the target feature 214 and the alignment features 216 (step S306). It is worth noting that if the first structural layer 151 and the second structural layer 162 use the measurement tool to determine a relative displacement, the second structural layer 162 and the third layer 170 selectively penetrate and allow light to pass through. without significant light scattering.

Then, the method 300 proceeds to step S308 , in which a relative displacement of the first structural layer 151 and the second structural layer 162 may be determined using a position of the alignment feature 216 relative to the target feature 214 . In some embodiments, the overlay measurement is performed immediately after developing the second structural layer 162 including the photoresist material, meaning that the photoresist is developed away in the area exposed to light, so that in the photoresist Leave that overlapping pattern.

In the present disclosure, the first axis 210 and the second axis 212 are oriented relative to the alignment features 216 . Therefore, determining how to accurately align the first structural layer 150 with the second structural layer can be accomplished by comparing a position of the first axis 210 relative to the target feature 214 and comparing a position of the second axis 212 relative to the target feature 214 160. Alternatively, determining how to accurately align the first structural layer 150 and the second structural layer 160 may be accomplished by comparing an intersection of the first and second axes 210 , 212 relative to the target feature 214 .

Referring to FIGS. 15 and 16 , in some embodiments, once the first axis 210 and the second axis 212 extend through the target structure 214 , the first structural layer 151 and the second structural layer 162 are correctly aligned. Alternatively, it is determined that when an intersection of the first axis 210 and the second axis 212 overlaps the target feature 216, the first structural layer 151 and the second structural layer 162 are correctly aligned.

Referring to FIGS. 17 and 18 , since a displacement x exists between the second axis 212 and the target feature 214 , the second structural layer 162 is not correctly aligned with the first structural layer 151 . Referring to FIGS. 19 and 20 , since a displacement y exists between the second axis 212 and the target feature 214 , the second structural layer 162 is not correctly aligned with the first structural layer 151 . In other words, overlay errors exist in the first structural layer 151 and the second structural layer 162 .

Generally speaking, a larger overlay error results in a larger misalignment of one of the first structural layer 151 and the second structural layer 162 . If the overlay error is too large, it may jeopardize the performance of a manufactured integrated circuit; therefore, a substrate 10 with an unacceptable overlay error can be reworked by removing and redepositing a re-exposed and re-developed photoresist ( reworked). Rework is generally undesirable, but it is better than scrapping the wafer 140 entirely.

In summary, due to the configuration of the overlay measurement marks 200 including the first axis 210 and the second axis 212 extending through the centers of the alignment features 216 , the overlay of the correction process is used to maintain the overlay error within a desired range. Measurements can be done efficiently and quickly.

An embodiment of the present disclosure provides an overlay measurement mark. The overlay measurement mark includes a first axis, a second axis, a target feature, a first alignment feature and a second alignment feature. The second axis intersects the first axis. The target feature is set at an intersection of the first axis and the second axis. The first alignment feature is disposed on the first axis, the second alignment feature is disposed on the second axis, and the first alignment feature and the second alignment feature are disposed in pairs.

One embodiment of the present disclosure provides an overlay measurement mark for confirming multiple relative positions of a plurality of consecutive patterned layers of a substrate. The overlay measurement mark includes a first axis, a second axis, a target feature and a plurality of alignment features. The second axis is orthogonal and crosses the first axis. The target feature is set at an intersection of the first axis and the second axis. The plurality of alignment features are disposed along the first axis and the second axis.

One embodiment of the present disclosure provides a method of identifying a stack alignment error during a semiconductor manufacturing process. The method includes forming a first structural layer on a wafer, the first structural layer including a target feature; forming a second structural layer on the first structural layer, the second structural layer including a first axis, a second axis and a pair of alignment features, wherein the pair of alignment features are disposed at the first axis and the second axis; and using a position of the first axis relative to the target feature and the second axis relative to A relative displacement of the first structural layer and the second structural layer is determined at a position of the target feature.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

10: Base 110: Grain area 112:Array area 1124:Memory cell 114: Surrounding area 1142:Address buffer 1144: Column decoder 1146: Sense amplifier 1148: Line decoder 1150: Input/output buffer 1152: Clock generator 120: First cutting line 130: Second cutting line 140:wafer 150:First floor 151: First structural layer 160:Second floor 162:Second structural layer 170:Third floor 180: Photoresist layer 182:Characteristic pattern 200: Overlay measurement mark 210:First axis 212:Second axis 214:Target features 2142:Line segment 2144:Line segment 215a: First alignment feature 215b: Second alignment feature 216: Alignment features 2162: Vacancy area 2164: Square microstructure 220: First alignment group 222a: Alignment features 222b: Alignment features. 222c: Alignment features 222d: Alignment features 230: Second alignment group 232a: Alignment features 232b: Alignment features 232c: Alignment features 232d: Alignment features 300:Method BL: bit line d: shortest distance D1: first direction D2: second direction L: length S301: Step S302: Step S303: Step S304: Step S306: Step S308: Step W1: first width W2: second width WL: word line x: displacement y: displacement

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements. Figure 1 is a schematic top view illustrating a substrate according to some embodiments of the present disclosure. FIG. 2 is an enlarged schematic diagram illustrating area A in FIG. 1 . FIG. 3 is a block diagram illustrating a dynamic random access memory according to some embodiments of the present disclosure. 4 is a top schematic diagram illustrating a first axis, a second axis, a first alignment feature, and a second alignment feature according to some embodiments of the present disclosure. Figure 5 is a schematic top view illustrating alignment features of some embodiments of the present disclosure. 6 is a schematic top view illustrating some embodiments of the present disclosure for aligning overlay measurement marks on different layers on a wafer. FIG. 7 is a schematic top view illustrating overlay measurement marks used to measure overlay errors according to some embodiments of the present disclosure. 8 is a schematic top view illustrating a portion of a substrate including a plurality of die regions and a stack of measurement marks. FIG. 9 is a schematic flowchart illustrating a method for determining overlay errors during a semiconductor manufacturing process according to some embodiments of the present disclosure. FIG. 10 is a schematic cross-sectional view illustrating an intermediate stage in forming overlay measurement marks according to some embodiments of the present disclosure. FIG. 11 is a schematic cross-sectional view illustrating an intermediate stage in forming overlay measurement marks according to some embodiments of the present disclosure. 12 is a schematic top view illustrating an intermediate stage in forming overlay measurement marks according to some embodiments of the present disclosure. FIG. 13 is a schematic cross-sectional view, illustrating a cross-section along line AA′ of FIG. 12 . 14 is a schematic cross-sectional view illustrating an intermediate stage in forming overlay measurement marks according to some embodiments of the present disclosure. 15 is a schematic top view illustrating an intermediate stage in forming overlay measurement marks according to some embodiments of the present disclosure. FIG. 16 is a schematic cross-sectional view, illustrating a cross-section along the cross-section line BB′ of FIG. 15 . 17 is a schematic top view illustrating an intermediate stage in forming overlay measurement marks according to some embodiments of the present disclosure. FIG. 18 is a schematic cross-sectional view, illustrating a cross-section along line CC′ of FIG. 17 . 19 is a schematic top view illustrating an intermediate stage in forming overlay measurement marks according to some embodiments of the present disclosure. FIG. 20 is a schematic cross-sectional view, illustrating a cross-section along the cross-section line DD′ of FIG. 19 .

110: Grain area

112:Array area

114: Surrounding area

116:Sealing ring

120: First cutting line

130: Second cutting line

200: Overlay measurement mark

210:First axis

212:Second axis

214:Target features

215a: First alignment feature

215b: Second alignment feature

D1: first direction

D2: second direction

Claims (20)

An overlay measurement mark, including: a first axis; a second axis intersecting the first axis; A target feature is set at an intersection of the first axis and the second axis; a first alignment feature disposed on the first axis; and a second alignment feature disposed on the second axis; The first alignment feature and the second alignment feature are arranged in pairs. The overlay measurement mark of claim 1, wherein the first axis, the second axis, the target feature, the first alignment feature and the second alignment feature are disposed on at least one cutting line of the substrate middle. The overlay measurement mark of claim 1, wherein a shortest distance between the first axis and the second alignment feature is equal to a shortest distance between the second axis and the first alignment feature. The overlay measurement mark of claim 1, wherein the target feature is disposed on a first structural layer of the substrate, and the first axis, the second axis, the first alignment feature and the second Alignment features are provided on a second structural layer above or below the first layer. The overlay measurement mark of claim 4, wherein the target feature includes a two-line segment, and when the first layer and the second layer are correctly aligned, the first axis and the second axis are respectively aligned with The line segments overlap. The overlay measurement mark of claim 1, wherein the first axis is orthogonal to the second axis. The overlay measurement mark of claim 6, wherein the target feature has a cross shape. The overlay measurement mark of claim 1, wherein the first alignment feature and the second alignment feature are each composed of a plurality of repeated microstructures. The overlay measurement mark of claim 1, wherein the first alignment feature and the second alignment feature respectively have a square outline and are composed of a plurality of square microstructures, and the microstructures are formed through a separated from each other by vacant areas. The overlay measurement mark of claim 9, wherein the vacant areas have a first width, and the microstructures have a second width, and the second width is greater than the first width. The overlay measurement mark of claim 9, wherein the pair of vacancy areas includes a horizontal vacancy area and a longitudinal vacancy area, and the first axis extends through the first alignment feature located at the first axis. the horizontal void area, and the second axis extending through the longitudinal void area of the second alignment feature located at the second axis. An overlay measurement mark, including: a first axis; a second axis orthogonal to and crossing the first axis; A target feature is located at an intersection of the first axis and the second axis; and A plurality of alignment features are disposed along the first axis and the second axis. The overlay measurement mark of claim 12, wherein a distance between adjacent pairs of alignment features is fixed, and the first axis and the second axis have a length of approximately 15 nanometers. The overlay measurement mark of claim 13, wherein the adjacent pairs of alignment features are separated from the intersection of the first axis and the second axis by an equal distance, and the adjacent pairs The alignment features are configured to determine the relative positions of the plurality of consecutive patterned layers. The overlay measurement mark of claim 12, wherein the first axis separates the second axis into an upper section and a lower section; the second axis separates the first axis into a left section and a right section. section; providing the plurality of alignment features disposed at the upper section and the lower section to determine the relative positions of the plurality of consecutive patterned layers in an array region of the substrate; and Alignment features disposed at the lower section and the upper section are provided to determine the relative positions of the plurality of consecutive patterned layers in a surrounding region adjacent to one of the array regions. The overlay measurement mark of claim 12, wherein manufacturing one of the plurality of alignment features close to the target feature is performed before manufacturing another of the plurality of alignment features disposed away from the target feature. manufacturing. The overlay measurement mark of claim 12, wherein the first axis, the second axis, the target feature and the plurality of alignment features are disposed in a plurality of cutting lines of the substrate. The overlay measurement mark of claim 12, wherein the target feature is disposed on a first structural layer of the substrate, and the first axis, the second axis and the plurality of alignment features are disposed at on a second structural layer above or below the first structural layer. The overlay measurement mark of claim 12, wherein the plurality of alignment features are divided into four equal parts through a pair of vacant areas, and the first axis or the second axis extends through one of the vacant areas. The overlay measurement mark as claimed in claim 12, wherein the overlay measurement mark has a reflection symmetry or rotational symmetry.