TW202329264A - Package structure - Google Patents
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Abstract
Description
本揭示內容係關於一種封裝結構,且特別是一種增加可銲接面積的封裝結構。The present disclosure relates to a package structure, and in particular to a package structure with increased solderable area.
現今半導體封裝產業中,四方平面無引腳封裝(Quad Flat No Leads, QFN)因其引腳側邊的可銲接的面積較少,故四方平面無引腳封裝通常與電路板的銲接強度較差。In today's semiconductor packaging industry, Quad Flat No Leads (QFN) packages usually have poor soldering strength with circuit boards due to the small solderable area on the sides of the leads.
為解決前述問題,目前已發展一種四方平面無引腳封裝的引腳相對底面內縮的結構,藉此提升引腳側邊可銲接的面積以強化與電路板的銲接強度。然而,引腳底面設置於電路板的面積變小容易造成設置於電路板上不穩定,導致產生壽命下降的問題。因此,發展一種可維持引腳的底面可銲接面積,同時可增加引腳的側面可銲接面積,並且可使引腳穩定地設置於電路板的封裝結構遂成為業界重要且急欲解決的問題。In order to solve the aforementioned problems, a structure in which the pins of the quadrilateral planar leadless package are retracted relative to the bottom surface has been developed, so as to increase the solderable area of the side of the pins and strengthen the soldering strength with the circuit board. However, the reduced area of the bottom surface of the pins disposed on the circuit board tends to cause instability on the circuit board, resulting in a problem of reduced lifespan. Therefore, developing a packaging structure that can maintain the solderable area of the bottom surface of the pin, increase the solderable area of the side of the pin, and enable the pin to be stably arranged on the circuit board has become an important and urgent problem in the industry.
本揭示內容提供一種封裝結構,透過設置於封裝結構的引腳的本體與延伸部的電鍍面以維持底面的可銲接面積,並提升側面的可銲接面積,藉以提升封裝結構設置於電路板的穩定性與熱循環壽命。This disclosure provides a packaging structure, which maintains the solderable area of the bottom surface and increases the solderable area of the side surface through the plating surface of the body and extension of the lead of the packaging structure, so as to improve the stability of the packaging structure on the circuit board. resistance and thermal cycle life.
依據本揭示內容一實施方式提供一種封裝結構,其包含一導線架、一半導體晶片及一塑膠封裝材料。導線架包含一晶片座與複數引腳。引腳設置於晶片座的四周,且各引腳包含一本體、至少一延伸部及複數電鍍面。延伸部連接本體,且本體與延伸部為一體成型。電鍍面設置於本體與延伸部。半導體晶片設置於導線架的晶片座上。塑膠封裝材料設置於導線架上。各引腳的本體與延伸部突出於塑膠封裝材料的外緣。An embodiment according to the present disclosure provides a packaging structure, which includes a lead frame, a semiconductor chip and a plastic packaging material. The lead frame includes a chip seat and a plurality of pins. The pins are arranged around the chip seat, and each pin includes a body, at least one extension and a plurality of plating surfaces. The extension part is connected to the main body, and the main body and the extension part are integrally formed. The electroplating surface is disposed on the main body and the extension part. The semiconductor chip is arranged on the chip seat of the lead frame. The plastic encapsulation material is arranged on the lead frame. The body and extension of each pin protrude from the outer edge of the plastic packaging material.
依據前段所述實施方式的封裝結構,其中各引腳可更包含至少一無電鍍面,且無電鍍面設置於延伸部。According to the package structure of the above-mentioned embodiment, each pin may further include at least one electroless plating surface, and the electroless plating surface is disposed on the extension portion.
依據前段所述實施方式的封裝結構,其中封裝結構的一長度為L,封裝結構的一寬度為W,各引腳的一最大突出長度為Lmax,其可滿足下列條件:W ≤ L;0.01W ≤ Lmax;以及Lmax ≤ 0.5L。According to the packaging structure of the embodiment described in the preceding paragraph, wherein a length of the packaging structure is L, a width of the packaging structure is W, and a maximum protruding length of each pin is Lmax, which can satisfy the following conditions: W ≤ L; 0.01W ≤ Lmax; and Lmax ≤ 0.5L.
依據前段所述實施方式的封裝結構,其中本體的一寬度為W1,延伸部的一寬度為W2,引腳的一厚度為T,其可滿足下列條件:0.25T ≤ W2 < W1。According to the packaging structure of the above-mentioned embodiment, wherein a width of the body is W1, a width of the extension part is W2, and a thickness of the pin is T, which can satisfy the following condition: 0.25T ≤ W2 < W1.
依據前段所述實施方式的封裝結構,其中電鍍面的數量可為至少八。According to the package structure of the embodiment described in the preceding paragraph, the number of plated surfaces may be at least eight.
依據前段所述實施方式的封裝結構,其中各引腳可更包含一凸出部,凸出部連接本體,本體、延伸部及凸出部為一體成型,且電鍍面設置於凸出部。According to the packaging structure of the above-mentioned embodiment, each pin may further include a protruding part, the protruding part is connected to the main body, the main body, the extension part and the protruding part are integrally formed, and the electroplating surface is disposed on the protruding part.
依據前段所述實施方式的封裝結構,其中本體與延伸部可較凸出部遠離封裝結構的一下表面。According to the package structure of the embodiment described in the preceding paragraph, the main body and the extension part can be farther away from the lower surface of the package structure than the protruding part.
依據前段所述實施方式的封裝結構,其中本體的一延伸長度為L1,延伸部的一延伸長度為L2,各引腳的最大突出長度為Lmax,封裝結構的長度為L,其可滿足下列條件:0 < L2 ≤ 0.5L;以及0 < Lmax = L1+L2。According to the packaging structure of the embodiment described in the previous paragraph, wherein an extension length of the body is L1, an extension length of the extension part is L2, the maximum protruding length of each pin is Lmax, and the length of the packaging structure is L, which can satisfy the following conditions : 0 < L2 ≤ 0.5L; and 0 < Lmax = L1+L2.
依據前段所述實施方式的封裝結構,其中封裝結構的長度為L,凸出部的一延伸長度為L3,其可滿足下列條件:0 < L3 ≤ 0.5L。According to the packaging structure of the embodiment described in the preceding paragraph, wherein the length of the packaging structure is L, and an extension length of the protrusion is L3, which can satisfy the following condition: 0 < L3 ≤ 0.5L.
依據前段所述實施方式的封裝結構,其中本體與延伸部可較凸出部靠近封裝結構的下表面。According to the package structure of the embodiment described in the preceding paragraph, the body and the extension part may be closer to the lower surface of the package structure than the protruding part.
依據前段所述實施方式的封裝結構,其中各引腳可更包含一平面部,平面部連接本體,本體、延伸部及平面部為一體成型,且電鍍面設置於平面部。According to the packaging structure of the above-mentioned embodiment, each pin may further include a plane portion, the plane portion is connected to the body, the body, the extension portion and the plane portion are integrally formed, and the plating surface is disposed on the plane portion.
依據前段所述實施方式的封裝結構,其中本體與延伸部可較平面部遠離封裝結構的下表面。According to the package structure of the embodiment described in the preceding paragraph, the body and the extension part can be farther away from the lower surface of the package structure than the planar part.
依據前段所述實施方式的封裝結構,其中本體的延伸長度為L1,延伸部的延伸長度為L2,各引腳的最大突出長度為Lmax,封裝結構的長度為L,其可滿足下列條件:0 < L2 ≤ 0.5L;以及0 < Lmax = L1+L2。According to the packaging structure of the embodiment described in the preceding paragraph, wherein the extension length of the body is L1, the extension length of the extension part is L2, the maximum protruding length of each pin is Lmax, and the length of the packaging structure is L, which can meet the following conditions: 0 < L2 ≤ 0.5L; and 0 < Lmax = L1+L2.
依據前段所述實施方式的封裝結構,其中本體與延伸部可較平面部靠近封裝結構的下表面。According to the package structure of the embodiment described in the preceding paragraph, the main body and the extension part can be closer to the lower surface of the package structure than the planar part.
依據本揭示內容一實施方式提供一種封裝結構,其包含一導線架、一半導體晶片及一塑膠封裝材料。導線架包含一晶片座與複數引腳。引腳設置於晶片座的四周,且各引腳包含一本體、至少一延伸部及複數電鍍面。延伸部連接本體,且本體與延伸部為一體成型。電鍍面設置於本體與延伸部。半導體晶片設置於導線架的晶片座上。塑膠封裝材料設置於導線架上。各引腳的本體貼齊塑膠封裝材料的外緣,且各引腳的延伸部突出於塑膠封裝材料的外緣。An embodiment according to the present disclosure provides a packaging structure, which includes a lead frame, a semiconductor chip and a plastic packaging material. The lead frame includes a chip seat and a plurality of pins. The pins are arranged around the chip seat, and each pin includes a body, at least one extension and a plurality of plating surfaces. The extension part is connected to the main body, and the main body and the extension part are integrally formed. The electroplating surface is disposed on the main body and the extension part. The semiconductor chip is arranged on the chip seat of the lead frame. The plastic encapsulation material is arranged on the lead frame. The body of each pin is aligned with the outer edge of the plastic packaging material, and the extension part of each pin protrudes from the outer edge of the plastic packaging material.
依據前段所述實施方式的封裝結構,其中各引腳可更包含一平面部,平面部連接本體,本體、延伸部及平面部為一體成型,且電鍍面設置於平面部。According to the packaging structure of the above-mentioned embodiment, each pin may further include a plane portion, the plane portion is connected to the body, the body, the extension portion and the plane portion are integrally formed, and the plating surface is disposed on the plane portion.
依據前段所述實施方式的封裝結構,其中封裝結構的一長度為L,封裝結構的一寬度為W,各引腳的一最大突出長度為Lmax,其可滿足下列條件:W ≤ L;0.01W ≤ Lmax;以及Lmax ≤ 0.5L。According to the packaging structure of the embodiment described in the preceding paragraph, wherein a length of the packaging structure is L, a width of the packaging structure is W, and a maximum protruding length of each pin is Lmax, which can satisfy the following conditions: W ≤ L; 0.01W ≤ Lmax; and Lmax ≤ 0.5L.
請參照第1圖至第4圖,其中第1圖繪示依照本發明第一實施方式中封裝結構100的正面示意圖,第2圖繪示第1圖第一實施方式中封裝結構100的背面示意圖,第3圖繪示第1圖第一實施方式中封裝結構100的部分示意圖,第4圖繪示第1圖第一實施方式中封裝結構100的側面示意圖。由第1圖至第4圖可知,封裝結構100具有一上表面101與一下表面102,且包含一導線架(圖未標示)、一半導體晶片(圖未繪示)及一塑膠封裝材料130,其中導線架用以承載半導體晶片,塑膠封裝材料130設置於導線架上並覆蓋半導體晶片形成封裝結構100。Please refer to FIG. 1 to FIG. 4, wherein FIG. 1 shows a schematic front view of the
導線架包含一晶片座110與複數引腳120,其中半導體晶片設置於導線架的晶片座110上,引腳120設置於晶片座110的四周,且各引腳120包含一本體121、至少一延伸部122、複數電鍍面123、至少一無電鍍面124及一凸出部125。The lead frame includes a
延伸部122連接本體121,凸出部125連接本體121,且本體121、延伸部122及凸出部125為一體成型,其中電鍍面123設置於本體121、延伸部122及凸出部125,無電鍍面124設置於延伸部122,其中各引腳120的本體121、延伸部122及凸出部125突出於塑膠封裝材料130的外緣,且本體121與延伸部122較凸出部125遠離封裝結構100的下表面102。透過突出於塑膠封裝材料130的外緣的引腳120可提升封裝結構100的側面可銲接面積。再者,相較於現有技術中引腳未突出於塑膠封裝材料的外緣的封裝結構而言,封裝結構100可提升20%以上的板級(board level)的熱循環壽命。The
第一實施方式中,各引腳120的延伸部122的數量為二,各引腳120的電鍍面123的數量為九,各引腳120的無電鍍面124的數量為二,且各引腳120為一梯狀引腳。再者,電鍍面123的材質可為錫合金或鎳金合金,其中鎳金合金可為鎳鈀金(NiPdAu)、鎳鈀銀金(NiPdAgAu)或鎳金(NiAu),導線架的材質可為鐵鎳合金或銅合金,且塑膠封裝材料130的材質可為環氧樹脂,但並不以上述的材質為限。In the first embodiment, the number of
進一步來說,可透過蝕刻步驟、模壓步驟、雷射步驟、電鍍步驟及切割步驟得到第一實施方式的封裝結構100,但並不以此為限。詳細來說,蝕刻步驟為於導線架的下表面進行蝕刻,模壓步驟為將塑膠封裝材料130設置於導線架上並覆蓋半導體晶片,雷射步驟則是分別於導線架的上表面與下表面以雷射光束去除一部分塑膠封裝材料130,電鍍步驟為設置電鍍面123於雷射步驟後無覆蓋塑膠封裝材料130的導線架表面,接著再以切割步驟形成封裝結構100,其中雷射步驟可為二道以上,其取決於雷射光束的能量與參數,但並不以上述的製程步驟為限。Furthermore, the
由第2圖可知,封裝結構100的一長度為L,封裝結構100的一寬度為W,各引腳120的一最大突出長度為Lmax,其滿足下列條件:W ≤ L;0.01W ≤ Lmax;以及Lmax ≤ 0.5L。具體而言,塑膠封裝材料130可為正方形或長方形,且最大突出長度取決於電路板的配置,並不以上述的條件為限。再者,各引腳120的最大突出長度可為相同。藉此,封裝結構100四周的引腳120的可銲接面積可具有一致性,使後續封裝結構100銲接於電路板(圖未繪示)時不易產生銲接程度的差異,且可穩固地設置於電路板。It can be seen from FIG. 2 that the length of the
由第2圖至第4圖可知,本體121的一延伸長度為L1,延伸部122的一延伸長度為L2,凸出部125的一延伸長度為L3,本體121的一寬度為W1,延伸部122的一寬度為W2,引腳120的一厚度為T,封裝結構100的長度為L,各引腳120的最大突出長度為Lmax,其滿足下列條件:0 < L2 ≤ 0.5L;0 < L3 ≤ 0.5L;0.25T ≤ W2 < W1;以及0 < Lmax = L1+L2。藉此,可維持引腳120的結構穩定性,不易產生側邊爬錫不良的情況,且可提升可靠性。From Figures 2 to 4, it can be seen that an extension length of the
請參照第5圖至第9圖,其中第5圖繪示第1圖第一實施方式中封裝結構100於銲錫後的正面示意圖,第6圖繪示第1圖第一實施方式中封裝結構100於銲錫後的背面示意圖,第7圖繪示第1圖第一實施方式中封裝結構100於銲錫後的部分側面示意圖,第8圖繪示第1圖第一實施方式中封裝結構100於銲錫後的側面示意圖,第9圖繪示第8圖第一實施方式中封裝結構100於銲錫後的部分側面示意圖。由第5圖至第9圖可知,銲錫部140僅可設置於電鍍面123,其中銲錫部140接觸設置電鍍面123的本體121、延伸部122及凸出部125。藉此,除了維持封裝結構100於底面的可銲錫面積外,並可增加封裝結構100於側面的可銲錫面積,藉以提升封裝結構100與電路板的銲接強度。Please refer to FIG. 5 to FIG. 9, wherein FIG. 5 shows a schematic front view of the
由第7圖可知,於封裝結構100進行銲錫作業後,檢測人員可透過自動光學檢查(AOI, Automated optical inspection)以檢視方向D檢測銲錫狀況。具體而言,檢視方向D為由封裝結構100的上表面101往下表面102的方向,且檢測人員可直接以俯視的角度進行檢測。透過以俯視的角度進行自動光學檢查,可提升檢測的效率。As can be seen from FIG. 7 , after the soldering operation of the
必須說明的是,第5圖至第9圖中的銲錫部140的設置位置僅作為示意,主要用以表達銲錫部140僅設置於電鍍面123,並不會設置於無電鍍面124,但不以第5圖至第9圖中銲錫部140的設置位置為限。It must be noted that the installation positions of the
請參照第10圖至第13圖,其中第10圖繪示依照本發明第二實施方式中封裝結構200的正面示意圖,第11圖繪示第10圖第二實施方式中封裝結構200的背面示意圖,第12圖繪示第10圖第二實施方式中封裝結構200的部分示意圖,第13圖繪示第10圖第二實施方式中封裝結構200的側面示意圖。由第10圖至第13圖可知,封裝結構200具有一上表面201與一下表面202,且包含一導線架(圖未標示)、一半導體晶片(圖未繪示)及一塑膠封裝材料230,其中導線架用以承載半導體晶片,塑膠封裝材料230設置於導線架上並覆蓋半導體晶片形成封裝結構200。Please refer to FIG. 10 to FIG. 13, wherein FIG. 10 shows a schematic front view of the
導線架包含一晶片座210與複數引腳220,其中半導體晶片設置於導線架的晶片座210上,引腳220設置於晶片座210的四周,且各引腳220包含一本體221、至少一延伸部222、複數電鍍面223、至少一無電鍍面224及一平面部226。The lead frame includes a
延伸部222連接本體221,平面部226連接本體221,且本體221、延伸部222及平面部226為一體成型,其中電鍍面223設置於本體221、延伸部222及平面部226,無電鍍面224設置於延伸部222,其中各引腳220的本體221與延伸部222突出於塑膠封裝材料230的外緣,且本體221與延伸部222較平面部226遠離封裝結構200的下表面202。透過突出於塑膠封裝材料230的外緣的引腳220可提升封裝結構200的側面可銲接面積。再者,相較於現有技術中引腳未突出於塑膠封裝材料的外緣的封裝結構而言,封裝結構200可提升20%以上的板級的熱循環壽命。The
第二實施方式中,各引腳220的延伸部222的數量為一,各引腳220的電鍍面223的數量為十,各引腳220的無電鍍面224的數量為一,且各引腳220為一梯狀引腳。In the second embodiment, the number of
進一步來說,可透過蝕刻步驟、模壓步驟、雷射步驟、電鍍步驟及切割步驟得到第二實施方式的封裝結構200,但並不以此為限。詳細來說,蝕刻步驟為於導線架的下表面進行蝕刻,模壓步驟為將塑膠封裝材料230設置於導線架上並覆蓋半導體晶片,雷射步驟則是分別於導線架的上表面與下表面以雷射光束去除一部分塑膠封裝材料230,電鍍步驟為設置電鍍面223於雷射步驟後無覆蓋塑膠封裝材料230的導線架表面,接著再以切割步驟形成封裝結構200,其中雷射步驟可為二道以上,其取決於雷射光束的能量與參數,但並不以上述的製程步驟為限。Furthermore, the
由第11圖可知,封裝結構200的一長度為L,封裝結構200的一寬度為W,各引腳220的一最大突出長度為Lmax,其滿足下列條件:W ≤ L;0.01W ≤ Lmax;以及Lmax ≤ 0.5L。具體而言,塑膠封裝材料230可為正方形或長方形,且最大突出長度取決於電路板的配置,並不以上述的條件為限。再者,各引腳220的最大突出長度可為相同。藉此,封裝結構200四周的引腳220的可銲接面積可具有一致性,使後續封裝結構200銲接於電路板(圖未繪示)時不易產生銲接程度的差異,且可穩固地設置於電路板。It can be seen from FIG. 11 that the length of the
由第11圖至第13圖可知,本體221的一延伸長度為L1,延伸部222的一延伸長度為L2,本體221的一寬度為W1,延伸部222的一寬度為W2,引腳220的一厚度為T,封裝結構200的長度為L,各引腳220的最大突出長度為Lmax,其滿足下列條件:0 < L2 ≤ 0.5L;0.25T ≤ W2 < W1;以及0 < Lmax = L1+L2。藉此,可維持引腳220的結構穩定性,且不易產生側邊爬錫不良的情況。It can be seen from Fig. 11 to Fig. 13 that an extension length of the
再者,引腳220中靠近封裝結構200的下表面202的部分未超出塑膠封裝材料230的邊緣。因此,透過第二實施方式的封裝結構200並不需要更換封裝外型圖(Package Outline Drawing, POD)的樣式,減少重新繪製封裝外型圖的程序。Furthermore, the portion of the
請參照第14圖至第18圖,其中第14圖繪示第10圖第二實施方式中封裝結構200於銲錫後的正面示意圖,第15圖繪示第10圖第二實施方式中封裝結構200於銲錫後的背面示意圖,第16圖繪示第10圖第二實施方式中封裝結構200於銲錫後的部分側面示意圖,第17圖繪示第10圖第二實施方式中封裝結構200於銲錫後的側面示意圖,第18圖繪示第17圖第二實施方式中封裝結構200於銲錫後的部分側面示意圖。由第14圖至第18圖可知,銲錫部240僅可設置於電鍍面223,其中銲錫部240接觸設置電鍍面223的本體221、延伸部222及平面部226。藉此,除了維持封裝結構200於底面的可銲錫面積外,並可增加封裝結構200於側面的可銲錫面積,藉以提升封裝結構200與電路板的銲接強度。Please refer to FIG. 14 to FIG. 18, wherein FIG. 14 shows the front view of the
由第16圖可知,於封裝結構200進行銲錫作業後,檢測人員可透過自動光學檢查以檢視方向D檢測銲錫狀況。具體而言,檢視方向D為由封裝結構200的上表面201往下表面202的方向,且檢測人員可直接以俯視的角度進行檢測。透過以俯視的角度進行自動光學檢查,可提升檢測的效率。It can be seen from FIG. 16 that after the soldering operation of the
另外,第二實施方式與第一實施方式其餘的元件之結構及配置關係皆相同,在此將不另贅述。In addition, the second embodiment is the same as the first embodiment in terms of structure and arrangement of other elements, so it will not be repeated here.
請參照第19圖至第22圖,其中第19圖繪示依照本發明第三實施方式中封裝結構300的正面示意圖,第20圖繪示第19圖第三實施方式中封裝結構300的背面示意圖,第21圖繪示第19圖第三實施方式中封裝結構300的部分示意圖,第22圖繪示第19圖第三實施方式中封裝結構300的側面示意圖。由第19圖至第22圖可知,封裝結構300具有一上表面301與一下表面302,且包含一導線架(圖未標示)、一半導體晶片(圖未繪示)及一塑膠封裝材料330,其中導線架用以承載半導體晶片,塑膠封裝材料330設置於導線架上並覆蓋半導體晶片形成封裝結構300。Please refer to FIG. 19 to FIG. 22, wherein FIG. 19 shows a schematic front view of the
導線架包含一晶片座310與複數引腳320,其中半導體晶片設置於導線架的晶片座310上,引腳320設置於晶片座310的四周,且各引腳320包含一本體321、至少一延伸部322、複數電鍍面323及至少一無電鍍面324。The lead frame includes a
延伸部322連接本體321,且本體321與延伸部322為一體成型,其中電鍍面323設置於本體321與延伸部322,無電鍍面324設置於延伸部322,其中各引腳320的本體321與延伸部322突出於塑膠封裝材料330的外緣。透過突出於塑膠封裝材料330的外緣的引腳320可提升封裝結構300的側面可銲接面積。再者,相較於現有技術中引腳未突出於塑膠封裝材料的外緣的封裝結構而言,封裝結構300可提升20%以上的板級的熱循環壽命。The
第三實施方式中,各引腳320的延伸部322的數量為一,各引腳320的電鍍面323的數量為八,各引腳320的無電鍍面324的數量為一,且各引腳320為一突出引腳。In the third embodiment, the number of
進一步來說,可透過蝕刻步驟、模壓步驟、雷射步驟、電鍍步驟及切割步驟得到第三實施方式的封裝結構300,但並不以此為限。詳細來說,蝕刻步驟為於導線架的下表面進行蝕刻,模壓步驟為將塑膠封裝材料330設置於導線架上並覆蓋半導體晶片,雷射步驟則是於導線架的上表面以雷射光束去除一部分塑膠封裝材料330,電鍍步驟為設置電鍍面323於雷射步驟後無覆蓋塑膠封裝材料330的導線架表面,接著再以切割步驟形成封裝結構300,其中雷射步驟可為二道以上,其取決於雷射光束的能量與參數,但並不以上述的製程步驟為限。Furthermore, the
由第20圖可知,封裝結構300的一長度為L,封裝結構300的一寬度為W,各引腳320的一最大突出長度為Lmax,其滿足下列條件:W ≤ L;0.01W ≤ Lmax;以及Lmax ≤ 0.5L。具體而言,塑膠封裝材料330可為正方形或長方形,且最大突出長度取決於電路板的配置,並不以上述的條件為限。再者,各引腳320的最大突出長度可為相同。藉此,封裝結構300四周的引腳320的可銲接面積可具有一致性,使後續封裝結構300銲接於電路板(圖未繪示)時不易產生銲接程度的差異,且可穩固地設置於電路板。It can be seen from FIG. 20 that the length of the
由第21圖與第22圖可知,本體321的一寬度為W1,延伸部322的一寬度為W2,引腳320的一厚度為T,其滿足下列條件:0.25T ≤ W2 < W1。藉此,可維持引腳320的結構穩定性,且不易產生側邊爬錫不良的情況。It can be seen from FIG. 21 and FIG. 22 that the
請參照第23圖至第27圖,其中第23圖繪示第19圖第三實施方式中封裝結構300於銲錫後的正面示意圖,第24圖繪示第19圖第三實施方式中封裝結構300於銲錫後的背面示意圖,第25圖繪示第19圖第三實施方式中封裝結構300於銲錫後的部分側面示意圖,第26圖繪示第19圖第三實施方式中封裝結構300於銲錫後的側面示意圖,第27圖繪示第26圖第三實施方式中封裝結構300於銲錫後的部分側面示意圖。由第23圖至第27圖可知,銲錫部340僅可設置於電鍍面323,其中銲錫部340接觸設置電鍍面323的本體321與延伸部322。藉此,除了維持封裝結構300於底面的可銲錫面積外,並可增加封裝結構300於側面的可銲錫面積,藉以提升封裝結構300與電路板的銲接強度。Please refer to FIG. 23 to FIG. 27, wherein FIG. 23 shows the front view of the
由第25圖可知,於封裝結構300進行銲錫作業後,檢測人員可透過自動光學檢查以檢視方向D檢測銲錫狀況。具體而言,檢視方向D為由封裝結構300的上表面301往下表面302的方向,且檢測人員可直接以俯視的角度進行檢測。透過以俯視的角度進行自動光學檢查,可提升檢測的效率。It can be seen from FIG. 25 that after the soldering operation is performed on the
另外,第三實施方式與第一實施方式其餘的元件之結構及配置關係皆相同,在此將不另贅述。In addition, the third embodiment is the same as the first embodiment in terms of structure and disposition relationship of other components, which will not be repeated here.
請參照第28圖至第31圖,其中第28圖繪示依照本發明第四實施方式中封裝結構400的正面示意圖,第29圖繪示第28圖第四實施方式中封裝結構400的背面示意圖,第30圖繪示第28圖第四實施方式中封裝結構400的部分示意圖,第31圖繪示第28圖第四實施方式中封裝結構400的側面示意圖。由第28圖至第31圖可知,封裝結構400具有一上表面401與一下表面402,且包含一導線架(圖未標示)、一半導體晶片(圖未繪示)及一塑膠封裝材料430,其中導線架用以承載半導體晶片,塑膠封裝材料430設置於導線架上並覆蓋半導體晶片形成封裝結構400。Please refer to FIG. 28 to FIG. 31, wherein FIG. 28 shows a schematic front view of the
導線架包含一晶片座410與複數引腳420,其中半導體晶片設置於導線架的晶片座410上,引腳420設置於晶片座410的四周,且各引腳420包含一本體421、至少一延伸部422、複數電鍍面423、至少一無電鍍面424及一凸出部425。The lead frame includes a
延伸部422連接本體421,凸出部425連接本體421,且本體421、延伸部422及凸出部425為一體成型,其中電鍍面423設置於本體421、延伸部422及凸出部425,無電鍍面424設置於延伸部422,其中各引腳420的本體421、延伸部422及凸出部425突出於塑膠封裝材料430的外緣,且本體421與延伸部422較凸出部425靠近封裝結構400的下表面402。透過突出於塑膠封裝材料430的外緣的引腳420可提升封裝結構400的側面可銲接面積。再者,相較於現有技術中引腳未突出於塑膠封裝材料的外緣的封裝結構而言,封裝結構400可提升20%以上的板的熱循環壽命。The
第四實施方式中,各引腳420的延伸部422的數量為二,各引腳420的電鍍面423的數量為九,各引腳420的無電鍍面424的數量為二,且各引腳420為一梯狀引腳。In the fourth embodiment, the number of
進一步來說,可透過蝕刻步驟、模壓步驟、雷射步驟、電鍍步驟及切割步驟得到第四實施方式的封裝結構400,但並不以此為限。詳細來說,蝕刻步驟為於導線架的上表面進行蝕刻,模壓步驟為將塑膠封裝材料430設置於導線架上並覆蓋半導體晶片,雷射步驟則是於導線架的上表面以雷射光束去除一部分塑膠封裝材料430,電鍍步驟為設置電鍍面423於雷射步驟後無覆蓋塑膠封裝材料430的導線架表面,接著再以切割步驟形成封裝結構400,其中雷射步驟可為二道以上,其取決於雷射光束的能量與參數,但並不以上述的製程步驟為限。Furthermore, the
由第29圖可知,封裝結構400的一長度為L,封裝結構400的一寬度為W,各引腳420的一最大突出長度為Lmax,其滿足下列條件:W ≤ L;0.01W ≤ Lmax;以及Lmax ≤ 0.5L。具體而言,塑膠封裝材料430可為正方形或長方形,且最大突出長度取決於電路板的配置,並不以上述的條件為限。再者,各引腳420的最大突出長度可為相同。藉此,封裝結構400四周的引腳420的可銲接面積可具有一致性,使後續封裝結構400銲接於電路板(圖未繪示)時不易產生銲接程度的差異,且可穩固地設置於電路板。It can be seen from FIG. 29 that the length of the
由第29圖至第31圖可知,封裝結構400的長度為L,凸出部425的一延伸長度為L3,本體421的一寬度為W1,延伸部422的一寬度為W2,引腳420的一厚度為T,其滿足下列條件:0 < L3 ≤ 0.5L;以及0.25T ≤ W2 < W1。藉此,可維持引腳420的結構穩定性,不易產生側邊爬錫不良的情況,且可提升可靠性。It can be seen from FIG. 29 to FIG. 31 that the length of the
請參照第32圖至第36圖,其中第32圖繪示第28圖第四實施方式中封裝結構400於銲錫後的正面示意圖,第33圖繪示第28圖第四實施方式中封裝結構400於銲錫後的背面示意圖,第34圖繪示第28圖第四實施方式中封裝結構400於銲錫後的部分側面示意圖,第35圖繪示第28圖第四實施方式中封裝結構400於銲錫後的側面示意圖,第36圖繪示第35圖第四實施方式中封裝結構400於銲錫後的部分側面示意圖。由第32圖至第36圖可知,銲錫部440僅可設置於電鍍面423,其中銲錫部440接觸設置電鍍面423的本體421、延伸部422及凸出部425。藉此,除了維持封裝結構400於底面的可銲錫面積外,並可增加封裝結構400於側面的可銲錫面積,藉以提升封裝結構400與電路板的銲接強度。Please refer to FIG. 32 to FIG. 36, wherein FIG. 32 shows the front view of the
由第34圖可知,於封裝結構400進行銲錫作業後,檢測人員可透過自動光學檢查以檢視方向D檢測銲錫狀況。具體而言,檢視方向D為由封裝結構400的上表面401往下表面402的方向,且檢測人員可直接以俯視的角度進行檢測。透過以俯視的角度進行自動光學檢查,可提升檢測的效率。It can be seen from FIG. 34 that after the soldering operation is performed on the
另外,第四實施方式與第一實施方式其餘的元件之結構及配置關係皆相同,在此將不另贅述。In addition, the fourth embodiment is the same as the first embodiment in the structure and configuration relationship of the rest of the components, which will not be repeated here.
請參照第37圖至第40圖,其中第37圖繪示依照本發明第五實施方式中封裝結構500的正面示意圖,第38圖繪示第37圖第五實施方式中封裝結構500的背面示意圖,第39圖繪示第37圖第五實施方式中封裝結構500的部分示意圖,第40圖繪示第37圖第五實施方式中封裝結構500的側面示意圖。由第37圖至第40圖可知,封裝結構500具有一上表面501與一下表面502,且包含一導線架(圖未標示)、一半導體晶片(圖未繪示)及一塑膠封裝材料530,其中導線架用以承載半導體晶片,塑膠封裝材料530設置於導線架上並覆蓋半導體晶片形成封裝結構500。Please refer to FIG. 37 to FIG. 40, wherein FIG. 37 shows a schematic front view of the
導線架包含一晶片座510與複數引腳520,其中半導體晶片設置於導線架的晶片座510上,引腳520設置於晶片座510的四周,且各引腳520包含一本體521、至少一延伸部522、複數電鍍面523、至少一無電鍍面524及一平面部526。The lead frame includes a
延伸部522連接本體521,平面部526連接本體521,且本體521、延伸部522及平面部526為一體成型,其中電鍍面523設置於本體521、延伸部522及平面部526,無電鍍面524設置於延伸部522,其中各引腳520的本體521與延伸部522突出於塑膠封裝材料530的外緣,且本體521與延伸部522較平面部526靠近封裝結構500的下表面502。透過突出於塑膠封裝材料530的外緣的引腳520可提升封裝結構500的側面可銲接面積。再者,相較於現有技術中引腳未突出於塑膠封裝材料的外緣的封裝結構而言,封裝結構500可提升20%以上的板級的熱循環壽命。The
第五實施方式中,各引腳520的延伸部522的數量為一,各引腳520的電鍍面523的數量為九,各引腳520的無電鍍面524的數量為一,且各引腳520為一梯狀引腳。In the fifth embodiment, the number of
進一步來說,可透過蝕刻步驟、模壓步驟、雷射步驟、電鍍步驟及切割步驟得到第五實施方式的封裝結構500,但並不以此為限。詳細來說,蝕刻步驟為於導線架的上表面進行蝕刻,模壓步驟為將塑膠封裝材料530設置於導線架上並覆蓋半導體晶片,雷射步驟則是於導線架的上表面以雷射光束去除一部分塑膠封裝材料530,電鍍步驟為設置電鍍面523於雷射步驟後無覆蓋塑膠封裝材料530的導線架表面,接著再以切割步驟形成封裝結構500,其中雷射步驟可為二道以上,其取決於雷射光束的能量與參數,但並不以上述的製程步驟為限。Furthermore, the
由第38圖可知,封裝結構500的一長度為L,封裝結構500的一寬度為W,各引腳520的一最大突出長度為Lmax,其滿足下列條件:W ≤ L;0.01W ≤ Lmax;以及Lmax ≤ 0.5L。具體而言,塑膠封裝材料530可為正方形或長方形,且最大突出長度取決於電路板的配置,並不以上述的條件為限。再者,各引腳520的最大突出長度可為相同。藉此,封裝結構500四周的引腳520的可銲接面積可具有一致性,使後續封裝結構500銲接於電路板(圖未繪示)時不易產生銲接程度的差異,且可穩固地設置於電路板。It can be seen from FIG. 38 that the length of the
由第39圖與第40圖可知,本體521的一寬度為W1,延伸部522的一寬度為W2,引腳520的一厚度為T,其滿足下列條件:0.25T ≤ W2 < W1。藉此,可維持引腳520的結構穩定性,且不易產生側邊爬錫不良的情況。It can be known from FIG. 39 and FIG. 40 that the width of the
請參照第41圖至第45圖,其中第41圖繪示第37圖第五實施方式中封裝結構500於銲錫後的正面示意圖,第42圖繪示第37圖第五實施方式中封裝結構500於銲錫後的背面示意圖,第43圖繪示第37圖第五實施方式中封裝結構500於銲錫後的部分側面示意圖,第44圖繪示第37圖第五實施方式中封裝結構500於銲錫後的側面示意圖,第45圖繪示第44圖第五實施方式中封裝結構500於銲錫後的部分側面示意圖。由第41圖至第45圖可知,銲錫部540僅可設置於電鍍面523,其中銲錫部540接觸設置電鍍面523的本體521、延伸部522及平面部526。藉此,除了維持封裝結構500於底面的可銲錫面積外,並可增加封裝結構500於側面的可銲錫面積,藉以提升封裝結構500與電路板的銲接強度。Please refer to FIG. 41 to FIG. 45, wherein FIG. 41 shows the front view of the
由第43圖可知,於封裝結構500進行銲錫作業後,檢測人員可透過自動光學檢查以檢視方向D檢測銲錫狀況。具體而言,檢視方向D為由封裝結構500的上表面501往下表面502的方向,且檢測人員可直接以俯視的角度進行檢測。透過以俯視的角度進行自動光學檢查,可提升檢測的效率。It can be seen from FIG. 43 that after the soldering operation is performed on the
另外,第五實施方式與第一實施方式其餘的元件之結構及配置關係皆相同,在此將不另贅述。In addition, the fifth embodiment is the same as the first embodiment in terms of the structure and arrangement of other elements, so it will not be repeated here.
請參照第46圖至第49圖,其中第46圖繪示依照本發明第六實施方式中封裝結構600的正面示意圖,第47圖繪示第46圖第六實施方式中封裝結構600的背面示意圖,第48圖繪示第46圖第六實施方式中封裝結構600的部分示意圖,第49圖繪示第46圖第六實施方式中封裝結構600的側面示意圖。由第46圖至第49圖可知,封裝結構600具有一上表面601與一下表面602,且包含一導線架(圖未標示)、一半導體晶片(圖未繪示)及一塑膠封裝材料630,其中導線架用以承載半導體晶片,塑膠封裝材料630設置於導線架上並覆蓋半導體晶片形成封裝結構600。Please refer to FIG. 46 to FIG. 49, wherein FIG. 46 shows a schematic front view of the
導線架包含一晶片座610與複數引腳620,其中半導體晶片設置於導線架的晶片座610上,引腳620設置於晶片座610的四周,且各引腳620包含一本體621、至少一延伸部622、複數電鍍面623、至少一無電鍍面624及一平面部626。The lead frame includes a
延伸部622連接本體621,平面部626連接本體621,且本體621、延伸部622及平面部626為一體成型,其中電鍍面623設置於本體621、延伸部622及平面部626,無電鍍面624設置於延伸部622,其中各引腳620的本體621貼齊塑膠封裝材料630的外緣,各引腳620的延伸部622突出於塑膠封裝材料630的外緣,且本體621與延伸部622較平面部626遠離封裝結構600的下表面602。透過突出於塑膠封裝材料630的外緣的引腳620可提升封裝結構600的側面可銲接面積。再者,相較於現有技術中引腳未突出於塑膠封裝材料的外緣的封裝結構而言,封裝結構600可提升20%以上的板級的熱循環壽命。必須說明的是,本體621貼齊塑膠封裝材料630的外緣表示本體621未突出於塑膠封裝材料630的外緣。The
第六實施方式中,各引腳620的延伸部622的數量為二,各引腳620的電鍍面623的數量為十,各引腳620的無電鍍面624的數量為二,且各引腳620為一突出引腳。In the sixth embodiment, the number of
進一步來說,可透過蝕刻步驟、模壓步驟、雷射步驟、電鍍步驟及切割步驟得到第六實施方式的封裝結構600,但並不以此為限。詳細來說,蝕刻步驟為於導線架的下表面進行蝕刻,模壓步驟為將塑膠封裝材料630設置於導線架上並覆蓋半導體晶片,雷射步驟則是分別於導線架的上表面與下表面以雷射光束去除一部分塑膠封裝材料630,電鍍步驟為設置電鍍面623於雷射步驟後無覆蓋塑膠封裝材料630的導線架表面,接著再以切割步驟形成封裝結構600,其中雷射步驟可為二道以上,其取決於雷射光束的能量與參數,但並不以上述的製程步驟為限。Furthermore, the
由第47圖可知,封裝結構600的一長度為L,封裝結構600的一寬度為W,各引腳620的一最大突出長度為Lmax,其滿足下列條件:W ≤ L;0.01W ≤ Lmax;以及Lmax ≤ 0.5L。具體而言,塑膠封裝材料630可為正方形或長方形,且最大突出長度取決於電路板的配置,並不以上述的條件為限。再者,各引腳620的最大突出長度可為相同。藉此,封裝結構600四周的引腳620的可銲接面積可具有一致性,使後續封裝結構600銲接於電路板(圖未繪示)時不易產生銲接程度的差異,且可穩固地設置於電路板。It can be seen from FIG. 47 that the length of the
再者,引腳620中靠近封裝結構600的下表面602的部分未超出塑膠封裝材料630的邊緣。因此,透過第六實施方式的封裝結構600並不需要更換封裝外型圖的樣式,減少重新繪製封裝外型圖的程序。Furthermore, the part of the
請參照第50圖至第54圖,其中第50圖繪示第46圖第六實施方式中封裝結構600於銲錫後的正面示意圖,第51圖繪示第46圖第六實施方式中封裝結構600於銲錫後的背面示意圖,第52圖繪示第46圖第六實施方式中封裝結構600於銲錫後的部分側面示意圖,第53圖繪示第46圖第六實施方式中封裝結構600於銲錫後的側面示意圖,第54圖繪示第53圖第六實施方式中封裝結構600於銲錫後的部分側面示意圖。由第50圖至第54圖可知,銲錫部640僅可設置於電鍍面623,其中銲錫部640接觸設置電鍍面623的本體621、延伸部622及平面部626。藉此,除了維持封裝結構600於底面的可銲錫面積外,並可增加封裝結構600於側面的可銲錫面積,藉以提升封裝結構600與電路板的銲接強度。Please refer to FIG. 50 to FIG. 54, wherein FIG. 50 shows the front view of the
由第52圖可知,於封裝結構600進行銲錫作業後,檢測人員可透過自動光學檢查以檢視方向D檢測銲錫狀況。具體而言,檢視方向D為由封裝結構600的上表面601往下表面602的方向,且檢測人員可直接以俯視的角度進行檢測。透過以俯視的角度進行自動光學檢查,可提升檢測的效率。As can be seen from FIG. 52 , after the soldering operation of the
另外,第六實施方式與第一實施方式其餘的元件之結構及配置關係皆相同,在此將不另贅述。In addition, the structure and arrangement relationship of the rest of the components in the sixth embodiment are the same as those in the first embodiment, which will not be repeated here.
綜上所述,本發明的封裝結構可維持底面的銲接面積外,並可同時提升封裝結構的側面可銲接面積,進而提升封裝結構與電路板的銲接強度。並且,銲接後封裝結構可穩定地設置於電路板上,藉以增加板級的熱循環壽命。再者,於銲錫作業後的檢測作業中可提升檢測的效率。To sum up, the packaging structure of the present invention can maintain the soldering area of the bottom surface, and simultaneously increase the solderable area of the side of the packaging structure, thereby improving the soldering strength between the packaging structure and the circuit board. Moreover, the packaging structure can be stably arranged on the circuit board after soldering, so as to increase the thermal cycle life of the board level. Furthermore, the detection efficiency can be improved in the detection operation after the soldering operation.
雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above in terms of implementation, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.
100,200,300,400,500,600:封裝結構
101,201,301,401,501,601:上表面
102,202,302,402,502,602:下表面
110,210,310,410,510,610:晶片座
120,220,320,420,520,620:引腳
121,221,321,421,521,621:本體
122,222,322,422,522,622:延伸部
123,223,323,423,523,623:電鍍面
124,224,324,424,524,624:無電鍍面
125,425:凸出部
130,230,330,430,530,630:塑膠封裝材料
140,240,340,440,540,640:銲錫部
226,526,626:平面部
D:檢視方向
L1,L2,L3:延伸長度
W1,W2,W:寬度
L:長度
Lmax:最大突出長度
T:厚度
100,200,300,400,500,600:
第1圖繪示依照本發明第一實施方式中封裝結構的正面示意圖; 第2圖繪示第1圖第一實施方式中封裝結構的背面示意圖; 第3圖繪示第1圖第一實施方式中封裝結構的部分示意圖; 第4圖繪示第1圖第一實施方式中封裝結構的側面示意圖; 第5圖繪示第1圖第一實施方式中封裝結構於銲錫後的正面示意圖; 第6圖繪示第1圖第一實施方式中封裝結構於銲錫後的背面示意圖; 第7圖繪示第1圖第一實施方式中封裝結構於銲錫後的部分側面示意圖; 第8圖繪示第1圖第一實施方式中封裝結構於銲錫後的側面示意圖; 第9圖繪示第8圖第一實施方式中封裝結構於銲錫後的部分側面示意圖; 第10圖繪示依照本發明第二實施方式中封裝結構的正面示意圖; 第11圖繪示第10圖第二實施方式中封裝結構的背面示意圖; 第12圖繪示第10圖第二實施方式中封裝結構的部分示意圖; 第13圖繪示第10圖第二實施方式中封裝結構的側面示意圖; 第14圖繪示第10圖第二實施方式中封裝結構於銲錫後的正面示意圖; 第15圖繪示第10圖第二實施方式中封裝結構於銲錫後的背面示意圖; 第16圖繪示第10圖第二實施方式中封裝結構於銲錫後的部分側面示意圖; 第17圖繪示第10圖第二實施方式中封裝結構於銲錫後的側面示意圖; 第18圖繪示第17圖第二實施方式中封裝結構於銲錫後的部分側面示意圖; 第19圖繪示依照本發明第三實施方式中封裝結構的正面示意圖; 第20圖繪示第19圖第三實施方式中封裝結構的背面示意圖; 第21圖繪示第19圖第三實施方式中封裝結構的部分示意圖; 第22圖繪示第19圖第三實施方式中封裝結構的側面示意圖; 第23圖繪示第19圖第三實施方式中封裝結構於銲錫後的正面示意圖; 第24圖繪示第19圖第三實施方式中封裝結構於銲錫後的背面示意圖; 第25圖繪示第19圖第三實施方式中封裝結構於銲錫後的部分側面示意圖; 第26圖繪示第19圖第三實施方式中封裝結構於銲錫後的側面示意圖; 第27圖繪示第26圖第三實施方式中封裝結構於銲錫後的部分側面示意圖; 第28圖繪示依照本發明第四實施方式中封裝結構的正面示意圖; 第29圖繪示第28圖第四實施方式中封裝結構的背面示意圖; 第30圖繪示第28圖第四實施方式中封裝結構的部分示意圖; 第31圖繪示第28圖第四實施方式中封裝結構的側面示意圖; 第32圖繪示第28圖第四實施方式中封裝結構於銲錫後的正面示意圖; 第33圖繪示第28圖第四實施方式中封裝結構於銲錫後的背面示意圖; 第34圖繪示第28圖第四實施方式中封裝結構於銲錫後的部分側面示意圖; 第35圖繪示第28圖第四實施方式中封裝結構於銲錫後的側面示意圖; 第36圖繪示第35圖第四實施方式中封裝結構於銲錫後的部分側面示意圖; 第37圖繪示依照本發明第五實施方式中封裝結構的正面示意圖; 第38圖繪示第37圖第五實施方式中封裝結構的背面示意圖; 第39圖繪示第37圖第五實施方式中封裝結構的部分示意圖; 第40圖繪示第37圖第五實施方式中封裝結構的側面示意圖; 第41圖繪示第37圖第五實施方式中封裝結構於銲錫後的正面示意圖; 第42圖繪示第37圖第五實施方式中封裝結構於銲錫後的背面示意圖; 第43圖繪示第37圖第五實施方式中封裝結構於銲錫後的部分側面示意圖; 第44圖繪示第37圖第五實施方式中封裝結構於銲錫後的側面示意圖; 第45圖繪示第44圖第五實施方式中封裝結構於銲錫後的部分側面示意圖; 第46圖繪示依照本發明第六實施方式中封裝結構的正面示意圖; 第47圖繪示第46圖第六實施方式中封裝結構的背面示意圖; 第48圖繪示第46圖第六實施方式中封裝結構的部分示意圖; 第49圖繪示第46圖第六實施方式中封裝結構的側面示意圖; 第50圖繪示第46圖第六實施方式中封裝結構於銲錫後的正面示意圖; 第51圖繪示第46圖第六實施方式中封裝結構於銲錫後的背面示意圖; 第52圖繪示第46圖第六實施方式中封裝結構於銲錫後的部分側面示意圖; 第53圖繪示第46圖第六實施方式中封裝結構於銲錫後的側面示意圖;以及 第54圖繪示第53圖第六實施方式中封裝結構於銲錫後的部分側面示意圖。 FIG. 1 shows a schematic front view of a packaging structure according to a first embodiment of the present invention; FIG. 2 shows a schematic view of the rear of the packaging structure in the first embodiment of FIG. 1; FIG. 3 shows a partial schematic diagram of the package structure in the first embodiment of FIG. 1; FIG. 4 shows a schematic side view of the package structure in the first embodiment of FIG. 1; FIG. 5 shows a schematic front view of the package structure after soldering in the first embodiment of FIG. 1; FIG. 6 shows a schematic view of the back side of the package structure after soldering in the first embodiment of FIG. 1; FIG. 7 shows a partial side view of the package structure after soldering in the first embodiment of FIG. 1; FIG. 8 shows a schematic side view of the package structure after soldering in the first embodiment of FIG. 1; FIG. 9 shows a partial side view of the package structure after soldering in the first embodiment of FIG. 8; FIG. 10 shows a schematic front view of the packaging structure according to the second embodiment of the present invention; FIG. 11 shows a schematic diagram of the rear of the package structure in the second embodiment of FIG. 10; FIG. 12 shows a partial schematic diagram of the package structure in the second embodiment of FIG. 10; FIG. 13 shows a schematic side view of the package structure in the second embodiment of FIG. 10; FIG. 14 shows a schematic front view of the package structure after soldering in the second embodiment of FIG. 10; FIG. 15 shows a schematic view of the back side of the package structure after soldering in the second embodiment of FIG. 10; FIG. 16 shows a partial side view of the package structure after soldering in the second embodiment of FIG. 10; FIG. 17 shows a schematic side view of the package structure after soldering in the second embodiment of FIG. 10; FIG. 18 shows a partial side view of the package structure after soldering in the second embodiment of FIG. 17; FIG. 19 shows a schematic front view of the packaging structure according to the third embodiment of the present invention; FIG. 20 shows a schematic view of the rear of the package structure in the third embodiment shown in FIG. 19; FIG. 21 is a partial schematic diagram of the package structure in the third embodiment shown in FIG. 19; FIG. 22 shows a schematic side view of the package structure in the third embodiment shown in FIG. 19; FIG. 23 shows a schematic front view of the package structure after soldering in the third embodiment shown in FIG. 19; FIG. 24 is a schematic diagram of the rear surface of the package structure after soldering in the third embodiment shown in FIG. 19; FIG. 25 shows a partial side view of the package structure after soldering in the third embodiment of FIG. 19; FIG. 26 shows a schematic side view of the package structure after soldering in the third embodiment of FIG. 19; FIG. 27 shows a partial side view of the package structure after soldering in the third embodiment of FIG. 26; FIG. 28 shows a schematic front view of the packaging structure according to the fourth embodiment of the present invention; FIG. 29 shows a schematic diagram of the rear of the package structure in the fourth embodiment shown in FIG. 28; FIG. 30 is a partial schematic diagram of the package structure in the fourth embodiment shown in FIG. 28; FIG. 31 is a schematic side view of the package structure in the fourth embodiment shown in FIG. 28; FIG. 32 shows a schematic front view of the package structure after soldering in the fourth embodiment shown in FIG. 28; FIG. 33 is a schematic diagram of the rear surface of the package structure after soldering in the fourth embodiment shown in FIG. 28; FIG. 34 shows a partial side view of the package structure after soldering in the fourth embodiment shown in FIG. 28; FIG. 35 shows a schematic side view of the package structure after soldering in the fourth embodiment shown in FIG. 28; FIG. 36 shows a partial side view of the package structure after soldering in the fourth embodiment shown in FIG. 35; FIG. 37 shows a schematic front view of the packaging structure according to the fifth embodiment of the present invention; FIG. 38 shows a schematic view of the rear of the packaging structure in the fifth embodiment shown in FIG. 37; FIG. 39 shows a partial schematic diagram of the package structure in the fifth embodiment shown in FIG. 37; FIG. 40 shows a schematic side view of the package structure in the fifth embodiment shown in FIG. 37; FIG. 41 shows a schematic front view of the package structure after soldering in the fifth embodiment shown in FIG. 37; FIG. 42 is a schematic diagram of the rear surface of the package structure in the fifth embodiment shown in FIG. 37 after soldering; FIG. 43 shows a partial side view of the package structure after soldering in the fifth embodiment of FIG. 37; FIG. 44 shows a schematic side view of the package structure after soldering in the fifth embodiment shown in FIG. 37; FIG. 45 shows a partial side view of the package structure after soldering in the fifth embodiment of FIG. 44; FIG. 46 shows a schematic front view of the packaging structure according to the sixth embodiment of the present invention; FIG. 47 shows a schematic view of the rear of the packaging structure in the sixth embodiment shown in FIG. 46; FIG. 48 shows a partial schematic diagram of the packaging structure in the sixth embodiment of FIG. 46; FIG. 49 shows a schematic side view of the package structure in the sixth embodiment shown in FIG. 46; FIG. 50 shows a schematic front view of the packaging structure after soldering in the sixth embodiment shown in FIG. 46; FIG. 51 is a schematic diagram of the rear surface of the packaging structure after soldering in the sixth embodiment shown in FIG. 46; FIG. 52 shows a partial side view of the packaging structure in the sixth embodiment shown in FIG. 46 after soldering; FIG. 53 shows a schematic side view of the packaging structure in the sixth embodiment of FIG. 46 after soldering; and FIG. 54 is a partial side view of the packaging structure in FIG. 53 in the sixth embodiment after soldering.
100:封裝結構 100: Package structure
121:本體 121: Ontology
122:延伸部 122: Extension
123:電鍍面 123: Plating surface
124:無電鍍面 124: Electroless plating surface
125:凸出部 125: protruding part
130:塑膠封裝材料 130: plastic packaging material
L1,L2:延伸長度 L1, L2: extension length
W1,W2:寬度 W1, W2: width
Claims (17)
Priority Applications (2)
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TW111100156A TWI825546B (en) | 2022-01-03 | 2022-01-03 | Package structure |
US17/723,536 US20220246501A1 (en) | 2020-03-27 | 2022-04-19 | Package structure |
Applications Claiming Priority (1)
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TW111100156A TWI825546B (en) | 2022-01-03 | 2022-01-03 | Package structure |
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TW202329264A true TW202329264A (en) | 2023-07-16 |
TWI825546B TWI825546B (en) | 2023-12-11 |
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US6198171B1 (en) * | 1999-12-30 | 2001-03-06 | Siliconware Precision Industries Co., Ltd. | Thermally enhanced quad flat non-lead package of semiconductor |
TW440972B (en) * | 2000-03-08 | 2001-06-16 | Siliconware Precision Industries Co Ltd | Leadless image sensor package |
US20070130759A1 (en) * | 2005-06-15 | 2007-06-14 | Gem Services, Inc. | Semiconductor device package leadframe formed from multiple metal layers |
US7405106B2 (en) * | 2006-05-23 | 2008-07-29 | International Business Machines Corporation | Quad flat no-lead chip carrier with stand-off |
US9576884B2 (en) * | 2013-03-09 | 2017-02-21 | Adventive Ipbank | Low profile leaded semiconductor package |
US9431313B1 (en) * | 2015-02-19 | 2016-08-30 | Freescale Semiconductor, Inc. | Integrated circuit carrier coating |
TWI719517B (en) * | 2019-06-27 | 2021-02-21 | 立昌先進科技股份有限公司 | Package method for attached single small size and array type of chip semiconductor component |
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