CN100378992C - Semiconductor package and mfg. method thereof - Google Patents
Semiconductor package and mfg. method thereof Download PDFInfo
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- CN100378992C CN100378992C CNB021231915A CN02123191A CN100378992C CN 100378992 C CN100378992 C CN 100378992C CN B021231915 A CNB021231915 A CN B021231915A CN 02123191 A CN02123191 A CN 02123191A CN 100378992 C CN100378992 C CN 100378992C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The present invention relates to a semiconductor packaging member with a tetragonal plane and without a base pin and a manufacturing method thereof. The packaging member is provided with a conducting wire frame, wherein the conducting wire frame is composed of at least a plurality of base pins, a convex segment whose thickness is smaller than that of the base pins is formed on the base pins, and a gold thread welding region which is predefined on the first surface of the convex segment is staggered and partitioned off a welding block welding region for providing the connection of multiple conductive assemblies on a second surface opposite to the convex segment. When the conducting wire frame having a plurality of chips and the conductive assemblies is moved in a clamp for throwing, because the welding block welding region is far away from the gold thread welding region, downward pressure generated by the compression joint of welding wires can completely avoid welding positions of the conductive assemblies in order to prevent the rhegma of the assemblies caused by compression; relatively, the gold thread welding region can be also away from the working environment of the conductive assemblies, and solutions used in work are prevented from staining the preplating surface of the base pins to influence the welding quality of gold threads.
Description
Technical field
The invention relates to a kind of semiconductor package part, particularly about a kind of Sequare shape pin-free planar semiconductor packaging part with soldering projection (Quad Flat Non-Lead Package, QFN).
Background technology
For adapting to the compact developing trend of electronic product, the many directions towards low cost, high-performance and Highgrade integration of semiconductor device develop now, after making every effort to improvement on manufacturing cost, performance and the memory capacity of semiconductor device, the volume of semiconductor device and integral thickness also require exquisite as far as possible, chip size packages (Chip Size Package is arranged then, CSP), (Multi-Chip Module MCM) waits encapsulating products to come out for the encapsulation of silicon wafer level (Wafer Level Package) or multi-chip module.Settle chip yet above-mentioned packaging system is commonly used to go up at multilayer board (Multi-layer Printed Circuit Board), the gold thread that is relied between each circuit board binding often causes the routing difficulty because of circuit is too numerous and jumbled.
In view of this, United States Patent (USP) the 6th, 198 has been invented for No. 171 and a kind ofly have been replaced the Sequare shape pin-free planar semiconductor packaging part of printed circuit board (PCB) as chip bearing member with lead frame.As shown in Figure 1, this Sequare shape pin-free planar formula packaging part 1 is to comprise a lead frame 10, this lead frame 10 has a chip carrier 11 and ring is put many pin ones 2 of these chip carrier 11 peripheries, makes each pin one 2 inner 122 form the protuberance 123 of a thickness less than pin one 2 his ones through half erosion or process for stamping; Semiconductor chip 14, adopt the glutinous brilliant routing of circuit face 140 mode down, form with this pin one 2 protuberances 123 bottom surfaces 121 for this chip 14 and to be electrically conducted relation, and one coats this chip carrier 11, chip 14, gold thread 180 and fills up the packing colloid 19 in this space, pin one 2 protuberances, 123 bottom.
Reduce pin one 2 thickness of protuberance 123, can be these protuberance 123 bottoms and offer a dozen space of lines, therefore when this chip 14 links with circuit face 140 downward modes and this protuberance 123 conductions, chip 14 is very near apart from the gold thread link (not icon) of pin one 2, so can reduce the routing arc length, shorten the signal conducting path, promote the electrical functionality of packaging part then; Simultaneously, bank is placed in pin one 2 bottoms also can make the space of chip 14 tops greatly increase, and then holds function and the processing speed with the multiplication encapsulating products of multicore sheet more.Accompanying drawing 2 shows that promptly as shown in the figure, the characteristics of this structure 1 are to set up larger-size second semiconductor chip 15 above former chip 14 in addition through the multi-chip structure 1 of improvement, and this second chip 15 is to join with partial circuit face 150 and former chip 14.Simultaneously,, and possesses good electrical quality, on these second chip, 15 circuit face 150 and be formed with several metal welding blocks 16 for this chip 15 and these protuberance 123 end faces 120 electrically connects for the complexity that makes circuit reduces.
The making of above-mentioned multi-chip semiconductor device is: have only earlier this second chip 15 properly to be welded to pin one 2 protuberances 123 end faces 120, can implement the bonding wire manufacture process of former chip 14.So, as shown in Figure 3, when pin one 2 routing positions 124 are arrived in wire bonder 18 (Wire Bonder) slippage, planted appropriate many strip metals welding block 16 in fact with respect to pin one 2 end faces 120 of these routing position 124 dorsal parts; Be that a crisp matter alloy material is made because of this welding block 16 again, the downward pressure that this wire bonder 18 is bestowed this routing position 124 when causing gold thread 180 crimping can be taken advantage of a situation and is delivered on the metal welding block 16, and it is cracked even jeopardize the electrical welding quality of this second chip 15 to cause welding block 16 structures.
Summary of the invention
Main purpose of the present invention provides the welding block of tossing about with it in routing zone in a kind of pin bottom surface and plants and connect the position and be mutually to misplace and separate, routing application of force direction must be avoided fully, in case the Sequare shape pin-free planar semiconductor packaging part of welding block pressurized rhegma with this welding block welding position.
A further object of the present invention provides the welding block of tossing about with it in routing zone in a kind of pin bottom surface and plants and connect the position and be mutually to misplace and separate, in order to avoid the stained Sequare shape pin-free planar semiconductor packaging part that influences the gold thread soldering reliability to the routing position of the corrosion solution of using in the welding block operating environment.
In view of above-mentioned and other purpose, the present invention provides a Sequare shape pin-free planar semiconductor packaging part with metal welding block, it comprises: a lead frame, this lead frame is made of some pins at least, and adjacent chips is settled on the regional pin bottom surface and is offered a step structure (Stepped Structure) to form the convex section of a thickness less than his one of pin, wherein, this convex section has a first surface and a relative second surface, and pre-definedly on this second surface go out a gold thread welding region, with this first surface on provide many strip metals welding block to settle welding block plant and connect location dislocation and separate; One first chip is to connect with the downward mode of its action face and this gold thread welding region routing; One second chip is borrowed many strip metals welding block of forming on its action face that this chip is electrically coupled to this welding block and is planted and connect on the position; And a packing colloid in order to coat this first, second chip, gold thread and to make this pin partly expose.
Characteristics of the present invention are to offer the convex section of thickness less than pin on each pin bottom surface, and the gold thread welding region of this convex section second surface is to plant with the welding block of this first surface to connect the position mutual dislocation and separate, therefore this wire bonder direction of exerting pressure can be avoided this welding block fully and plants and connect the position when carrying out the routing operation, the downward pressure that produces during the gold thread crimping can not cause compressing to remote metal welding block, can exempt the anxiety of welding block pressure break.Moreover, this pin routing position connects the position because of planting away from this welding block, be not subject to solution (as scaling powder (Flux), soda acid cleaning fluid etc.) that the welding block operating environment uses pollution, the complete to provide gold thread better welding quality of pin preplating surface effectively is provided.
Description of drawings
Below with best concrete example conjunction with figs. in detail invention characteristics of the present invention and effect:
Accompanying drawing 1 is to be United States Patent (USP) the 6th, 198, the generalized section of No. 171 Sequare shape pin-free planar semiconductor packaging part;
Accompanying drawing 2 be for existing routing and welding block connect about the seated position over against the generalized section of Sequare shape pin-free planar semiconductor packaging part;
Accompanying drawing 3 be for existing gold thread and welding block connect seated position up and down over against the operation of semiconductor package part execution routing the time local enlarged diagram;
Accompanying drawing 4 is the generalized sections for the Sequare shape pin-free planar semiconductor packaging part of first embodiment of the invention;
Accompanying drawing 5A to accompanying drawing 5D be integral manufacturing schematic flow sheet for the Sequare shape pin-free planar semiconductor packaging part of first embodiment of the invention;
Accompanying drawing 6 is the generalized sections for the Sequare shape pin-free planar semiconductor packaging part of second embodiment of the invention; And
Accompanying drawing 7 is the generalized sections for the Sequare shape pin-free planar semiconductor packaging part of third embodiment of the invention.
Symbol description
1,2,3 semiconductor package part 2 ' packaging part semi-finished product
10,20 lead frames, 11,21 chip carriers
12,22,32 pin ones, 20,220 convex section first surfaces
121,221,321 convex section second surfaces, 122,222 internal pin ends
123,223,323 convex sections (portion), 124 pin routing positions
224 gold thread welding regions, 225 welding block corresponding regions
226 welding blocks are planted and are connect 23 convex section spaces, position
14,24 first chips, 140 circuit face
The non-action face of 240 first chip action face, 241 first chips
15,25,35 second chips, 150,250 second chip action face
27 anchor clamps, 270 top boards
271 lower platens 272 prolong platform part
37 heat sinks, 18,28 wire bonders
180,280 gold threads, 19,29 packing colloids
Embodiment
Below being the embodiment of conjunction with figs. 4 to accompanying drawing 5C detailed description Sequare shape pin-free planar semiconductor packaging part of the present invention, for clear understanding making flow process of the present invention, is example with twin-core chip semiconductor packaging part, and the present invention is made an explanation.Yet the method for making of this embodiment also is to be widely used in all pin connecting-types (Lead frame Based) semiconductor package part, and is not increasing under the encapsulating structure whole height, and the ccontaining quantity of chip must be three even more.
Embodiment 1
See also accompanying drawing 4, this figure is the generalized section for the Sequare shape pin-free planar semiconductor packaging part of first embodiment of the invention.As shown in the figure, this semiconductor package part 2 is to include a lead frame 20, this lead frame 20 has one and is positioned at the chip carrier 21 of central authorities and is located on many pin twos 2 of these chip carrier 21 peripheries, and internal pin 22 bottom surfaces 221 of contiguous this chip carrier 21 are provided with step structure (Stepped Structure) to form a convex section 223 less than pin two 2 his thickness; One first chip 24 is to be bonded on this chip carrier 21 in its action face 240 downward modes; One second chip 25 forms electric property couplings with many strip metals welding block 26 of forming on its action face 250 with pin two 2 end faces 220 of this chip 25 and this convex section 223; Many gold threads 280 are linked on these convex section 223 pin twos 2 bottom surfaces 221 for this first chip 24 conductions, and its routing position is to plant with this metal welding block 26 to connect the position and be dislocation mutually and separate; And, a packing colloid 29 in order to coat this first, second chip 24,25 and to make these pin two 2 bottom surfaces 221 parts expose.
Below promptly describe the integral manufacturing flow process of Sequare shape pin-free planar semiconductor packaging part of the present invention in detail to accompanying drawing 5D with accompanying drawing 5A.
Shown in accompanying drawing 5A, be equipped with a lead frame 20 made from copper, copper alloy or metalloid material, this lead frame 20 is made of a chip carrier 21 and many pin twos 2 that are located on these chip carrier 21 peripheries, wherein, this pin two 2 is to be defined as internal pin 22 (label is with pin two 2) near chip carrier 21 parts.Then, utilize existing half erosion (Half-Etching) or punching press (Punch) technology on this internal pin 22, to make at least one step structure (Stepped Structure), to form a convex section 223 from these internal pin end 222 extensions of pin two 2 mediads, making these convex section 223 thickness be significantly less than pin two 2 his thickness provides the routing bank to take in to possess a space 23; And, this convex section 223 must have the first surface 220 and the opposing second surface 221 of sufficient length, cause this first surface 220 to keep sufficient area and can be pre-defined go out the gold thread welding region 224 and the welding block corresponding region 225 of non-overlapping copies, and this welding block corresponding region 225 be with this second surface 221 on welding block plant connect position 226 (shown in welding block imaginary line among the figure) up and down over against, make this welding block plant connecing the gold thread welding region 224 of tossing about with it position 226 to be the dislocation relation mutually.
Afterwards, shown in accompanying drawing 5B, prefabricated one first chip 24 and one second chip 25 make this chip 24,25 respectively have an action face 240,250 (promptly being equipped with the surface of many electronic circuits and electronic building brick) and a non-action face 241,251; Wherein, plant appropriate many strip metals welding block 26 on the action face 250 of this second chip 25 in advance, be electrically conducted so as to providing this chip 25 to form with pin two 2.After treating that this first chip 24 is bonded to this chip carrier 21 down with its action face 240, coating one gluing layer (not icon) on these first chip, 24 non-action face 241, can by this metal welding block 26 this second chip 25 is soldered on this convex section 223 and make this metal welding block 26 be positioned at this welding block corresponding region 225 directly over.
Then, shown in accompanying drawing 5C, with clampings upset in this packaging part semi-finished product 2 ' immigration one anchor clamps (Jig) 27 and impose preheating; These anchor clamps 27 are to comprise a top board 270 and must constitute with the lower platen 271 of these top board 270 clampings simultaneously, and this lower platen 271 is to have one to prolong platform part 272 so that support this convex section 223 in order to avoid pin two 2 shakes corresponding to these pin two 2 convex sections 223 positions.Afterwards, shown in accompanying drawing 5D, many gold threads 280 are carried out the solid welding crimping from these first chip, 24 action face, 240 routings to the gold thread welding region 224 of pin two 2 convex sections 223 with a traditional wire bonder 28 (WireBonder).Because this gold thread welding region 224 and the welding block on pin two 2 first surfaces 220 are planted and connect position 226 distances and very far and mutually be dislocation on pin two 2 bottom surfaces 221, so wire bonder 28 downward pressure of bestowing this gold thread welding region 224 can not influence this welding block and plants and connect position 226 and can exempt metal welding block 26 by the anxiety of pressure break.Moreover, this gold thread welding region 224 and welding block are planted and are connect position 226 distance of being separated by, therefore, the corrosion solution (as scaling powder (Flux), soda acid cleaning fluid etc.) that applies when carrying out the welding block solid welding is difficult for polluting this gold thread welding region 224, can guarantee the welding quality of 224 of gold thread 280 and this gold thread welding regions; The making of this convex section 223 simultaneously is to continue to use existing mode fully need not additionally increase equipment, satisfies the cost of manufacture of also unlikely increase lead frame.
Accompanying drawing 6 and accompanying drawing 7 are another embodiment that show semiconductor package part of the present invention respectively, the structure of this embodiment and aforementioned first embodiment are roughly the same, and it does not only exist together in the non-action face 351 of this second chip 35 is directly to expose (as shown in Figure 6) or addition heat sink 37 (as shown in Figure 7) separately thereon.As shown in the figure, these convex section 323 length increases force the area of dissipation that pin 32 exposes relatively to reduce, utilize chip 35 non-action face 351 to expose or set up the integral heat sink usefulness that heat sink 37 modes can be strengthened packaging part 3, and then effectively safeguard the chip performance of twin-core sheet (even multicore sheet) packaging part.
The above is preferred embodiment of the present invention only, is not in order to limiting essence technology contents of the present invention, and essence technology contents of the present invention is broadly to be defined in claims.Any technology entity or method that other people are finished, if with claims in defined identical or be a kind of change of equivalence, all will treat as and be covered by within this scope of patent protection.
Claims (17)
1. a semiconductor package part is characterized in that, this semiconductor package part is to comprise:
One lead frame, it has some pins, on this bottom surface, form a convex section less than pin thickness, and be pre-defined at least one first welding region that goes out on the first surface of this convex section, separate with second welding region dislocation that forms on the first surface opposing second surface of this convex section;
At least one first semiconductor chip, it has an action face and a non-action face, and borrow many bonding wires to connect this first semiconductor chip to this first welding region in the downward mode of this action face, make and form the electric property coupling relation between this first chip and this pin, above-mentioned convex section is to extend constituting a step structure to described lead frame central authorities from described pin, and the convex section below possesses a bonding wire accommodation space;
At least one second semiconductor chip is bonded on first semiconductor chip, borrows many conductive components that this second chip is electrically conducted to this second welding region; And
One packing colloid is in order to coat first and second semiconductor chips and this conductive component.
2. semiconductor package part as claimed in claim 1 is characterized in that, this semiconductor package part is a Sequare shape pin-free planar semiconductor packaging part.
3. semiconductor package part as claimed in claim 1 is characterized in that, the material of this lead frame is to be selected from a kind of obtained in copper and the copper alloy.
4. semiconductor package part as claimed in claim 1 is characterized in that, this conductive component is to be the metal welding block.
5. semiconductor package part as claimed in claim 1 is characterized in that, is formed with a welding block corresponding region that is right against this second welding region fully on this convex section first surface.
6. semiconductor package part as claimed in claim 5 is characterized in that, this welding block corresponding region and this first welding region non-overlapping copies.
7. semiconductor package part as claimed in claim 1 is characterized in that, this bonding wire connected mode is to borrow a traditional wire bonder that many gold thread contrapositions are welded crimping to this first welding region.
8. semiconductor package part as claimed in claim 7 is characterized in that, this wire bonder can be bestowed this first welding region, one downward pressure.
9. a method for producing semiconductor packaging part is characterized in that, this method for making is to comprise following steps:
Be equipped with a lead frame earlier, it has some pins, on this bottom surface, form a convex section less than his thickness of pin, and be pre-defined at least one first welding region that goes out on the first surface of this convex section, separate with second welding region dislocation that forms on the first surface opposing second surface of this convex section;
Prefabricated at least one first semiconductor chip and second semiconductor chip, this first semiconductor chip is mutually bonding with this second semiconductor chip, treat that this second semiconductor chip is electrically conducted to this second welding region by many conductive components, this lead frame is moved into enforcement bonding wire operation in the anchor clamps, above-mentioned convex section is to extend to constitute a step structure to described lead frame central authorities from described pin, and possess a bonding wire accommodation space on the convex section first surface, make this first semiconductor chip form the electric property coupling relation by bonding wire and this first welding region; And
Coat this first and second semiconductor chip, bonding wire and this conductive component with a packing colloid at last.
10. method for producing semiconductor packaging part as claimed in claim 9 is characterized in that, this semiconductor package part is a Sequare shape pin-free planar semiconductor packaging part.
11. method for producing semiconductor packaging part as claimed in claim 9 is characterized in that, the material of this lead frame is to be selected from a kind of obtained in copper and the copper alloy.
12. method for producing semiconductor packaging part as claimed in claim 9 is characterized in that, this conductive component is to be crisp matter metal welding block.
13. method for producing semiconductor packaging part as claimed in claim 9 is characterized in that, is formed with a welding block corresponding region that is right against this second welding region fully on this convex section first surface.
14. method for producing semiconductor packaging part as claimed in claim 13 is characterized in that, this welding block corresponding region and this first welding region non-overlapping copies.
15. method for producing semiconductor packaging part as claimed in claim 9 is characterized in that, these anchor clamps are to comprise a top board and a relative lower platen, and this lower platen is that a prolongation platform part that provides this convex section to support is provided corresponding to this pin place.
16. method for producing semiconductor packaging part as claimed in claim 9 is characterized in that, this bonding wire operation is to borrow a traditional wire bonder that many gold thread contrapositions are welded crimping to this first welding region.
17. method for producing semiconductor packaging part as claimed in claim 16 is characterized in that, this wire bonder can be bestowed this first welding region, one downward pressure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021231915A CN100378992C (en) | 2002-06-28 | 2002-06-28 | Semiconductor package and mfg. method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021231915A CN100378992C (en) | 2002-06-28 | 2002-06-28 | Semiconductor package and mfg. method thereof |
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| Publication Number | Publication Date |
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| CN1466211A CN1466211A (en) | 2004-01-07 |
| CN100378992C true CN100378992C (en) | 2008-04-02 |
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| CNB021231915A Expired - Lifetime CN100378992C (en) | 2002-06-28 | 2002-06-28 | Semiconductor package and mfg. method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107564875A (en) * | 2016-07-01 | 2018-01-09 | 三菱电机株式会社 | Semiconductor device |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100409436C (en) * | 2005-12-01 | 2008-08-06 | 上海华虹Nec电子有限公司 | Application method of press welding block on top of logic integrated circuit |
| CN102082130B (en) * | 2009-11-30 | 2012-10-17 | 日月光半导体制造股份有限公司 | Semiconductor package piece and manufacturing method thereof |
| CN102376592B (en) * | 2010-08-10 | 2014-05-07 | 矽品精密工业股份有限公司 | Chip size packaging part and production method thereof |
| CN102800642A (en) * | 2011-05-25 | 2012-11-28 | 力成科技股份有限公司 | Multi-chip encapsulation structure with lead frame type contact finger |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0547998A (en) * | 1991-08-21 | 1993-02-26 | Sony Corp | High density mounting semiconductor device |
| US6198171B1 (en) * | 1999-12-30 | 2001-03-06 | Siliconware Precision Industries Co., Ltd. | Thermally enhanced quad flat non-lead package of semiconductor |
| JP2001358285A (en) * | 2000-06-12 | 2001-12-26 | Hitachi Ltd | Resin sealed semiconductor device |
| US20020027275A1 (en) * | 2000-09-07 | 2002-03-07 | Hiroaki Fujimoto | Semiconductor device |
-
2002
- 2002-06-28 CN CNB021231915A patent/CN100378992C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0547998A (en) * | 1991-08-21 | 1993-02-26 | Sony Corp | High density mounting semiconductor device |
| US6198171B1 (en) * | 1999-12-30 | 2001-03-06 | Siliconware Precision Industries Co., Ltd. | Thermally enhanced quad flat non-lead package of semiconductor |
| JP2001358285A (en) * | 2000-06-12 | 2001-12-26 | Hitachi Ltd | Resin sealed semiconductor device |
| US20020027275A1 (en) * | 2000-09-07 | 2002-03-07 | Hiroaki Fujimoto | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107564875A (en) * | 2016-07-01 | 2018-01-09 | 三菱电机株式会社 | Semiconductor device |
| CN107564875B (en) * | 2016-07-01 | 2020-05-22 | 三菱电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1466211A (en) | 2004-01-07 |
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