CN102082130B - Semiconductor package piece and manufacturing method thereof - Google Patents
Semiconductor package piece and manufacturing method thereof Download PDFInfo
- Publication number
- CN102082130B CN102082130B CN200910253103A CN200910253103A CN102082130B CN 102082130 B CN102082130 B CN 102082130B CN 200910253103 A CN200910253103 A CN 200910253103A CN 200910253103 A CN200910253103 A CN 200910253103A CN 102082130 B CN102082130 B CN 102082130B
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- China
- Prior art keywords
- substrate
- semiconductor package
- sealing
- groove
- package part
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
The invention relates to a semiconductor package piece and a manufacturing method thereof. The semiconductor package piece comprises a chip, a sealant, a pattern circuit and a groove, wherein the chip comprises a first substrate and a second substrate which are oppositely arranged, and the second substrate comprises a connecting pad; the sealant covers the chip and is provided with a through hole as well as a first sealant surface and a second sealant surface which are corresponding; the first sealant surface is exposed out of the first substrate; the through hole passes through from the first sealant surface to the second sealant surface; the pattern circuit is connected with the connecting pad and the second sealant surface through the through hole; and the groove passes through the first substrate so as to expose the connecting pad.
Description
Technical field
The invention relates to a kind of semiconductor package part and manufacturing approach thereof, and particularly have the semiconductor package part and the manufacturing approach thereof of perforation relevant for a kind of its chip.
Background technology
Please with reference to Fig. 1 (prior art), it illustrates the sketch map of known semiconductor packaging part.Semiconductor package part 10 comprise one have a groove 26 ceramic substrate 12, a glass substrate 14, a chip 16 and several bonding wires 18.
The inner space of the groove 26 of ceramic substrate 12 need reach greatly, and the space of routing tool heads activity just can be provided, and makes bonding wire 18 successfully connect bonding wire 18 and ceramic substrate 12.
Summary of the invention
The invention relates to a kind of semiconductor package part and manufacturing approach thereof.With the sealing packaged chip, significantly dwindle the volume and the thickness of semiconductor package part.
According to an aspect of the present invention, a kind of semiconductor package part is proposed.Semiconductor package part comprises a chip, a sealing and a pattern circuit and has a groove.Chip comprises one first substrate and one second substrate that is oppositely arranged, and second substrate comprises a connection pad.The sealant covers chip also has a conducting perforation and corresponding one first sealing surface and one second sealing surface.First substrate is exposed on the first sealing surface, and the conducting perforation is through to second sealing surface from the first sealing surface.The pattern circuit connects connection pad and second sealing surface through the conducting perforation.Groove runs through first substrate to expose connection pad.
A kind of manufacturing approach of semiconductor package part is proposed according to a further aspect in the invention.Manufacturing approach may further comprise the steps.Several chips are provided, and chip comprises one first substrate and one second substrate that is oppositely arranged, and second substrate comprises a connection pad; Several chips are set on a support plate, make first substrate of chip be connected in support plate; With a sealant covers chip, wherein sealing has corresponding one first sealing surface and one second sealing surface; Remove support plate, make the first sealing surface expose first substrate of exposed chip; Form a groove, groove runs through first substrate to expose connection pad; Form a conducting perforation in sealing, the conducting perforation is through to second sealing surface from the first sealing surface; Form a pattern circuit, the pattern circuit connects connection pad and second sealing surface through the conducting perforation; And along between the two of those chips, the cutting sealing is to form several semiconductor package parts.
For letting the foregoing of the present invention can be more obviously understandable, hereinafter is special lifts preferred embodiment, and conjunction with figs., elaborates as follows:
Description of drawings
Fig. 1 (prior art) illustrates the sketch map of known semiconductor packaging part.
Fig. 2 illustrates the sketch map according to the semiconductor package part of first embodiment of the invention.
Fig. 3 illustrates the first substrate sketch map of watching toward direction V1 among Fig. 2.
Fig. 4 illustrates the manufacturing approach flow chart according to the semiconductor package part of first embodiment of the invention.
Fig. 5 A to 5I illustrates the manufacturing sketch map of the semiconductor package part of Fig. 2.
Fig. 6 illustrates the first substrate sketch map according to the semiconductor package part of second embodiment of the invention.
Fig. 7 illustrates the first substrate sketch map according to the semiconductor package part of third embodiment of the invention.
Fig. 8 illustrates the first substrate sketch map according to the semiconductor package part of fourth embodiment of the invention.
The primary clustering symbol description:
10,100: semiconductor package part
12: ceramic substrate
14: glass substrate
16,102: chip
18: bonding wire
26,126,226,326,426: groove
104: sealing
106: the pattern circuit
108,208,308,408: the first substrates
110: the second substrates
112: connection pad
114: support plate
Sealing in 118: the first surface
Sealing in 120: the second surface
122: the conducting perforation
124: colloid
128: substrate surface
130,230,330,430: the lateral border face
132,332: opening
134: active surface
136: strutting piece
140: paste film
142: madial wall
S402-S418: step
V1: direction
Embodiment
Below propose preferred embodiment as explanation of the present invention, yet the content that embodiment proposed is merely the usefulness that illustrates, and the accompanying drawing of drawing not is the usefulness as limit protection range of the present invention for cooperating explanation.Moreover the icon of embodiment also omits unnecessary assembly, in order to clear demonstration technical characterstic of the present invention.
First embodiment
Please with reference to Fig. 2, it illustrates the sketch map according to the semiconductor package part of first embodiment of the invention.Semiconductor package part 100 comprises a chip 102, a sealing 104, a pattern circuit 106 and colloid 124 and has a groove 126.
Colloid 124 be formed in the groove 126 and cover connection pad 112 and groove 126 in pattern circuit 106, avoid receiving the infringement of environment and avoid foreign body intrusion with protection connection pad 112.Preferable but non-exclusively, colloid 124 can fill up whole groove 126.
Sealing 104 coating chips 102 also have conducting perforation 122 and 118 and 1 second sealing surface, corresponding one first sealing surface 120.Conducting perforation 122 is through to second sealing surface 120 from first sealing surface 118.The substrate surface 128 of first substrate 108 is exposed on first sealing surface 118.The semiconductor package part 100 of present embodiment uses sealing 104 to come packaged chip 102, so the volume of semiconductor package part 100 and thickness are less.
In another embodiment, if semiconductor package part 100 is the semiconductor package part of an optical type, then first substrate 108 can be a transparency carrier, for example is glass substrate, makes light penetrate into the active surface 134 on second substrate 110 from first substrate 108.
Preferable but non-exclusively, colloid 124 and sealing 104 can have the suction optical activity, for example the color of colloid 124 and sealing 104 is that black or its material have extinction characteristic.So, penetrating into the light of first substrate 108 can be in the chip inscattering.Certainly, the common knowledge the knowledgeable in present technique field should understand, and the semiconductor package part 100 of present embodiment can be the semiconductor package part of other function, is not limited to the semiconductor package part of optical type.
Please with reference to Fig. 3, it illustrates the first substrate sketch map of watching toward direction V1 among Fig. 2.Be the structure of clear expression first substrate 108, Fig. 3 only shows first substrate 108 and connection pad 112.Single groove 126 exposes connection pad 112 and exposes an opening 132 from the lateral border face 130 of first substrate 108, and promptly groove 126 is connected in lateral border face 130.
To be example below, the manufacturing approach of the semiconductor package part of first embodiment of the invention will be described with semiconductor package part 100.Please with reference to Fig. 4, it illustrates the manufacturing approach flow chart according to the semiconductor package part of first embodiment of the invention.Please be simultaneously with reference to Fig. 5 A to 5I, it illustrates the manufacturing sketch map of the semiconductor package part of Fig. 2.
In step S402, shown in Fig. 5 A, several chips 102 are provided.Be clear expression, Fig. 5 A only shows single chip 102.Each chip 102 comprises first substrate 108 and second substrate 110 that is oppositely arranged.Second substrate 110 comprises connection pad 112.
Then, in step S404, shown in Fig. 5 B, chip 102 is set on a support plate 114.First substrate 108 of chip 102 is connected in pasting on the film 140 of support plate 114.
Then, in step S406, shown in Fig. 5 C, with sealing 104 coating chips 102.Because chip 102 is accomplished encapsulation with sealing 104, and the volume of semiconductor package part 100 and thickness are dwindled, and meets compact trend.Wherein.Sealing 104 has 118 and second sealing surface, corresponding first sealing surface 120.
Then, in step S408, shown in Fig. 5 D, remove support plate 114 and paste film 140, with the substrate surface 128 that exposes first substrate 108.The mode that removes support plate 114 for example is to adopt the mode of heating.
In another implements aspect, the some of first substrate 108 is absorbed in pastes in the film 140.In step S408, after removing support plate 114 and pasting film 140, this of first substrate 108 partly protrudes in first sealing surface 118 then.
Then, after step S408, can be inverted (reverse) sealing 104 and chip 102, make substrate surface 128 up to the state shown in Fig. 5 E.
Then, in step S410, shown in Fig. 5 F,, form a groove 126 for example with etching mode.Groove 126 runs through the sealing between first substrate 108 and first substrate 108 and second substrate 110, to expose connection pad 112.
Implement in the aspect at another, the some of groove 126 also can be formed at sealing 104.That is, in the process that forms groove 126, can run through first substrate 108 and remove sealing 104 partly simultaneously, to form groove 126.
Implement in the aspect at other, if do not have sealing between first substrate 108 and second substrate 110, then the groove 126 among this step S410 only need run through first substrate 108 and just can expose connection pad 112.For instance, this other implement the strutting piece of aspect profile be ring-type, its with first substrate 108 and second substrate 110 between formation one confined space, connection pad 112 is positioned at this confined space.Therefore, the sealing 104 among the step S406 receives stopping of strutting piece and can't get into this confined space, makes groove 126 among the step S410 only need run through first substrate 108 and just can expose connection pad 112.
Then, in step S412, shown in Fig. 5 G, form several conducting perforations 122 in sealing 104.Conducting perforation 122 is through to second sealing surface 120 from first sealing surface 118.
Then, in step S414, shown in Fig. 5 H, form pattern circuit 106.Pattern circuit 106 connects connection pad 112 and second sealing surface 120.Promptly; Pattern circuit 106 can extend through madial wall 142, first sealing surface 118, conducting perforation 122 to the second sealings surface 120 of groove 126 from connection pad 112; Making an external circuit (not illustrating), for example is that circuit board can electrically connect through pattern circuit 106 and chip 102.
Then, in step S416, shown in 5I figure, can form colloid 124, to cover the pattern circuit 106 in connection pad 112 and the groove 126 in groove 126.
Then, in step S418, along between the two of those chips 102, cutting sealing 104 is to form several semiconductor package parts as shown in Figure 2 100.
Second embodiment
Please with reference to Fig. 6, it illustrates the first substrate sketch map according to the semiconductor package part of second embodiment of the invention.Continue to use same numeral with the first embodiment something in common among second embodiment, repeat no more at this.Second embodiment and the first embodiment difference are that the lateral border face 230 of the groove 226 of the semiconductor package part of second embodiment and first substrate 208 is isolated from each other.
In the step S410 of Fig. 4, groove 226 exposes connection pad 112 after running through first substrate 208.The groove 226 of present embodiment is not connected with the lateral border face 230 of first substrate 208.
The manufacturing approach of the semiconductor package part of second embodiment repeats no more at this similar in appearance to the manufacturing approach of the semiconductor package part 100 of first embodiment.
The 3rd embodiment
Please with reference to Fig. 7, it illustrates the first substrate sketch map according to the semiconductor package part of third embodiment of the invention.Continue to use same numeral with the first embodiment something in common among the 3rd embodiment, repeat no more at this.The 3rd embodiment and the first embodiment difference are that first substrate 308 of the semiconductor package part of the 3rd embodiment has several grooves 326.
In the step S410 of Fig. 4, after forming several grooves 326 and running through first substrate 308, those grooves 326 expose those connection pads 112 accordingly.Those grooves 326 expose several openings 332 in the lateral border face 330 of this first substrate 308.
The manufacturing approach of the semiconductor package part of second embodiment repeats no more at this similar in appearance to the manufacturing approach of the semiconductor package part 100 of first embodiment.
The 4th embodiment
Please with reference to Fig. 8, it illustrates the first substrate sketch map according to the semiconductor package part of fourth embodiment of the invention.Continue to use same numeral with the 3rd embodiment something in common among the 4th embodiment, repeat no more at this.The 4th embodiment and the 3rd embodiment difference are that several grooves 426 of the semiconductor package part of the 4th embodiment and the lateral border face 430 of first substrate 408 are isolated from each other.
As shown in Figure 8, several grooves 426 are not connected with the lateral border face 430 of first substrate 408.
The manufacturing approach of the semiconductor package part of the 4th embodiment repeats no more at this similar in appearance to the manufacturing approach of the semiconductor package part 100 of first embodiment.
Semiconductor package part that the above embodiment of the present invention disclosed and manufacturing approach thereof.Come packaged chip through sealing, significantly dwindle the volume and the thickness of semiconductor package part.
In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (11)
1. semiconductor package part comprises:
One chip comprises one first substrate and one second substrate that are oppositely arranged, and this second substrate comprises at least one connection pad;
One sealing coats this chip and has a conducting perforation and corresponding one first sealing surface and one second sealing surface, and this first substrate is exposed on this first sealing surface, and this conducting perforation is through to this second sealing surface from this first sealing surface;
One pattern circuit connects this at least one connection pad and this second sealing surface through this conducting perforation; And
Colloid;
Wherein, this semiconductor package part has a groove, and this groove runs through this first substrate, and to expose this at least one connection pad, this colloid is formed in this groove.
2. semiconductor package part as claimed in claim 1, wherein this groove is showed out an opening from the lateral border of this first substrate.
3. semiconductor package part as claimed in claim 1, wherein the lateral border face of this groove and this first substrate is isolated from each other.
4. semiconductor package part as claimed in claim 1, wherein this second substrate comprises several connection pads, and this first substrate has several grooves, and those grooves expose those connection pads.
5. semiconductor package part as claimed in claim 1, wherein at least one material is suction optical activity material in this colloid and this sealing.
6. semiconductor package part as claimed in claim 1, wherein this first substrate is a transparency carrier.
7. semiconductor package part as claimed in claim 1, wherein this chip more comprises:
One strutting piece connects this first substrate and this second substrate.
8. the manufacturing approach of a semiconductor package part comprises:
Several chips are provided, and each those chip comprises one first substrate and one second substrate that is oppositely arranged, and this second substrate comprises at least one connection pad;
Those chips are set on a support plate, make this first substrate of each those chip be connected in this support plate;
With a sealing, coat those chips, this sealing has corresponding one first sealing surface and one second sealing surface;
Remove this support plate, make this first sealing surface expose this first substrate of each those chip;
Form a groove, this groove runs through this first substrate, to expose this at least one connection pad;
Form a conducting perforation in this sealing, this conducting perforation is through to this second sealing surface from this first sealing surface;
Form a pattern circuit, this pattern circuit connects this at least one connection pad and this second sealing surface through this conducting perforation;
Form colloid in this groove; And
Along between the two of those chips, cut this sealing, to form several semiconductor package parts.
9. manufacturing approach as claimed in claim 8, wherein after this step with these those chips of sealant covers, this manufacturing approach more comprises:
Be inverted this sealing and those chips.
10. manufacturing approach as claimed in claim 8, wherein this groove is showed out an opening from the lateral border of this first substrate.
11. manufacturing approach as claimed in claim 8, wherein this second substrate comprises several connection pads, in this step that forms this groove, more comprises:
Form several grooves, those grooves run through this first substrate and expose those connection pads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910253103A CN102082130B (en) | 2009-11-30 | 2009-11-30 | Semiconductor package piece and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910253103A CN102082130B (en) | 2009-11-30 | 2009-11-30 | Semiconductor package piece and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102082130A CN102082130A (en) | 2011-06-01 |
| CN102082130B true CN102082130B (en) | 2012-10-17 |
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| CN200910253103A Active CN102082130B (en) | 2009-11-30 | 2009-11-30 | Semiconductor package piece and manufacturing method thereof |
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| CN113130468A (en) * | 2021-04-15 | 2021-07-16 | 上海安略永信信息技术有限公司 | Flip chip semiconductor package and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1466211A (en) * | 2002-06-28 | 2004-01-07 | ��Ʒ���ܹ�ҵ�ɷ�����˾ | Semiconductor package and mfg. method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1466211A (en) * | 2002-06-28 | 2004-01-07 | ��Ʒ���ܹ�ҵ�ɷ�����˾ | Semiconductor package and mfg. method thereof |
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| CN102082130A (en) | 2011-06-01 |
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