TW202312230A - Composite substrate and manufacture method - Google Patents

Abstract

A composite substrate is provided in some embodiments of the present disclosure, including a graphene layer, a silicon carbide layer, a first silicon substrate, an insulation layer and a second silicon substrate. The silicon carbide layer is disposed on the graphene layer. The first silicon substrate is disposed on the silicon carbide layer. The insulation layer is disposed on the first silicon substrate. The second silicon substrate is disposed on the insulation layer. A method of manufacturing a composite substrate is further provided in some embodiments of the present disclosure.

Description

Composite substrate and manufacturing method thereof

The present disclosure relates to composite substrates and methods of making the same.

Recently, there has been an increasing demand for downsizing GaN microwave power components and increasing output power. However, as the density of power components (such as high-frequency components containing gallium nitride epitaxial structures) increases, the heat accumulation of the components increases rapidly, reducing the performance of the components, making the reliability and stability of the components severely challenged, and limiting Improve the power of the power components.

Therefore, how to improve the heat dissipation effect of the composite substrate carrying power components is a problem to be solved.

The purpose of one embodiment of the present disclosure is to provide a composite substrate, comprising: a graphene layer; a silicon carbide layer disposed on the graphene layer; a first silicon substrate disposed on the silicon carbide layer; an insulating layer disposed on the on the first silicon substrate; and the second silicon substrate is arranged on the insulating layer.

In some embodiments, the graphene layer is a multilayer graphene structure.

In some embodiments, the composite substrate further includes a silicon nitride layer disposed between the graphene layer and the silicon carbide layer.

In some embodiments, the composite substrate further includes an epitaxial multilayer disposed on the second silicon substrate, including gallium nitride.

An object of an embodiment of the present disclosure is to provide a method for manufacturing a composite substrate, including: forming a silicon carbide layer on the first surface of the first silicon substrate; forming a graphene layer on the silicon carbide layer; forming an insulating layer on the under the second surface of the first silicon substrate opposite to the first surface; and bonding the insulating layer and the second silicon substrate to obtain a composite substrate.

In some embodiments, after the step of forming the graphene layer on the silicon carbide layer, a step of thinning the first silicon substrate is further included.

In some embodiments, the step of forming a silicon carbide layer on the first surface of the first silicon substrate includes the steps of: performing a chemical vapor deposition process to form a silicon carbide layer; and the step of forming a graphene layer on the silicon carbide layer includes Step: heating the silicon carbide layer to sublimate a plurality of silicon atoms on the surface of the silicon carbide layer to form a graphene layer.

In some embodiments, the step of forming the silicon carbide layer on the first surface of the first silicon substrate includes the steps of: performing a carburizing furnace process to form the silicon carbide layer; and the step of forming the graphene layer on the silicon carbide layer includes Step: using nitrogen-containing gas to perform plasma-assisted selective reaction on the silicon carbide layer, respectively forming a silicon nitride layer on the silicon carbide layer and a graphene layer on the silicon nitride layer.

In some embodiments, the step of performing a plasma-assisted selective reaction on the silicon carbide layer includes the step of: performing a plasma implantation reaction on the silicon carbide layer using nitrogen gas to break a plurality of carbon-silicon bonds in the silicon carbide layer; and performing an annealing process on the silicon carbide layer in a gas environment containing nitrogen and hydrogen to form a silicon nitride layer on the silicon carbide layer and a graphene layer on the silicon nitride layer.

In some embodiments, before the step of bonding the insulating layer to the second silicon substrate, the steps include: forming an epitaxial multilayer comprising gallium nitride on the first surface of the second silicon substrate; and bonding the insulating layer to the second silicon substrate. The step of the second silicon substrate includes the steps of: adhering the insulating layer and the second surface of the second silicon substrate opposite to the first surface to each other; and heating the insulating layer and the second silicon substrate to bond the insulating layer and the second silicon substrate .

It can be understood that different implementations or examples provided in the following content can implement different features of the subject matter of the present disclosure. The examples of specific components and arrangements are used to simplify the present disclosure and not to limit the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, the description below that a first feature is formed on a second feature includes that the two are in direct contact, or that there are other additional features between the two instead of direct contact. In addition, the present disclosure may repeat reference numerals and/or symbols in several embodiments. Such repetition is for simplicity and clarity and does not imply a relationship between the various embodiments and/or configurations discussed.

The terms used in this specification generally have their ordinary meanings in the art and the context in which they are used. The examples used in this specification, including examples of any term discussed herein, are illustrative only and do not limit the scope and meaning of the disclosure or any exemplified term. Likewise, the disclosure is not limited to some of the embodiments provided in this specification.

In addition, relative terms in space, such as "below" and "upper", are used to conveniently describe the relative relationship between one element or feature and other elements or features in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise positioned (eg, rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.

In this article, "a" and "the" can generally refer to one or more, unless the article is specifically limited in the context. It will be further understood that the terms "comprising", "comprising", "having" and similar words used herein indicate the features, regions, integers, steps, operations, elements and/or components described therein, but do not exclude Other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that, although the terms first, second etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present embodiments.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, "about" generally means within about 20 percent, preferably within about 10 percent, and more preferably within about 5 percent of the error or range of the value of the index . If there is no explicit statement in the text, the values mentioned are regarded as approximate values, that is, the error or range indicated by "approximately".

Several implementations are listed below to describe the touch device of the present invention in more detail, but they are only for illustrative purposes and are not intended to limit the present invention. The scope of protection of the present invention shall prevail as defined by the scope of the appended patent application .

1A to 1G illustrate schematic diagrams of various process stages of manufacturing a composite substrate 100 in some embodiments of the present disclosure.

First, please refer to FIG. 1A , a first silicon substrate 110 is provided.

In some embodiments, the first silicon substrate 110 includes a silicon substrate, a silicon-on-insulator (SOI) substrate, a silicon carbide substrate, or a combination of two or more of the foregoing. In some embodiments, the thickness of the first silicon substrate 110 ranges from 500 microns to 1500 microns, such as 500 microns, 600 microns, 700 microns, 800 microns, 900 microns, 1000 microns, 1100 microns, 1200 microns, 1300 microns, 1400 microns Microns, 1500 microns, or a value in any of the aforementioned intervals. In some embodiments, the lattice orientation of the first silicon substrate 110 includes <100>, <111> or a combination of both, and the crystal with better lattice matching can be selected depending on the type of epitaxial layer to be grown subsequently. grid orientation. In some embodiments, the resistivity of the first silicon substrate 110 may range from 1×10 ⁻⁵ to 1×10 ⁶ ohm centimeters (Ωcm).

Next, please refer to FIG. 1B , performing chemical vapor deposition (Chemical Vapor Deposition; CVD) to form a silicon carbide layer 120 on the first surface 110A of the first silicon substrate 110 .

In some embodiments, when containing propane (C ₃ H _{8 ­­} ), monosilane (SiH ₄ ) and hydrogen (H ₂ ) gas environment, perform chemical vapor deposition to form a silicon carbide layer 120 on the first surface 110A of the first silicon substrate 110 . In some embodiments, at pressures ranging from 1.5 Torr to 100 Torr (e.g., 1.5 Torr, 5 Torr, 10 Torr, 20 Torr, 30 Torr, 40 Torr, 50 Torr, 60 Torr, 70 Torr, 80 Torr, 90 Torr, 100 Torr, or any value in the aforementioned interval), the temperature range is 1100°C to 1300°C (such as 1100°C, 1150°C, 1200°C, 1250°C, 1300°C, or any value in the aforementioned interval Numerical value) conditions, the chemical vapor deposition was performed. In some embodiments, the thickness of the silicon carbide layer 120 is 5 microns to 25 microns (eg, 5 microns, 10 microns, 15 microns, 20 microns, 25 microns, or any value in the aforementioned range).

Next, as shown in FIG. 1C , the silicon carbide layer 120 is heated to sublimate the silicon atoms on the surface of the silicon carbide layer 120 to form a graphene layer 130 on the silicon carbide layer 120 .

In some embodiments, the heating silicon carbide layer 120 can be included in a furnace tube (furnace) or in a chemical vapor deposition device, and the pressure is 50 Pa to 500 Pa (such as 50 Pa, 100 Pa, 200 Pa, or the aforementioned range. Any value in ), and the temperature is 950°C to 1400°C (such as 950°C, 1000°C, 1100°C, 1200°C, 1300°C, 1400°C, or any value in the preceding range) Under certain conditions, argon (Ar) gas is introduced at a gas flow rate of 1 liter/min to grow the graphene layer 130 .

In some embodiments, the heating of the silicon carbide layer 120 may include four temperature stages. The temperature of the first stage is 950°C to 1050°C. In this stage, the oxide on the surface of the silicon carbide layer 120 can be removed to enhance the silicon carbide Silicon atom content on the surface of layer 120 (silicon atoms are enriched on the surface). In the second stage, the temperature is increased from 1050°C to 1150°C for 10 minutes to restructure the surface structure of the silicon carbide layer 120 into a (√3x√3)R30° type. In the third stage, the temperature is increased to 1150°C to 1250°C for 20 minutes to change the structure of the surface of the silicon carbide layer 120 into a (6√3x6√3)R30° type as an interface buffer. structure. In the fourth stage, the temperature is further increased to 1300°C to 1400°C, thereby sublimating the silicon atoms and transforming the carbon atoms into the graphene layer 130 . Heating the silicon carbide layer 120 through the treatment of these multiple temperature stages gradually transforms the surface structure of the silicon carbide layer 120, which is beneficial to the subsequent formation of a graphene structure with a relatively continuous structure and a more consistent crystal form, so as to obtain a graphene structure with a higher thermal conductivity of the graphene layer 130 .

In some embodiments, the graphene layer 130 is a multilayer graphene structure with 10 to 150 layers (such as 10 layers, 20 layers, 30 layers, 40 layers, 50 layers, 60 layers, 70 layers, 80 layers, 90 layers, 100 layers, 110 layers, 120 layers, 130 layers, 140 layers, 150 layers, or any value in the aforementioned range), with a thickness of 3.4 nm to 51 nm (such as 3.4 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, or any value in the aforementioned range). In some embodiments, the number and thickness of the graphene layer 130 can be controlled by adjusting the temperature of the heating process, the number of heating stages, the duration of each stage, etc. according to actual needs. In some embodiments, the thickness of the graphene layer 130 can be increased by increasing the heating stage, extending the heating duration, or adjusting the two parameters at the same time.

Next, as shown in FIG. 1D , the first silicon substrate 110 is thinned.

In some embodiments, the second surface 110B of the first silicon substrate 110 can be polished to reduce the thickness T1 of the first silicon substrate 110 (please refer to FIG. 1C) to 80 microns to 120 microns. Thickness T2 (such as 80 microns, 90 microns, 100 microns, 110 microns, 120 microns, or a value in any of the aforementioned intervals), that is, thickness T2 is smaller than thickness T1 (please refer to Figure 1C), in order to reduce conduction resistance and thermal resistance , improving the action efficiency and heat dissipation efficiency of the subsequently formed composite substrate. In some implementations, after the first silicon substrate 110 is thinned, chemical mechanical polishing can be used to planarize the second surface 110B, so as to improve the first silicon substrate 110 through the insulating layer (for example, the insulating layer 140 in FIG. 1E ). ) and another silicon substrate (for example, the second silicon substrate 150 in FIGS. 1G to 1F ).

Next, please refer to FIG. 1E , an insulating layer 140 is formed under the second surface 110B of the first silicon substrate 110 opposite to the first surface 110A.

In some embodiments, the insulating layer 140 is grown using a high temperature furnace process or a chemical vapor deposition process. In some embodiments, the insulating layer 140 includes silicon dioxide. In some embodiments, the insulating layer 140 has a thickness of 0.5 microns to 10 microns (for example, 0.5 microns, 1 micron, 2 microns, 3 microns, 4 microns, 5 microns, 6 microns, 7 microns, 8 microns, 9 microns, 10 microns). microns, or any value within the preceding range).

Next, please refer to FIG. 1F , a second silicon substrate 150 is provided and the epitaxial multilayer E is disposed on the second silicon substrate 150 , wherein the epitaxial multilayer E includes gallium nitride.

In some embodiments, the material, property and thickness of the second silicon substrate 150 may be the same as or similar to that of the first silicon substrate 110 . It can be understood that, considering the lattice properties of the epitaxial multilayer E, the lattice orientation of the second silicon substrate 150 can be <111> to achieve better lattice matching with the epitaxial multilayer E.

In some embodiments, metal-organic chemical vapor deposition (Metal-organic Chemical Vapor Deposition; MOCVD) can be used to form an epitaxial multilayer E with a thickness of 1 to 10 microns on the first surface 150A of the second silicon substrate 150. (High electron mobility transistor (HEMT)). In some embodiments, the epitaxial multilayer E sequentially includes a seed layer disposed on the second silicon substrate 150, a buffer layer disposed on the seed layer, a resistive layer disposed on the buffer layer, a channel layer disposed on the resistive layer, a barrier layer The channel layer is disposed on the channel layer, and the cover layer is disposed on the barrier layer. In some embodiments, the seed layer may comprise aluminum nitride and have a thickness between 30 nm and 300 nm. In some embodiments, the buffer layer may comprise AlGaN, GaN, or combinations thereof, such as ladder AlGaN or superlattice AlGaN/GaN, with a thickness of 300 nm to 1000 nm. between nanometers. In some embodiments, the resistance layer is GaN, such as GaN doped with carbon or iron, and the thickness may be between 0.5 microns and 2.5 microns. In some embodiments, the channel layer is GaN with a thickness between 0.05 micron and 1 micron. In some embodiments, the barrier layer comprises aluminum gallium nitride and has a thickness between 10 nm and 50 nm. In some embodiments, the capping layer can be intrinsic GaN or p-type GaN with a thickness of 0.5 nm to 150 nm. In some embodiments, after the epitaxial multilayer E is formed, the gate and the source/drain are disposed on the epitaxial multilayer E successively.

In some embodiments, after forming the epitaxial multilayer E on the first surface 150A of the second silicon substrate 150, the second surface 150B of the second silicon substrate 150 can be thinned in a manner similar to that in FIG. 1D. The second silicon substrate 150 reduces the on-resistance and thermal resistance, and improves the action efficiency and heat dissipation efficiency of the subsequently formed composite substrate. In some embodiments, the thickness of the thinned second silicon substrate 150 is 0.2 microns to 10 microns (for example, 0.2 microns, 0.5 microns, 1 micron, 2 microns, 3 microns, 4 microns, 5 microns, 6 microns, 7 microns microns, 8 microns, 9 microns, 10 microns, or any value in the aforementioned range).

In some embodiments, in order to prevent the second silicon substrate 150 from warping due to being too thin after thinning, before thinning the second silicon substrate 150, glue that can be fixed by ultraviolet light or a known Adhesive technology, the temporary substrate is placed on the epitaxial multi-layer E, and the temporary substrate is removed after the second silicon substrate 150 is bonded to the insulating layer 140 (please also refer to FIG. 1E). In some embodiments, the temporary substrate may comprise a metal substrate, a glass substrate, a ceramic substrate, or a combination of two or more of the foregoing.

In some embodiments, after thinning the second silicon substrate 150, the second surface 150B can be planarized in a manner similar to that shown in FIG. The better the bonding effect).

Next, please refer to FIG. 1G , the insulating layer 140 and the second silicon substrate 150 are bonded to obtain the composite substrate 100 .

In some embodiments, the step of bonding the insulating layer 140 and the second silicon substrate 150 includes: attaching the insulating layer 140 and the second surface 150B of the second silicon substrate 150 to each other; and heating the insulating layer 140 and the second silicon substrate 150 , to bond the insulating layer 140 and the second silicon substrate 150 .

In some embodiments, bonding can be by means of fusion bonding or low temperature bonding.

In some embodiments, fusion bonding may be used to bond the insulating layer 140 to the second silicon substrate 150 . Specifically, fusion bonding is to contact the insulating layer 140 with the second surface 150B of the second silicon substrate 150 to be bonded in a vacuum environment, so as to utilize the Van der Waals force bonding between the two, and perform high temperature bonding after bonding. annealing treatment, so that the insulating layer 140 and the second silicon substrate 150 are covalently bonded to form a composite substrate 100 . In some embodiments, the high temperature annealing process is performed at a temperature of about 1000°C.

In some embodiments, low temperature bonding may be used to bond the insulating layer 140 to the second silicon substrate 150 . Specifically, low-temperature bonding is to perform plasma treatment on the insulating layer 140 to be bonded and the second silicon substrate 150 to increase the density of dangling bonds on the surface. Since the dangling bond is a high-energy structure, when the plasma-treated insulating layer 140 and the surface of the second silicon substrate 150 are in contact, in order to reduce energy, the two will combine the surface through a driving force. That is to say, by plasma processing the surface of the insulating layer 140 and the second surface 150B of the second silicon substrate 150 to be bonded, the density of the dangling bonds is increased, and the insulating layer 140 and the second silicon substrate 150 are to be bonded. The second surface 150B of the second silicon substrate 150B is contacted for bonding, and the low-temperature annealing treatment is performed after the bonding to complete the low-temperature bonding, and the insulating layer 140 and the second silicon substrate 150 are bonded to form the composite substrate 100 . In addition, the temperature at which the low temperature annealing treatment is performed is about 100°C to 400°C.

In some embodiments, the thickness of the composite substrate 100 is between 82.5 microns and 150 microns (such as 82.5 microns, 100 microns, 110 microns, 120 microns, 130 microns, 140 microns, 150 microns, or any value in the aforementioned range) .

Through the above-mentioned preparation steps in FIG. 1A to FIG. 1G, a composite substrate 100 can be obtained, including a graphene layer 130, a silicon carbide layer 120 disposed on the graphene layer 130, a first silicon substrate 110 disposed on the silicon carbide layer 120, The insulating layer 140 is disposed on the first silicon substrate 110 , the second silicon substrate 150 is disposed on the insulating layer 140 , and the epitaxial multilayer E is disposed on the second silicon substrate 150 . It is worth emphasizing that, compared to the aspect comprising only the first silicon substrate 110, the insulating layer 140, the second silicon substrate 150 and the epitaxial multilayer E, the thermal conductivity of silicon is only about 149 W/m·degree ( W/m·K) and the thermal conductivity of the insulating layer 140 (such as silicon dioxide) is only about 1.4 W/m·degree, and the composite substrate 100 also includes a silicon carbide layer 120 with a higher thermal conductivity (about 370 W /m·degree) and graphene layer 130 (about 5300 watts/m·degree), especially the existence of graphene layer 130 with high thermal conductivity, can greatly improve the heat dissipation efficiency of composite substrate 100, avoid composite substrate 100 When carrying the epitaxial multilayer E as a high-frequency component, the accumulated heat of the high-frequency component during operation limits the action efficiency.

FIG. 2A to FIG. 2F exemplarily describe the schematic diagrams of various process stages of manufacturing the composite substrate 200 in other embodiments of the present disclosure.

First, as shown in FIG. 2A , a first silicon substrate 210 is provided. The material, thickness T3, and lattice orientation of the first silicon substrate 210 may be the same or similar to those of the first silicon substrate 110 described in FIG. 1A , which will not be repeated here.

Next, as shown in FIG. 2B , a carburization process is performed to form a silicon carbide layer 220 on the first surface 210A of the first silicon substrate 210 .

In some embodiments, a carburizing furnace process is performed in a gas environment containing C ₃ H ₈ to form the silicon carbide layer 220 on the first surface 210A of the first silicon substrate 210 . In some embodiments, the carburizing furnace process is performed by feeding propane at a gas flow rate of 110 ml/min to 120 ml/min at a pressure ranging from 1.5 torr to 100 torr (e.g., 1.5 torr, 5 torr, 10 torr, 20 torr . 910°C, 920°C, 930°C, 940°C, 950°C, or any value in the aforementioned interval), the time is maintained for 30 minutes to 60 minutes (such as 30 minutes, 45 minutes, 60 minutes, or the aforementioned interval any value in ), diffuse carbon to the surface of the first silicon substrate 210 , and then process at a temperature of 30° C. to 55° C. to shape the silicon carbide structure to obtain the silicon carbide layer 220 . In some embodiments, the thickness of the silicon carbide layer 220 is 5 microns to 25 microns (eg, 5 microns, 10 microns, 15 microns, 20 microns, 25 microns, or any value in the aforementioned range). In some embodiments, the silicon carbide structure grown in the silicon carbide layer 220 may include 4H-SiC, 3C-SiC, 4H-SiC, 6H-SiC and other crystal structures. It is worth noting that, through the carburizing furnace process, the silicon carbide layer 220 is formed by using the principle of carbon diffusion, and the carbon can be more uniformly and continuously distributed between the silicon, which helps to form a more continuous process in the subsequent process. Extended graphene layers with high thermal conductivity.

Next, please refer to FIG. 2C, using a nitrogen-containing gas to perform a plasma-assisted selective reaction (Plasma-assisted Selective Reaction; PSR) on the silicon carbide layer 220, respectively forming a silicon nitride layer 230 on the silicon carbide layer 220 and graphite An alkene layer 240 is on the silicon nitride layer 230 .

Performing the plasma-assisted selective reaction on the SiC layer 220 may include two steps. In the first step, a plasma implantation reaction is performed on the silicon carbide layer 220 using nitrogen gas, and nitrogen atoms are used to break a plurality of carbon-silicon bonds in the silicon carbide layer 220 . In some embodiments, the frequency can be between 10 megahertz and 15 megahertz (such as 10 megahertz, 12 megahertz, 13.56 megahertz, 14 megahertz, 15 megahertz, or the aforementioned interval ), the power is 100 watts to 300 watts (such as 100 watts, 200 watts, 300 watts, or any value in the foregoing range), and the pressure is 1/100 torr to 1/10 torr (such as 1/100 torr , 1/50 Torr, 1/10 Torr, or any value in the foregoing range), using nitrogen gas, perform plasma implantation on the silicon carbide layer 220 for 20 minutes to 60 minutes. In the second step, an annealing process is performed on the silicon carbide layer 220 in an atmosphere containing nitrogen and hydrogen to form a silicon nitride layer 230 on the silicon carbide layer 220 and a graphene layer 240 on the silicon nitride layer 230 . In some embodiments, in a gas condition containing nitrogen and hydrogen, and at a temperature of 1000°C to 1300°C (such as 1000°C, 1050°C, 1100°C, 1150°C, 1200°C, 1250° C., 1300° C., or any value in the aforementioned range), perform an annealing process on the silicon carbide layer 220 for 10 minutes to 60 minutes. In the annealing process, nitrogen atoms will form a silicon nitride layer 230 (Si ₃ N ₄ structure) with silicon at high temperature (for example, 1150°C), and carbon atoms form a graphene layer on the silicon nitride layer 230 240. In addition, the hydrogen gas can react with oxygen to keep the reaction chamber clean and prevent components such as the silicon carbide layer 220 or the first silicon substrate 210 from being oxidized by oxygen. In some embodiments, the thickness of the silicon nitride layer 230 is 1 to 2 nanometers, and the thickness of the graphene layer 240 is 3 nanometers to 20 nanometers (such as 3 nanometers, 5 nanometers, 10 nanometers, 15 nanometers). meters, 20 nm, or any value within the preceding range).

Next, see FIG. 2D to FIG. 2F, thin the first silicon substrate 210 (FIG. 2D, that is, make the thickness T4 of FIG. 2D smaller than the thickness T3 of FIG. 2C), and form an insulating layer 250 on the first silicon substrate. On the second surface 210B of the substrate 210 (FIG. 2E), and the bonding insulating layer 250 and the second silicon substrate 260 (wherein the epitaxial multilayer E is disposed on the second silicon substrate 260, and the epitaxial multilayer E includes gallium nitride ) (FIG. 2F), a composite substrate 200 is obtained.

The specific process and materials in Figure 2D to Figure 2F can be basically the same or similar to the steps and materials in Figure 1D to Figure 1G (for example, Figure 2D can correspond to Figure 1D, and Figure 2E can correspond to Figure 1 FIG. 1E, FIG. 2F may correspond to FIG. 1F and FIG. 1G), and will not be repeated here.

Please refer to FIG. 2F, the composite substrate 200 includes a graphene layer 240, a silicon nitride layer 230 is disposed on the graphene layer 240, a silicon carbide layer 220 is disposed on the silicon nitride layer 230, and the first silicon substrate 210 is disposed on the silicon carbide layer. layer 220 , the insulating layer 250 is disposed on the first silicon substrate 210 , the second silicon substrate 260 is disposed on the insulating layer 250 , and the epitaxial multilayer E is disposed on the second silicon substrate 260 . It is worth emphasizing that the composite substrate 200 includes a silicon carbide layer 220 (about 370 W/m·degree) and a graphene layer 240 (about 5300 W/m·degree) with high thermal conductivity. The existence of the graphene layer 130 can greatly improve the heat dissipation efficiency of the composite substrate 200, and avoid the situation where the composite substrate 200 includes the epitaxial multilayer E as a high-frequency component, and the heat accumulation during operation limits the efficiency.

It is worth noting that, compared with the composite substrate 100 in FIG. 1G, the silicon carbide layer 120 is first formed through a chemical vapor deposition process, and then the silicon in the silicon carbide layer 120 is sublimated to form the graphene layer 130. FIG. 2F The composite substrate 200 of the company uses a carburizing furnace process to grow a silicon carbide layer 220 through carbon diffusion, and then uses nitrogen atoms to break the carbon-silicon bond and bond with silicon through a plasma-assisted selective reaction using nitrogen atoms. junction, the silicon nitride layer 230 is grown, and the carbon atoms form the graphene layer 240 . Those skilled in the art can select an appropriate method according to actual product specifications or manufacturing process requirements, and the manufacturing method of the disclosure is not limited thereto.

To sum up, some embodiments of the present disclosure provide composite substrates and manufacturing methods thereof. A graphene layer with high thermal conductivity is formed on a silicon substrate, and the high thermal conductivity of graphene is used to improve the heat dissipation efficiency of the composite substrate and improve Applying high-frequency components to composite substrates will reduce performance efficiency due to heat accumulation problems during operation, and improve the flexibility of composite substrate applications.

While this disclosure has described details in terms of certain implementations, other implementations are possible. Therefore, the spirit and scope of the appended claims should not be limited to the implementations described herein.

100, 200: composite substrate 110, 210: the first silicon substrate 110A, 150A, 210A: first surface 110B, 150B, 210B: second surface 120, 220: silicon carbide layer 130, 240: graphene layer 140, 250: insulating layer 150, 260: the second silicon substrate 230: silicon nitride layer E: epitaxial multilayer T1, T2, T3, T4: Thickness

A more complete understanding of the present disclosure can be obtained by reading the following detailed description of the embodiments with reference to the accompanying drawings. Figures 1A-1G exemplarily depict schematic diagrams of various process stages for manufacturing a composite substrate in accordance with some embodiments of the present disclosure. FIG. 2A to FIG. 2F exemplarily depict schematic diagrams of various process stages of manufacturing a composite substrate in other embodiments of the present disclosure.

100: composite substrate

110: The first silicon substrate

110A, 150A: first surface

110B, 150B: second surface

120: silicon carbide layer

130: graphene layer

140: insulating layer

150: the second silicon substrate

E: epitaxial multilayer

Claims (10)

A composite substrate comprising: a graphene layer; a silicon carbide layer disposed on the graphene layer; a first silicon substrate disposed on the silicon carbide layer; an insulating layer disposed on the first silicon substrate; and A second silicon substrate is arranged on the insulating layer. The composite substrate as claimed in claim 1, wherein the graphene layer is a multilayer graphene structure. The composite substrate as claimed in claim 1 further comprises a silicon nitride layer disposed between the graphene layer and the silicon carbide layer. The composite substrate as claimed in claim 1 further includes an epitaxial multilayer disposed on the second silicon substrate, including gallium nitride. A method of manufacturing a composite substrate comprising: forming a silicon carbide layer on a first surface of a first silicon substrate; forming a graphene layer on the silicon carbide layer; forming an insulating layer under a second surface of the first silicon substrate opposite to the first surface; and Bonding the insulating layer and a second silicon substrate to obtain a composite substrate. The method according to claim 5, further comprising the step of: thinning the first silicon substrate after the step of forming the graphene layer on the silicon carbide layer. The method according to claim 5, wherein the step of forming the silicon carbide layer on the first surface of the first silicon substrate comprises the steps of: performing a chemical vapor deposition process to form the silicon carbide layer; and The step of forming the graphene layer on the silicon carbide layer includes the step of: heating the silicon carbide layer to sublimate a plurality of silicon atoms on the surface of the silicon carbide layer to form the graphene layer. The method according to claim 5, wherein the step of forming the silicon carbide layer on the first surface of the first silicon substrate comprises the steps of: performing a carburizing furnace process to form the silicon carbide layer; and The step of forming the graphene layer on the silicon carbide layer includes the steps of: performing a plasma-assisted selective reaction on the silicon carbide layer using a nitrogen-containing gas, respectively forming a silicon nitride layer on the silicon carbide layer and The graphene layer is on the silicon nitride layer. The method as recited in claim 8, wherein the step of performing a plasma-assisted selective reaction on the silicon carbide layer comprises the steps of: performing a plasma implantation reaction on the silicon carbide layer using nitrogen gas to break a plurality of carbon-silicon bonds in the silicon carbide layer; and In a gas environment containing nitrogen and hydrogen, an annealing process is performed on the silicon carbide layer to form the silicon nitride layer on the silicon carbide layer and the graphene layer on the silicon nitride layer. The method as claimed in claim 5, wherein before the step of bonding the insulating layer and the second silicon substrate, comprising the step of: forming an epitaxial multilayer comprising gallium nitride on a first surface of the second silicon substrate on; and The step of bonding the insulating layer and the second silicon substrate includes the steps of: attaching the insulating layer to a second surface of the second silicon substrate opposite to the first surface; and The insulating layer and the second silicon substrate are heated to bond the insulating layer and the second silicon substrate.

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