TW202304138A - Sweep voltage generator and display panel - Google Patents

Abstract

A sweep generator circuit including a ramp generation circuit and a buffer stage is provided. The ramp generation circuit receives a reset signal, a first scan signal and a second scan signal which is inverted from the first scan signal, to provide a sweep reference voltage. The buffer stage receives the sweep reference voltage to provide a sweep signal in response to the sweep reference voltage. When the reset signal is disabled, the sweep signal drops from a preparation level to a stop level with time, and the first scan signal and the second scan signal determine the slope of the sweep signal.

Description

Ramp wave voltage generator and display panel

The present invention relates to a voltage generator, and in particular to a ramp voltage generator and a display panel.

In recent years, self-luminous displays have risen, among which organic light-emitting diode displays (OLED) and quantum dot light-emitting diode displays (QLED) are competing for the exclusive position of liquid crystal display (LCD) in display panels, and micro light-emitting diodes (Micro -LED) display is expected to become the mainstream of next-generation display technology based on its many excellent component characteristics.

In the micro light-emitting diode display, the pixel circuit can receive a ramp signal from an external digital-to-analog converter and use the ramp signal and written data to determine the current width of the diode. Moreover, the digital-to-analog converter converts the digital control signal provided by the Field Programmable Logic Gate Array (FPGA) into an analog signal to generate a required waveform. However, the above-mentioned method has a relatively complicated driving structure and a higher cost.

The invention provides a ramp wave generating circuit with a relatively simple circuit structure, so a digital-to-analog converter with high cost and complex control is not needed, so as to reduce the overall hardware cost and control complexity.

The slope voltage generator of the present invention includes a slope generating circuit and a buffer stage. The slope generation circuit receives the reset signal, the first scan signal and the second scan signal which is opposite to the first scan signal to generate a ramp reference voltage. The buffer stage receives a ramp reference voltage and provides a ramp signal in response to the ramp reference voltage. When the reset signal is disabled, the ramp signal drops from the ready level to the stop level with time, and the first scan signal and the second scan signal determine the slope of the ramp signal.

Based on the above, in the ramp wave generation circuit of the embodiment of the present invention, the ramp wave generation circuit is composed of a driver stage and a buffer with a relatively simple circuit structure, thereby eliminating the need for high-cost and complex-control digital-to-analog converters to reduce the overall hardware cost and control complexity.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

100: ramp voltage generator

110: Slope generating circuit

120: buffer level

301, 302, 303: curve

400: display panel

C1: the first capacitor

C2: second capacitor

d1: the first direction

d2: second direction

DL: source line

G1-G4: gate signal

GL: gate line

PX: pixel

RESET: reset signal

S1: the first scan signal

S1-S4: Source signal

S2: Second scan signal

T1: first transistor

T2: second transistor

T3: The third transistor

T4: The fourth transistor

T5: fifth transistor

VBP1: first bias voltage

VBP2: second bias voltage

VGH: gate high voltage

VGL: gate low voltage

VH: high voltage level

VL: low voltage level

Vpre: preset level

Vramp: ramp reference voltage

Vref: reference voltage

Vstop: stop level

Vsweep: ramp signal

FIG. 1 is a schematic circuit diagram of a ramp voltage generator according to an embodiment of the invention.

FIG. 2 is a schematic diagram of driving waveforms of a ramp voltage generator according to an embodiment of the present invention.

FIG. 3 is a control diagram of driving waveforms of a ramp voltage generator according to an embodiment of the present invention.

FIG. 4 is a system diagram of a display panel according to an embodiment of the invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.

It should be understood that although the terms "first", "second", "third" and the like may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or or parts thereof shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" unless the content clearly dictates otherwise. "or" means "and/or". As used herein, the term "and/or" includes one or more Any and all combinations of the relevant listed items. It should also be understood that when used in this specification, the terms "comprising" and/or "comprising" designate the stated features, regions, integers, steps, operations, the presence of elements and/or components, but do not exclude one or more Existence or addition of other features, regions as a whole, steps, operations, elements, parts and/or combinations thereof.

FIG. 1 is a schematic circuit diagram of a ramp voltage generator according to an embodiment of the invention. Referring to the figure, in this embodiment, the ramp voltage generator 100 includes a ramp generating circuit 110 and a buffer stage 120 . The ramp generating circuit 110 receives a reference voltage Vref, a reset signal RESET, a first scan signal S1 , a second scan signal S2 which is inverse to the first scan signal S1 , and a gate low voltage VGL to generate a ramp reference voltage Vramp. The buffer stage 120 receives the ramp reference voltage Vramp, the gate high voltage VGH and the gate low voltage VGL to respond to the ramp reference voltage Vramp and provide the ramp signal Vsweep to the pixels (400 in FIG. 4 ) of the display panel ( PX as shown in Figure 4). Wherein, the first sweep signal S1 and the second sweep signal S2 determine the slope of the ramp signal Vsweep, that is, the descending slope of the ramp signal Vsweep is controlled by the frequency of the first sweep signal S1 and the second sweep signal S2. Moreover, the ramp signal Vsweep drops from the preset level (Vpre as shown in FIG. 2 ) to the stop level (Vstop as shown in FIG. 2 ) in response to the level switching of the reset signal RESET.

In this embodiment, the slope generating circuit 110 is only composed of transistors and capacitors, and the buffer stage 120 is only composed of transistors, so the slope generating circuit 110 has a relatively simple circuit structure, thereby eliminating the need for high cost and complicated control. Digital-to-analog converter to reduce overall hardware cost and control complexity.

In this embodiment, the ramp generating circuit 110 includes a first transistor T1, The second transistor T2, the third transistor T3, the first capacitor C1 and the second capacitor C2. The first capacitor C1 has a first terminal and a second terminal coupled to the gate low voltage VGL. The first transistor T1 has a first end receiving the first bias voltage VBP1 , a second end coupled to the first end of the first capacitor C1 , and a control end receiving the first scan signal S1 . The second transistor T2 has a first terminal coupled to the first terminal of the first capacitor C1 , a second terminal providing the ramp reference voltage Vramp, and a control terminal receiving the second scan signal S2 .

The third transistor T3 has a first terminal receiving the reference voltage Vref, a second terminal coupled to the ramp reference voltage Vramp, and a control terminal receiving the reset signal RESET. The second capacitor C2 is coupled between the ramp reference voltage Vramp and the gate low voltage VGL.

The buffer stage 120 includes a fourth transistor T4 and a fifth transistor T5. The fourth transistor T4 has a first terminal for providing the ramp signal Vsweep, a second terminal for receiving the gate low voltage VGL, and a control terminal for receiving the ramp reference voltage Vramp. The fifth transistor T5 has a first terminal receiving the gate high voltage VGH, a second terminal coupled to the first terminal of the fourth transistor T4, and a control terminal receiving the second bias voltage VBP2.

In this embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are P-type transistors, but this embodiment of the present invention does not limit. Moreover, the fourth transistor T4 and the fifth transistor T5 can operate in a saturation region.

FIG. 2 is a schematic diagram of driving waveforms of a ramp voltage generator according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 2, when the reset signal RESET is switched from the high voltage level VH to the low voltage level VL (that is, the reset signal RESET is enabled), the third transistor The body T3 is turned on, so the reference voltage Vref is transmitted to the second capacitor C2, so that the voltage level of the ramp reference voltage Vramp is maintained at the reference voltage Vref. At this time, the voltage level of the ramp signal Vsweep (that is, the preparation level Vpre) is the sum of the reference voltage Vref and the voltage difference between the source and the gate of the fourth transistor T4. Moreover, the first scan signal S1 is at the high voltage level VH and the second scan signal S2 is at the low voltage level VL, the first transistor T1 is turned off and the second transistor T2 is turned on, so that the first capacitor C1 and the second capacitor The charge of C2 is equalized, that is, the voltage difference (or potential) stored in the first capacitor C1 and the second capacitor C2 will gradually approach to be equal (if time is sufficient).

Then, when the reset signal RESET is switched from the low voltage level VL to the high voltage level VH, the first scan signal S1 and the second scan signal S2 start to oscillate (that is, the high voltage level VH and the low voltage level VL alternately ). When the first scanning signal S1 is at the low voltage level VL and the second scanning signal S2 is at the high voltage level VH, the first transistor T1 is turned on and the second transistor T2 is turned off. At this time, the voltage stored in the first capacitor C1 The difference (or potential) will gradually approach the first bias voltage VBP1. When the first scan signal S1 is at the high voltage level VH and the second scan signal S2 is at the low voltage level VL, the first transistor T1 is turned off and the second transistor T2 is turned on, so that the first capacitor C1 and the second capacitor The pressure difference (or potential) stored by C2 will gradually approach.

Through the oscillation of the voltage levels of the first scan signal S1 and the second scan signal S2 , the voltage level of the ramp reference voltage Vramp is gradually pulled down from the reference voltage Vref to the first bias voltage VBP1 . Moreover, the slope of the reference voltage Vref being gradually pulled down to the first bias voltage VBP1 can refer to the following equation:

k1=C1/(C1+C2)

k2=C2/(C1+C2)

Vramp,0=reference voltage Vref

Conditioned on a fixed slope, the frequency

Wherein, T is the cycle time of the first scanning signal S1 and the second scanning signal S2, and when the slope Sn is set to be linear, the frequency f can increase with time, but the embodiment of the present invention does not take this as a limit.

FIG. 3 is a control diagram of driving waveforms of a ramp voltage generator according to an embodiment of the present invention. Please refer to Fig. 1 and Fig. 3, in the present embodiment, the frequency of the first scan signal S1 and the second scan signal S2 is, for example, 25 kilohertz (kHz), 2 kilohertz, and increases from 2 kilohertz to 25 kHz. The curve 301 reflects that the frequencies of the first scanning signal S1 and the second scanning signal S2 increase from 2 kHz to 8.51 kHz. The curve 302 reflects that the frequency of the first scanning signal S1 and the second scanning signal S2 is 2 kHz. The curve 303 reflects that the frequency of the first scanning signal S1 and the second scanning signal S2 is 25 kHz.

According to the curves 301 to 303 , if the slope of the desired ramp reference voltage Vramp is linear, the frequency of the first scan signal S1 and the second scan signal S2 can be set to increase from 2 kHz to 8.51 kHz. If the desired ramp reference voltage When the slope of Vramp is linear, the frequency of the first scanning signal S1 and the second scanning signal S2 can be set to 2 kHz. If the slope of the desired ramp reference voltage Vramp is linear, the frequencies of the first scanning signal S1 and the second scanning signal S2 can be set to 25 kHz. In this way, the slope characteristic of the ramp signal can be adjusted through the frequencies of the first scanning signal and the second scanning signal, so as to control the circuit operation of the pixel.

FIG. 4 is a system diagram of a display panel according to an embodiment of the invention. Referring to FIG. 1 and FIG. 1 , in this embodiment, the display panel 400 includes a plurality of pixels PX, a plurality of gate lines GL, a plurality of source lines DL, and a ramp voltage generator 100 . The pixels PX are arranged in an array. The gate lines GL individually receive one of a plurality of gate signals (such as G1 - G4 ), each extend along the first direction d1, and are individually coupled to some of the pixels PX. The source lines DL individually receive one of a plurality of source signals (such as S1-S4), each extend along the second direction d2 perpendicular to the first direction d1, and are individually coupled to some of these pixels PX . The ramp voltage generator 100 is coupled to all pixels PX to provide a ramp signal Vsweep to all pixels PX at the same time. The circuit structure and operation of the ramp voltage generator 100 can be shown in FIG. 1 to FIG. 3 . This will not be repeated.

In this embodiment, the ramp voltage generator 100 can be configured on the display panel 400, but in other embodiments, the ramp voltage generator 100 can be configured on a film substrate connected to the display panel 400, such as a ramp The voltage generator 100 can be integrated into the source driver, but the embodiment of the present invention is not limited thereto.

To sum up, in the ramp wave generation circuit of the embodiment of the present invention, the ramp wave generation circuit is composed of a driver stage and a buffer with a relatively simple circuit structure, thereby eliminating the need for High-cost and complex-control digital-to-analog converters to reduce overall hardware cost and control complexity.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100: ramp voltage generator

110: Slope generating circuit

120: buffer level

C1: the first capacitor

C2: second capacitor

RESET: reset signal

S1: the first scan signal

S2: Second scan signal

T1: first transistor

T2: second transistor

T3: The third transistor

T4: The fourth transistor

T5: fifth transistor

VBP1: first bias voltage

VBP2: second bias voltage

VGH: gate high voltage

VGL: gate low voltage

Vramp: ramp reference voltage

Vref: reference voltage

Vsweep: ramp signal

Claims (9)

A ramp voltage generator comprising: a ramp generating circuit, receiving a reset signal, a first scan signal and a second scan signal opposite to the first scan signal to generate a ramp reference voltage: and a buffer stage, receiving the ramp reference voltage to provide a ramp signal in response to the ramp reference voltage, Wherein when the reset signal is disabled, the ramp signal drops from a ready level to a stop level with time, and the first scan signal and the second scan signal determine the slope of the ramp signal. The ramp voltage generator as claimed in item 1, wherein the ramp generating circuit includes: a first capacitor having a first terminal and a second terminal coupled to a very low gate voltage; A first transistor having a first terminal receiving a first bias voltage, a second terminal coupled to the first terminal of the first capacitor, and a control terminal receiving the first scan signal; a second transistor, having a first end coupled to the first end of the first capacitor, a second end providing the ramp reference voltage, and a control end receiving the second scan signal; a third transistor having a first end receiving a reference voltage, a second end coupled to the ramp reference voltage, and a control end receiving the reset signal; and A second capacitor is coupled between the ramp reference voltage and the gate low voltage. The ramp voltage generator as described in claim 2, wherein the buffer stage includes: A fourth transistor has a first end for providing the ramp signal, a second end for receiving a gate low voltage, and a control end for receiving the ramp reference voltage; and A fifth transistor has a first terminal receiving a very high gate voltage, a second terminal coupled to the first terminal of the fourth transistor, and a control terminal receiving a second bias voltage. The ramp voltage generator as claimed in claim 3, wherein the fourth transistor and the fifth transistor operate in a saturation region. The slope voltage generator as claimed in item 3, wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are each a P-type transistor . The ramp voltage generator as claimed in claim 1, wherein the ramp signal is maintained at the ready level when the reset signal is enabled. The ramp voltage generator as claimed in claim 1, wherein the falling slope of the ramp signal is controlled by the frequencies of the first scanning signal and the second scanning signal. The ramp voltage generator as claimed in claim 7, wherein the frequencies of the first scanning signal and the second scanning signal increase with time. A display panel, comprising: Multiple pixels, arranged in an array; a plurality of gate lines, each extending along a first direction, and being individually coupled to some of the pixels; a plurality of source lines respectively extending along a second direction perpendicular to the first direction and respectively coupled to some of the pixels; and A ramp voltage generator as described in claim 1 is coupled to the pixels to provide a ramp signal to the pixels.

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