CN205753946U - A kind of time decision circuitry module for blood pressure lowering manipulator - Google Patents
A kind of time decision circuitry module for blood pressure lowering manipulator Download PDFInfo
- Publication number
- CN205753946U CN205753946U CN201620592093.6U CN201620592093U CN205753946U CN 205753946 U CN205753946 U CN 205753946U CN 201620592093 U CN201620592093 U CN 201620592093U CN 205753946 U CN205753946 U CN 205753946U
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- circuit
- signal
- blood pressure
- field effect
- pressure lowering
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Abstract
A kind of time decision circuitry module for blood pressure lowering manipulator, this utility model relates to blood pressure lowering manipulator detection technique field, it aims to solve the problem that prior art judges that turn-off time and turn on time delay are serious, and causes punching suppression signal to have delay and comparison reference voltage to arrange the technical problems such as unreasonable.Input circuit, has cascade audion, receives input signal and output signal；Current mirroring circuit, the voltage signal changing input circuit correspondence input signal and output signal generation is the first current signal；Scanning switch circuit, receives the first current signal of current mirroring circuit output；Ramp circuit, receives the second current signal of scanning switch circuit output；Time decision circuitry, including comparator, comparator is provided with the reference voltage mated with ramp circuit, at least receives the ramp voltage of ramp circuit output.This utility model is for reducing the delay of blood pressure lowering manipulator middle controller detection turn-off time and ON time.
Description
Technical field
This utility model relates to blood pressure lowering manipulator detection technique field, is specifically related to a kind of time for blood pressure lowering manipulator
Decision circuitry module.
Background technology
The stable output voltage that is adjusted is provided Power Processing by the conversion of DC input voltage by DC to DC transducer
Device, ASICS, memorizer and other circuit.Develop DC to the DC transducer of all kinds and form, comprised and be less than for offer
The step-down controller of the output voltage of input voltage, and the boost conversion of the output voltage higher than input voltage can be provided
Device.Type of voltage step-up/down converter provides by can provide the ability being adjusted output voltage more than or less than the level of input voltage.A kind of
The type of voltage step-up/down converter of form is referred to as by being followed by, in buck power level, the cascade buck conversion that pressure power stage of continuing rising is formed
Device.But, there is prominent delay problem, the ON time Ton of controller and turn-off time in current core control portions
Toff detection occur at needs punching suppression time, when occurring to rush, existing structure by produce same frequency compensation signal allow
Controller sent punching suppression signal, but now this crosses punching time shift on wave spectrum, and crossing punching suppression has delay, produces circuit
Raw unfavorable；Existing structure comparator reference voltage arranges the most unreasonable.
Summary of the invention
For above-mentioned prior art, this utility model purpose is to provide, and it aims to solve the problem that when prior art judges to turn off
Between and turn on time delay serious, and caused punching suppression signal to have delay and comparison reference voltage to arrange the technology such as unreasonable to ask
Topic.
For reaching above-mentioned purpose, the technical solution adopted in the utility model is as follows:
A kind of time decision circuitry module for blood pressure lowering manipulator, including input signal and the output letter of blood pressure lowering manipulator
Number, also include input circuit, there is cascade audion, receive input signal and output signal；Current mirroring circuit, changes defeated
The voltage signal entering circuit correspondence input signal and output signal generation is the first current signal；Scanning switch circuit, is used for controlling
Shutoff cycle processed and control turn-on cycle, receive the first current signal of current mirroring circuit output；Ramp circuit, is used for turning on week
In phase, charging and electric discharge in the cycle of shutoff, receive the second current signal of scanning switch circuit output；Time decision circuitry, wherein
Including comparator, comparator is provided with the reference voltage mated with ramp circuit, at least receives the slope electricity of ramp circuit output
Pressure.
In such scheme, described input circuit, including the first audion, its base stage receives output signal and colelctor electrode leads to
Cross the first resistance connection and have power supply；Second audion, its base stage connects emitter stage and the emitter stage reception input of the first audion
Signal.
In such scheme, described current mirroring circuit, including a pair common gate field effect transistor and field, a pair cascade pole
Effect pipe；Wherein, a pair described common gate field effect transistor receives input signal and the voltage signal of output signal generation；Described
A pair cascade pole field effect transistor connect described in a pair common gate field effect transistor, also export the first current signal.
In such scheme, described current mirroring circuit, including a pair common source field effect transistor, its drain electrode is connected respectively described
The source electrode of a pair common gate field effect transistor；First current source, absorbs the source current of the pair of common source field effect transistor.
In such scheme, described scanning switch circuit, including switched field effect pipe, its grid receives scan clock and leakage
Pole receives the first current signal.
In such scheme, described scanning switch circuit, also include the first diode, its low electrode connecting valve field effect
The drain electrode of pipe；Second diode, the source electrode of its low electrode connecting valve field effect transistor；Wherein, the first diode and the two or two pole
Pipe high electrode ground connection.The parasitic capacitance of suppression switched field effect pipe the non-linear distortion of compensated scanning clock.
In such scheme, described ramp circuit, including the first potentiometer, receive the second current signal；3rd audion,
Its colelctor electrode connects base stage, colelctor electrode is also connected with the first potentiometer and grounded emitter；Second potentiometer, connects the first current potential
Device；Electric capacity, its one end connects the first potentiometer and other end ground connection；Second current source, for the electric charge of Absorption Capacitance, connects the
Two potentiometers.
In such scheme, described time decision circuitry, including comparator, its high electrical input connects ramp circuit and low
Electrical input connects reference voltage；NAND gate, its input port connects to be had enable signal and connects the outfan of comparator, defeated
Go out to turn on clock signal.
Compared with prior art, the beneficial effects of the utility model:
By receive blood pressure lowering manipulator input/output signal, utilize current mirroring circuit, to meet scan period relation and
The electric current of CL Compare Logic detects, and beneficially controller detects when there being punching to occur and suppresses, and significantly reduces
Detection time delay, is more reasonably provided with CL Compare Logic；Suppress the parasitic capacitance of switched field effect pipe the non-of compensated scanning clock
Linear distortion.
Accompanying drawing explanation
Fig. 1 is of the present utility model to be embodied as circuit diagram；
Fig. 2 is potentiometer schematic diagram of the present utility model.
Detailed description of the invention
All features disclosed in this specification, or disclosed all methods or during step, except mutually exclusive
Feature and/or step beyond, all can combine by any way.
Below in conjunction with the accompanying drawings this utility model is described further:
Embodiment 1
As Fig. 1, pull-up power vd D receive buck controller by resistance R6 connecting triode Q1, audion Q1 base stage
Output signal Vout；Audion Q2 emitter stage receives the input signal of buck controller, and its colelctor electrode connects field effect transistor Q4
Drain electrode；The drain electrode of field effect transistor Q4 connects its grid, and its grid is also connected with the grid of field effect transistor Q3；Field effect transistor Q3
Drain electrode connects the drain electrode of field effect transistor Q5；The drain electrode of field effect transistor Q5 is also connected with its grid, and its source electrode connects pull-up power vd D,
And its grid connects the grid of field effect transistor Q6；The source electrode of field effect transistor Q6 connects pull-up power vd D, drain electrode output electric current I, electricity
The current value of stream I is proportional to the voltage difference of output signal Vout and input signal Vin；The grid of field effect transistor Q7 is inputted
Scan clock CLK_SCAN characterizes turn-on cycle and the cycle of shutoff, and field effect transistor Q7 connects also by resistance R7 current detecting end
Isense, it may be judged whether working properly；Audion Q1 emitter stage, also by the resistance R1 connected, diode D3 ground connection, can guide
Current source I2 exports electric current；Field effect transistor Q9 grid connects has feedback voltage Vfb, feedback voltage Vfb to be adopted by output signal Vout
Sample gained, when circuit does not works, redundancy electric charge in loop can quickly be released by the feedback voltage Vfb of over-sampling；Field effect transistor
Q10 grid connects reference voltage Vref 1, and setting can mate feedback voltage Vfb, it is possible to the controller by blood pressure lowering manipulator is direct
There is provided.
Embodiment 2
In scan clock CLK_SCAN turn-on cycle, base stage that reference voltage Vref is audion Q8 is set to emitter stage
Voltage Vbe, preset potentiometer to suitable resistance, electric current I is much larger than current source I1, the most negligible, electric capacity C1 quilt
Charging to equilibrium state, comparator U2 does not the most export, and NAND gate is output as turning on clock signal Ton；At scan clock CLK_
In the SCAN shutoff cycle, electric capacity C1 is under the driving of current source I1, and repid discharge, formation ramp signal, this signal will make ratio
Relatively device U2 obtains output, and now NAND gate is output as turning off clock signal Toff, it is achieved quickly cut-off signals and Continuity signal
Detection, does not use the form of output feedback to detect, and delay acquisition significantly reduces.
Embodiment 3
Such as Fig. 2, the first described potentiometer or the second potentiometer, select WIJ3266 type presetting multi-turn cermet potentiometer,
(A) being elevation structure, (B) is the side profile structure of partial cross section, and primary structure includes shell and adjusting rod, regulation
The opering characteristics of electric apparatus such as the inner termination of bar mates grafting with the upper adjustment cap of glass glaze preset potentiometer, Effective Electrical Travel are wide, high temperature resistant,
Antivibration, simple in construction and with low cost.
The above, detailed description of the invention the most of the present utility model, but protection domain of the present utility model does not limit to
In this, any belong to those skilled in the art in the technical scope that this utility model discloses, the change that can readily occur in
Change or replace, all should contain within protection domain of the present utility model.
Claims (8)
1. for a time decision circuitry module for blood pressure lowering manipulator, including input signal Vin and the output of blood pressure lowering manipulator
Signal Vout, it is characterised in that also include
Input circuit, has cascade audion, receives input signal Vin and output signal Vout；
Current mirroring circuit, the voltage signal changing input circuit correspondence input signal Vin and the generation of output signal Vout is first
Current signal；
Scanning switch circuit, is used for controlling the shutoff cycle and controlling turn-on cycle, receives the first electric current of current mirroring circuit output
Signal；
Ramp circuit, charges in turn-on cycle and discharges in the shutoff cycle, receives the second electricity of scanning switch circuit output
Stream signal；
Time decision circuitry, including comparator, comparator is provided with the reference voltage mated with ramp circuit, at least receives
The ramp voltage of ramp circuit output.
A kind of time decision circuitry module for blood pressure lowering manipulator the most according to claim 1, it is characterised in that described
Input circuit, including
First audion Q1, its base stage receives output signal Vout and colelctor electrode has power vd D by the first resistance R6 connection；
Second audion Q2, its base stage connects emitter stage and emitter stage reception input signal Vin of the first audion Q1.
A kind of time decision circuitry module for blood pressure lowering manipulator the most according to claim 1, it is characterised in that described
Current mirroring circuit, including
A pair common gate field effect transistor and a pair cascade pole field effect transistor；
Wherein, a pair described common gate field effect transistor receives input signal Vin and the voltage signal of output signal Vout generation；
Described a pair common gate field effect transistor described in a pair cascade pole field effect transistor connection, also exports the first electric current letter
Number.
A kind of time decision circuitry module for blood pressure lowering manipulator the most according to claim 3, it is characterised in that described
Current mirroring circuit, including
A pair common source field effect transistor, its drain electrode is connected respectively the source electrode of the pair of common gate field effect transistor；
First current source I2, absorbs the source current of the pair of common source field effect transistor.
A kind of time decision circuitry module for blood pressure lowering manipulator the most according to claim 1, it is characterised in that institute
The scanning switch circuit stated, including
Switched field effect pipe Q7, its grid receives scan clock CLK_SCAN and drain electrode receives the first current signal.
A kind of time decision circuitry module for blood pressure lowering manipulator the most according to claim 5, it is characterised in that described
Scanning switch circuit, also include
First diode D1, the drain electrode of its low electrode connecting valve field effect transistor Q7；
Second diode D2, the source electrode of its low electrode connecting valve field effect transistor Q7；
Wherein, the first diode D1 and the second diode D2 high electrode ground connection.
A kind of time decision circuitry module for blood pressure lowering manipulator the most according to claim 1, it is characterised in that described
Ramp circuit, including
First potentiometer, receives the second current signal；
3rd audion Q8, its colelctor electrode connects base stage, colelctor electrode is also connected with the first potentiometer and grounded emitter；
Second potentiometer, connects the first potentiometer；
Electric capacity C1, its one end connects the first potentiometer and other end ground connection；
Second current source I1, for the electric charge of Absorption Capacitance C1, connects the second potentiometer.
A kind of time decision circuitry module for blood pressure lowering manipulator the most according to claim 1, it is characterised in that described
Time decision circuitry, including
Comparator U2, its high electrical input connects ramp circuit and the connection of low electrical input has reference voltage Vref 2；
NAND gate U1A, its input port connects to be had enable signal Ven and connects the outfan of comparator U2, output conducting clock
Signal Ton.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620592093.6U CN205753946U (en) | 2016-06-16 | 2016-06-16 | A kind of time decision circuitry module for blood pressure lowering manipulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620592093.6U CN205753946U (en) | 2016-06-16 | 2016-06-16 | A kind of time decision circuitry module for blood pressure lowering manipulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205753946U true CN205753946U (en) | 2016-11-30 |
Family
ID=57385562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620592093.6U Expired - Fee Related CN205753946U (en) | 2016-06-16 | 2016-06-16 | A kind of time decision circuitry module for blood pressure lowering manipulator |
Country Status (1)
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|---|---|
| CN (1) | CN205753946U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106385177A (en) * | 2016-10-19 | 2017-02-08 | 成都益睿信科技有限公司 | Oscillator circuit based on synchronous input signal current source |
| CN114299855A (en) * | 2021-07-02 | 2022-04-08 | 友达光电股份有限公司 | Ramp voltage generator and display panel |
-
2016
- 2016-06-16 CN CN201620592093.6U patent/CN205753946U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106385177A (en) * | 2016-10-19 | 2017-02-08 | 成都益睿信科技有限公司 | Oscillator circuit based on synchronous input signal current source |
| CN114299855A (en) * | 2021-07-02 | 2022-04-08 | 友达光电股份有限公司 | Ramp voltage generator and display panel |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20161130 Termination date: 20180616 |