TW202303918A - Semiconductor packaging structure, method, device and electronic product - Google Patents

Semiconductor packaging structure, method, device and electronic product Download PDF

Info

Publication number
TW202303918A
TW202303918A TW111104271A TW111104271A TW202303918A TW 202303918 A TW202303918 A TW 202303918A TW 111104271 A TW111104271 A TW 111104271A TW 111104271 A TW111104271 A TW 111104271A TW 202303918 A TW202303918 A TW 202303918A
Authority
TW
Taiwan
Prior art keywords
packaged component
packaged
groove
pad
substrate
Prior art date
Application number
TW111104271A
Other languages
Chinese (zh)
Other versions
TWI818429B (en
Inventor
維平 李
Original Assignee
大陸商上海易卜半導體有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 大陸商上海易卜半導體有限公司 filed Critical 大陸商上海易卜半導體有限公司
Publication of TW202303918A publication Critical patent/TW202303918A/en
Application granted granted Critical
Publication of TWI818429B publication Critical patent/TWI818429B/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/111—Manufacture and pre-treatment of the bump connector preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Abstract

The invention provides a semiconductor packaging structure, method and device and an electronic product. In the semiconductor packaging structure, first packaged elements are fixed in first grooves in a one-to-one correspondence mode, second packaged elements are fixed in second grooves in a one-to-one correspondence mode, the first packaged elements are in a bare core state, and the second packaged elements are in a packaged state and are provided with exposed second electrode structures. The substrate is made of a semiconductor material or an insulating material, the thermal expansion coefficient of the substrate is the same as or similar to that of the semiconductor material in the first packaged element, and the rewiring layer is formed by a wafer manufacturing process. The semiconductor packaging structure is small in warping degree, high in reliability, mature in process, high in interconnection density and small in area, and the assembly process between packaged elements is reduced.

Description

半導體封裝結構、方法、器件和電子產品Semiconductor packaging structure, method, device and electronic product

本申請屬於半導體製造技術領域，具體涉及一種半導體封裝結構、方法、器件和電子產品。The application belongs to the technical field of semiconductor manufacturing, and in particular relates to a semiconductor packaging structure, method, device and electronic product.

現有半導體封裝製造工藝中，需要對被封裝元件（例如是裸芯，也稱die）進行封裝，進而得到半導體器件。通常的工藝是將被封裝元件固定在基板（substrate）、框架（leadframe）或轉接板（interposer）上，然後再用互聯和塑封等一系列工藝實現對被封裝元件的包覆，從而得到封裝好的半導體器件。封裝好的半導體器件再與其他封裝好的半導體器件進行組裝（即實現二者的電連接以及機械固定）。In the existing semiconductor packaging manufacturing process, it is necessary to package the packaged components (for example, a bare core, also called die) to obtain a semiconductor device. The usual process is to fix the packaged components on the substrate (substrate), frame (leadframe) or interposer (interposer), and then use a series of processes such as interconnection and plastic packaging to cover the packaged components, so as to obtain packaging good semiconductor device. The packaged semiconductor device is then assembled with other packaged semiconductor devices (that is, to realize the electrical connection and mechanical fixation of the two).

本申請的目的在於提供一種半導體封裝結構、方法、器件和電子產品。The purpose of this application is to provide a semiconductor packaging structure, method, device and electronic product.

為解決上述技術問題，本申請採用如下技術方案：一種半導體封裝結構，包括：襯底、至少一個第一被封裝元件、至少一個第二被封裝元件、重佈線層和鈍化層，所述襯底上開設有至少一個第一凹槽和至少一個第二凹槽，所述第一被封裝元件一一對應地固定在所述第一凹槽內，所述第二被封裝元件一一對應地固定在所述第二凹槽內，所述第一被封裝元件呈裸芯狀態，所述第二被封裝元件呈封裝狀態且具有外露的第二電極結構；In order to solve the above technical problems, the present application adopts the following technical solution: a semiconductor package structure, including: a substrate, at least one first packaged component, at least one second packaged component, a rewiring layer and a passivation layer, the substrate There are at least one first groove and at least one second groove, the first packaged components are fixed in the first groove in one-to-one correspondence, and the second packaged components are fixed in one-to-one correspondence In the second groove, the first packaged component is in a bare core state, and the second packaged component is in a packaged state and has an exposed second electrode structure;

所述第一被封裝元件的有源表面背向所述襯底，所述第一被封裝元件與其所處第一凹槽之間由絕緣材料隔開，所述第二被封裝元件與其所處第二凹槽之間由絕緣材料隔開，各所述第一被封裝元件均具有位於其有源表面上的第一焊盤，全部所述第一焊盤背向所述襯底的表面以及全部第二電極結構背向所述襯底的表面平齊；The active surface of the first packaged component faces away from the substrate, the first packaged component is separated from the first groove where it is located by an insulating material, and the second packaged component is separated from the first groove where it is located. The second grooves are separated by an insulating material, each of the first packaged components has a first pad located on its active surface, all of the first pads face away from the surface of the substrate, and all second electrode structures are flush with the surface facing away from the substrate;

所述重佈線層位於所述第一被封裝元件和所述第二被封裝元件背向所述襯底一側，所述重佈線層的第一面上形成有多個第二焊盤，所述重佈線層的與所述第一面相對的第二面上形成有多個第三焊盤，所述第一焊盤與部分第二焊盤一一對應地電接觸，所述第二電極結構與其餘第二焊盤一一對應地電接觸，所述重佈線層還具有電連接第二焊盤和第三焊盤的走線、以及電連接第二焊盤和第二電極結構的走線；The redistribution layer is located on the side of the first packaged component and the second packaged component facing away from the substrate, and a plurality of second pads are formed on the first surface of the redistribution layer, so A plurality of third pads are formed on the second surface of the redistribution layer opposite to the first surface, the first pads are in electrical contact with part of the second pads in one-to-one correspondence, and the second electrode The structure is in one-to-one electrical contact with the remaining second pads, and the redistribution layer also has a trace electrically connecting the second pad and the third pad, and a trace electrically connecting the second pad and the second electrode structure. Wire;

所述鈍化層位於所述重佈線層背向所述襯底一側；The passivation layer is located on the side of the redistribution layer facing away from the substrate;

其中，所述襯底由半導體材料或絕緣材料形成，所述襯底與所述第一被封裝元件內的半導體材料的熱膨脹係數相同或相近，所述重佈線層由晶圓製造工藝形成。Wherein, the substrate is formed of a semiconductor material or an insulating material, the thermal expansion coefficient of the substrate is the same or similar to that of the semiconductor material in the first packaged component, and the rewiring layer is formed by a wafer manufacturing process.

為解決上述技術問題，本申請採用如下技術方案：一種半導體封裝方法，包括：In order to solve the above technical problems, this application adopts the following technical solution: a semiconductor packaging method, comprising:

在襯底上形成至少一個第一凹槽和至少一個第二凹槽；forming at least one first groove and at least one second groove on the substrate;

將至少一個第一被封裝元件一一對應地固定在所述第一凹槽內，將至少一個第二被封裝元件一一對應地固定在所述第二凹槽內，其中，所述第一被封裝元件呈裸芯狀態，所述第二被封裝元件呈封裝狀態且具有外露的第二電極結構，所述第一被封裝元件的有源表面背向所述襯底，所述第一被封裝元件與其所處第一凹槽之間由絕緣材料隔開，所述第二被封裝元件與其所處第二凹槽之間由絕緣材料隔開，各所述第一被封裝元件均具有位於其有源表面上的第一焊盤，全部所述第一焊盤以及全部第二電極結構的背向所述襯底的表面平齊；fixing at least one first packaged component in the first groove in a one-to-one correspondence, and fixing at least one second packaged component in the second groove in a one-to-one correspondence, wherein the first The packaged component is in a bare core state, the second packaged component is in a packaged state and has an exposed second electrode structure, the active surface of the first packaged component faces away from the substrate, and the first packaged component The packaging component is separated from the first groove where it is located by an insulating material, and the second packaged component is separated from the second groove where it is located by an insulating material. Each of the first packaged components has a The first pad on its active surface, the surfaces of all the first pads and all the second electrode structures facing away from the substrate are flush;

形成曝露所述第一焊盤以及所述第二電極結構的平整表面；forming a flat surface exposing the first pad and the second electrode structure;

採用晶圓製作工藝形成重佈線層，所述重佈線層的第一面上形成有多個第二焊盤，所述重佈線層的與所述第一面相對的第二面上形成有多個第三焊盤，所述第一焊盤與部分第二焊盤一一對應地電接觸，所述第二電極結構與其餘第二焊盤一一對應地電接觸，所述重佈線層具有電連接第二焊盤和第三焊盤的走線、以及電連接第二焊盤和第二電極結構的走線；A redistribution layer is formed by using a wafer manufacturing process, a plurality of second pads are formed on the first surface of the redistribution layer, and multiple pads are formed on a second surface of the redistribution layer opposite to the first surface. a third pad, the first pad is in one-to-one electrical contact with part of the second pads, the second electrode structure is in one-to-one electrical contact with the rest of the second pads, and the redistribution layer has a wiring electrically connecting the second pad and the third pad, and a wiring electrically connecting the second pad and the second electrode structure;

形成鈍化層；form a passivation layer;

其中，所述襯底由半導體材料或絕緣材料形成，所述襯底與所述第一被封裝元件內的半導體材料的熱膨脹係數相同或相近。Wherein, the substrate is formed of a semiconductor material or an insulating material, and the coefficient of thermal expansion of the substrate is the same or similar to that of the semiconductor material in the first packaged component.

為解決上述技術問題，本申請採用如下技術方案：一種半導體器件，包括：前述的半導體封裝結構。In order to solve the above technical problems, the present application adopts the following technical solution: a semiconductor device, comprising: the aforementioned semiconductor packaging structure.

為解決上述技術問題，本申請採用如下技術方案：一種電子產品，包括：前述的半導體器件。In order to solve the above technical problems, the present application adopts the following technical solution: an electronic product, comprising: the aforementioned semiconductor device.

與現有技術相比，本申請的有益效果為：Compared with the prior art, the beneficial effects of the present application are:

由於第一被封裝元件內的半導體材料和襯底的熱膨脹係數相等或接近（例如二者由相同的半導體材料構成），所述重佈線層內至少一種絕緣材料與所述第一被封裝元件內的絕緣材料的熱膨脹係數相同或相近，封裝完成之後，半導體封裝結構隨溫度變化而產生的翹曲度相對更小，有利於提高半導體器件的良率以及電學和機械上的可靠性。同時，在一些實施例中，半導體襯底比傳統封裝形式的模塑材料散熱性好。Since the thermal expansion coefficients of the semiconductor material in the first packaged component and the substrate are equal or close (for example, both are made of the same semiconductor material), at least one insulating material in the redistribution layer is the same as that in the first packaged component The thermal expansion coefficient of the insulating material is the same or similar. After the package is completed, the warpage of the semiconductor package structure with temperature changes is relatively small, which is conducive to improving the yield rate and electrical and mechanical reliability of semiconductor devices. Also, in some embodiments, the semiconductor substrate dissipates heat better than conventional packaging molding materials.

進一步，由於重佈線層通過現有的半導體製造工藝（FAB工藝、晶圓製造工藝）形成重佈線層，不僅製造工藝成熟，而且重佈線層內的線寬更細且線距更小，從而使得互連密度更高，半導體封裝結構面積更小。Furthermore, since the redistribution layer is formed through the existing semiconductor manufacturing process (FAB process, wafer manufacturing process), not only the manufacturing process is mature, but also the line width in the redistribution layer is thinner and the line spacing is smaller, so that the interconnection The connection density is higher, and the semiconductor package structure area is smaller.

第一被封裝元件呈裸芯的狀態，第二被封裝元件則是已經封裝完成的元件。本申請的半導體封裝結構實現對第一被封裝元件的初次封裝以及對第二被封裝元件的二次封裝，並實現第一被封裝元件與第二被封裝元件之間的互連。這也減少了將兩類被封裝元件進行組裝的工藝步驟。The first packaged component is in the state of a bare core, and the second packaged component is a packaged component. The semiconductor packaging structure of the present application realizes the primary packaging of the first packaged component and the secondary packaging of the second packaged component, and realizes the interconnection between the first packaged component and the second packaged component. This also reduces the process steps for assembling the two types of packaged components.

在本申請中，應理解，諸如“包括”或“具有”等術語旨在指示本說明書中存在所公開的特徵、數位、步驟、行為、部件、部分或其組合的存在，但是並不排除存在一個或多個其他特徵、數位、步驟、行為、部件、部分或其組合存在的可能性。In this application, it should be understood that terms such as "comprising" or "having" are intended to indicate the presence of disclosed features, figures, steps, acts, components, parts or combinations thereof in this specification, but do not exclude the presence of Possibility that one or more other features, figures, steps, acts, parts, parts or combinations thereof exist.

另外還需要說明的是，在不衝突的情況下，本申請中的實施例及實施例中的特徵可以相互組合。下面將參考附圖並結合實施例來詳細說明本申請。In addition, it should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and embodiments.

本申請的實施例提供一種半導體封裝結構，包括：襯底、至少一個第一被封裝元件、至少一個第二被封裝元件、重佈線層和鈍化層，襯底上開設有至少一個第一凹槽和至少一個第二凹槽，第一被封裝元件一一對應地固定在第一凹槽內，第二被封裝元件一一對應地固定在第二凹槽內，第一被封裝元件呈裸芯狀態，第二被封裝元件呈封裝狀態且具有外露的第二電極結構；第一被封裝元件的有源表面背向襯底，第一被封裝元件與其所處第一凹槽之間由絕緣材料隔開，第二被封裝元件與其所處第二凹槽之間由絕緣材料隔開，各第一被封裝元件均具有位於其有源表面上的第一焊盤，全部第一焊盤背向所述襯底的表面以及全部第二電極結構背向襯底的表面平齊；重佈線層位於第一被封裝元件和第二被封裝元件背向襯底一側，重佈線層的第一面上形成有多個第二焊盤，重佈線層的與第一面相對的第二面上形成有多個第三焊盤，第一焊盤與部分第二焊盤一一對應地電接觸，第二電極結構與其餘第二焊盤一一對應地電接觸，所述重佈線層還具有電連接第二焊盤和第三焊盤的走線、以及電連接第二焊盤和第二電極結構的走線；鈍化層位於重佈線層背向襯底一側；其中，所述襯底由半導體材料或絕緣材料形成，所述襯底與所述第一被封裝元件內的半導體材料的熱膨脹係數相同或相近，重佈線層由晶圓製造工藝形成。An embodiment of the present application provides a semiconductor packaging structure, including: a substrate, at least one first packaged component, at least one second packaged component, a rewiring layer and a passivation layer, and at least one first groove is opened on the substrate and at least one second groove, the first packaged components are fixed in the first groove one by one, the second packaged components are fixed in the second groove one by one, the first packaged component is a bare core state, the second packaged component is in a packaged state and has an exposed second electrode structure; the active surface of the first packaged component faces away from the substrate, and the first packaged component and the first groove where it is located are covered by an insulating material Separated, the second packaged component and the second groove where it is located are separated by an insulating material, each first packaged component has a first pad located on its active surface, and all the first pads face away from the The surface of the substrate and the surface of all second electrode structures facing away from the substrate are flush; the redistribution layer is located on the side of the first packaged component and the second packaged component facing away from the substrate, and the first surface of the redistribution layer is A plurality of second pads are formed on the redistribution layer, and a plurality of third pads are formed on the second surface of the redistribution layer opposite to the first surface. The first pads are in one-to-one electrical contact with part of the second pads. The second electrode structure is in one-to-one electrical contact with the rest of the second pads, and the redistribution layer also has a wiring that electrically connects the second pad and the third pad, and electrically connects the second pad and the second electrode. The routing of the structure; the passivation layer is located on the side of the rewiring layer facing away from the substrate; wherein, the substrate is formed of semiconductor material or insulating material, and the thermal expansion of the substrate and the semiconductor material in the first packaged component The coefficients are the same or similar, and the redistribution layer is formed by the wafer manufacturing process.

例如，所述襯底內的半導體材料與所述第一被封裝元件內的半導體材料相同。For example, the semiconductor material in the substrate is the same as the semiconductor material in the first packaged component.

本申請中，兩種材料的熱膨脹係數相近，指的是二者的差與二者中絕對值較小一者的比值的絕對值小於9。In the present application, the coefficients of thermal expansion of the two materials are similar, which means that the absolute value of the ratio of the difference between the two to the one with the smaller absolute value of the two is less than 9.

例如，所述被封裝元件內的半導體材料為矽或砷化鎵或氮化鎵或碳化矽，並且所述襯底的材料為玻璃材料。這些材料的熱膨脹係數在同一數量級。For example, the semiconductor material in the packaged component is silicon, gallium arsenide, gallium nitride or silicon carbide, and the material of the substrate is glass material. The thermal expansion coefficients of these materials are of the same order of magnitude.

這些實施例中，第一被封裝元件是放置在襯底上形成的第一凹槽內的，第二被封裝元件是放置在襯底上形成的第二凹槽內的，第一被封裝元件和第二被封裝元件上方是被重佈線層所覆蓋的。襯底、第一被封裝元件內的基礎材料都是相同的半導體材料。In these embodiments, the first packaged component is placed in the first groove formed on the substrate, the second packaged component is placed in the second groove formed on the substrate, and the first packaged component and above the second packaged component are covered by a redistribution layer. The substrate, the base material within the first packaged component are all the same semiconductor material.

第一被封裝元件呈裸芯的狀態，第二被封裝元件則是已經封裝完成的元件。本申請的半導體封裝結構實現對第一被封裝元件的初次封裝以及對第二被封裝元件的二次封裝，並實現第一被封裝元件與第二被封裝元件之間的互連。這避免了將兩個被封裝元件進行組裝的步驟，也能實現更大密度的互連。The first packaged component is in the state of a bare core, and the second packaged component is a packaged component. The semiconductor packaging structure of the present application realizes the primary packaging of the first packaged component and the secondary packaging of the second packaged component, and realizes the interconnection between the first packaged component and the second packaged component. This avoids the step of assembling the two packaged components and also enables higher density interconnections.

第二被封裝元件的封裝形式例如是貼片式封裝、陶瓷封裝等。第二被封裝元件例如是貼片電阻、片式多層陶瓷電容器等，也可以是其他已經處於封裝狀態的元件。The package form of the second packaged component is, for example, a patch package, a ceramic package, and the like. The second packaged component is, for example, a chip resistor, a chip multilayer ceramic capacitor, etc., and may also be other components already in a packaged state.

本申請對同一個第二被封裝元件的各第二電極結構的形狀和位置不做限定，只要這些第二電極結構具有平齊的表面即可，從而能夠與第一被封裝元件的第一焊盤實現共面。The present application does not limit the shape and position of the second electrode structures of the same second packaged component, as long as these second electrode structures have a flat surface, so as to be able to be welded to the first soldered structure of the first packaged component. The disk achieves coplanarity.

本申請中“相同的半導體材料”指的是它們的化學成分是相同的，例如都是矽材料形成的，或者都是由砷化鎵材料形成的。但並不限定這些半導體材料的純度或者密度或者結晶狀態等完全一致。"Same semiconductor materials" in this application means that their chemical compositions are the same, for example, both are formed of silicon material, or both are formed of gallium arsenide material. However, it is not limited that the purity, density, or crystalline state of these semiconductor materials are completely consistent.

由於第一被封裝元件和襯底二者的熱膨脹係數相同或相近，封裝完成之後，半導體器件隨溫度變化而產生的翹曲度相對更小，有利於提高半導體封裝結構的良率以及電學和機械上的可靠性。同時，在一些實施例中，半導體襯底比傳統封裝形式的模塑材料散熱性好。Since the thermal expansion coefficients of the first packaged component and the substrate are the same or similar, after the package is completed, the warpage of the semiconductor device due to temperature changes is relatively small, which is conducive to improving the yield rate of the semiconductor package structure and the electrical and mechanical properties. on the reliability. Also, in some embodiments, the semiconductor substrate dissipates heat better than conventional packaging molding materials.

進一步，該半導體封裝結構實現對第二被封裝元件的二次封裝，以及第一被封裝元件與第二被封裝元件之間的互連，從而使得半導體封裝結果具有更高的集成度，同時省去了將兩類被封裝元件進行組裝的步驟。Further, the semiconductor packaging structure realizes the secondary packaging of the second packaged component, and the interconnection between the first packaged component and the second packaged component, so that the semiconductor package has a higher integration degree and saves The step of assembling the two types of packaged components is gone.

進一步，由於重佈線層能夠通過現有的半導體製造工藝（FAB工藝、晶圓製造工藝）形成。不僅形成重佈線的製造工藝成熟，而且重佈線層內的線寬更細且線距更小，從而使得互連密度更高，半導體封裝結構面積更小。Further, since the redistribution layer can be formed through the existing semiconductor manufacturing process (FAB process, wafer manufacturing process). Not only is the manufacturing process for forming rewiring mature, but also the line width in the rewiring layer is thinner and the line spacing is smaller, so that the interconnection density is higher and the semiconductor package structure area is smaller.

例如，所述重佈線層內的走線由包括沉積、光刻和刻蝕的晶圓製造工藝形成，所述重佈線層內的絕緣材料由包括沉積的晶圓製造工藝形成。For example, the wiring in the redistribution layer is formed by a wafer manufacturing process including deposition, photolithography and etching, and the insulating material in the redistribution layer is formed by a wafer manufacturing process including deposition.

在一些實施例中，所述第一被封裝元件內的絕緣材料以及所述重佈線層內的絕緣材料的熱膨脹係數相同或相近。In some embodiments, the thermal expansion coefficients of the insulating material in the first packaged component and the insulating material in the redistribution layer are the same or similar.

例如，所述重佈線層內的絕緣材料和所述第一被封裝元件內的絕緣材料均包含二氧化矽。For example, the insulating material in the redistribution layer and the insulating material in the first packaged component both contain silicon dioxide.

重佈線層與第一被封裝元件的熱膨脹特性更為接近，這進一步有利於防止半導體封裝結構的翹曲。The thermal expansion characteristics of the redistribution layer and the first packaged component are closer, which is further beneficial to prevent warping of the semiconductor package structure.

當重佈線層與第一被封裝元件均包含相同的絕緣材料，形成被第一封裝元件的工藝場所也可以用於形成重佈線層。這進一步降低製作工藝的複雜度。When the redistribution layer and the first packaged component both contain the same insulating material, the process site for forming the first packaged component can also be used to form the redistribution layer. This further reduces the complexity of the manufacturing process.

在一些實施例中，第一被封裝元件的數量為多個且厚度相等，各第一凹槽的深度相等。In some embodiments, the number of the first packaged components is multiple and the thickness is equal, and the depth of each first groove is equal.

參考圖1a和圖3a，第一被封裝元件22a和23a的厚度相等，二者所處第一凹槽H1的深度相等。Referring to FIG. 1a and FIG. 3a, the thicknesses of the first packaged components 22a and 23a are equal, and the depths of the first groove H1 where they are located are equal.

當然，第一被封裝元件22a和第一被封裝元件23a可以是相同型號的被封裝元件，也可以是不同型號的被封裝元件。由於第一被封裝元件21a和第一被封裝元件22a的厚度相等，各第一凹槽10可採用相同的開槽（比如刻蝕）工藝形成。Certainly, the first packaged component 22 a and the first packaged component 23 a may be packaged components of the same model, or packaged components of different models. Since the thicknesses of the first packaged component 21 a and the first packaged component 22 a are equal, each first groove 10 can be formed by using the same groove (such as etching) process.

如這些第一被封裝元件最初的厚度是不一致的，可以通過減薄的工藝使得它們的厚度相等。If the initial thicknesses of these first packaged components are inconsistent, they can be made equal through a thinning process.

當然，即使這些第一被封裝元件22a、23a的最初的厚度是相等的，也可通過減薄的工藝使得它們的厚度減小並相等。如此，可以減少在襯底1中開設凹槽10的槽深。Of course, even if the initial thicknesses of the first packaged components 22a, 23a are equal, their thicknesses can be reduced and equalized through a thinning process. In this way, the groove depth of the groove 10 in the substrate 1 can be reduced.

由於第二被封裝元件是處於封裝狀態，其外觀尺寸相對固定。故第二凹槽的深度是相對固定的，其可調整的餘量相對較小。故優選相對薄的第二被封裝元件加入至該半導體封裝結構。Since the second packaged component is in a packaged state, its external dimensions are relatively fixed. Therefore, the depth of the second groove is relatively fixed, and its adjustable margin is relatively small. Therefore, a relatively thin second packaged component is preferably added to the semiconductor package structure.

在一些實施例中，第一被封裝元件的數量為多個，且至少兩個第一被封裝元件的厚度不相等，其中，至少兩個第一凹槽的深度不同，以使各第一被封裝元件的第一焊盤的上表面平齊。In some embodiments, there are multiple first packaged components, and the thicknesses of at least two first packaged components are not equal, wherein the depths of at least two first grooves are different, so that each first packaged component The upper surface of the first pad of the packaged component is even.

參考圖1b和圖4a，第一被封裝元件22a和第一被封裝元件23a的厚度不相等，二者所處第一凹槽H1的深度也不相等。第一被封裝元件22a更厚，相應地，其所處的第一凹槽H1的深度更深。Referring to FIG. 1 b and FIG. 4 a , the thicknesses of the first packaged component 22 a and the first packaged component 23 a are not equal, and the depths of the first groove H1 where the two are located are also not equal. The first packaged component 22a is thicker, and correspondingly, the depth of the first groove H1 where it is located is deeper.

可以通過控制開槽工藝（比如分步刻蝕或二次刻蝕）形成不同深度的第一凹槽H1以及第二凹槽H2。The first groove H1 and the second groove H2 with different depths can be formed by controlling the grooving process (such as stepwise etching or secondary etching).

在一些實施例中，鈍化層覆蓋重佈線層上方的第三焊盤後，該半導體封裝結構即可作為獨立出售的產品。In some embodiments, after the passivation layer covers the third pad above the redistribution layer, the semiconductor package structure can be used as an independently sold product.

在一些實施例中，參考圖1a和圖1b，半導體封裝結構還包括位於鈍化層4背向襯底1一側的第一電極結構5，鈍化層4上與第三焊盤32相對的區域開設有過孔，第一電極結構5與第三焊盤32一一對應，第一電極結構5通過過孔與對應第三焊盤32電連接。In some embodiments, referring to FIG. 1a and FIG. 1b, the semiconductor package structure further includes a first electrode structure 5 located on the side of the passivation layer 4 facing away from the substrate 1, and an area on the passivation layer 4 opposite to the third pad 32 is opened. There are via holes, and the first electrode structures 5 correspond to the third pads 32 one by one, and the first electrode structures 5 are electrically connected to the corresponding third pads 32 through the via holes.

具體地，第一電極結構5例如包含覆蓋第三焊盤的凸點下金屬（UBM），以及位於凸點下金屬上方的焊錫球。當然，第一電極結構也可以是形成在第三焊盤上方的焊盤（Pad）。Specifically, the first electrode structure 5 includes, for example, an under bump metallurgy (UBM) covering the third pad, and solder balls located above the UBM. Certainly, the first electrode structure may also be a pad (Pad) formed above the third pad.

在一些實施例中，第一被封裝元件與所處第一凹槽的槽底之間由絕緣黏膠層隔開，第二被封裝元件與所處第二凹槽的槽底之間由絕緣黏膠層隔開。即由絕緣黏膠層固定第一被封裝元件和第二被封裝元件，並實現第一被封裝元件與第一凹槽槽底之間的絕緣，以及實現第二被封裝元件與第二凹槽槽底之間的絕緣。In some embodiments, the first packaged component is separated from the bottom of the first groove by an insulating adhesive layer, and the second packaged component is separated from the bottom of the second groove by an insulating layer. Adhesive layer separated. That is, the first packaged component and the second packaged component are fixed by the insulating adhesive layer, and the insulation between the first packaged component and the bottom of the first groove is realized, and the second packaged component and the second groove are realized. Insulation between tank bottoms.

在一些實施例中，第一被封裝元件與所處第一凹槽的側面之間由固化的樹脂材料（例如是環氧樹脂）或無機絕緣材料隔開；第二被封裝元件與所處第二凹槽的側面之間由固化的樹脂材料（例如是環氧樹脂）或無機絕緣材料隔開。即可向各被封裝元件與其所處凹槽之間的間隙填充並固化樹脂材料，或者向該間隙沉積無機絕緣材料（例如是二氧化矽）。In some embodiments, the first packaged component is separated from the side of the first groove by cured resin material (such as epoxy resin) or inorganic insulating material; the second packaged component is separated from the side of the first groove. The side surfaces of the two grooves are separated by cured resin material (such as epoxy resin) or inorganic insulating material. That is, filling and curing the resin material into the gap between each packaged component and the groove where it is located, or depositing an inorganic insulating material (such as silicon dioxide) into the gap.

重佈線層內包含至少一層金屬走線、以及包含連接不同層金屬走線（如果有多層金屬走線）的過孔、連接金屬走線與第二焊盤的過孔、連接金屬走線與第三焊盤的過孔。重佈線層內的走線可以實現第二焊盤與第三焊盤的互連，第二焊盤與第二電極結構的互連，當然，還可以實現第二焊盤與第二焊盤的互連。The redistribution layer contains at least one layer of metal traces, and includes vias connecting different layers of metal traces (if there are multiple layers of metal traces), vias connecting metal traces and the second pad, and connecting metal traces and the second pad. Three pad vias. The wiring in the redistribution layer can realize the interconnection between the second pad and the third pad, the interconnection between the second pad and the second electrode structure, and of course, the connection between the second pad and the second pad can also be realized. interconnection.

參考圖2，本申請的實施例還提供一種半導體封裝方法。該封裝方法能夠製造得到前述實施例所提供的半導體封裝結構。該製造方法包括以下步驟。Referring to FIG. 2 , the embodiment of the present application also provides a semiconductor packaging method. This packaging method can manufacture the semiconductor packaging structure provided by the foregoing embodiments. The manufacturing method includes the following steps.

步驟1000、在襯底上形成至少一個第一凹槽和至少一個第二凹槽；Step 1000, forming at least one first groove and at least one second groove on the substrate;

步驟1001、將至少一個第一被封裝元件一一對應地固定在第一凹槽內，將至少一個第二被封裝元件一一對應地固定在第二凹槽內，其中，第一被封裝元件呈裸芯狀態，第二被封裝元件呈封裝狀態且具有外露的第二電極結構，第一被封裝元件的有源表面背向襯底，第一被封裝元件與其所處第一凹槽之間由絕緣材料隔開，第二被封裝元件與其所處第二凹槽之間由絕緣材料隔開，各第一被封裝元件均具有位於其有源表面上的第一焊盤，全部第一焊盤以及全部第二電極結構的背向襯底的表面平齊；Step 1001, fixing at least one first packaged component in the first groove in one-to-one correspondence, and fixing at least one second packaged component in the second groove in one-to-one correspondence, wherein the first packaged component It is in a bare core state, the second packaged component is in a packaged state and has an exposed second electrode structure, the active surface of the first packaged component faces away from the substrate, and the first packaged component is located between the first groove Separated by an insulating material, the second packaged component and the second groove where it is located are separated by an insulating material, each first packaged component has a first pad located on its active surface, and all the first pads the surface of the disk and of all second electrode structures facing away from the substrate is flush;

步驟1002、形成曝露第一焊盤以及第二電極結構的平整表面；Step 1002, forming a flat surface exposing the first pad and the second electrode structure;

步驟1003、採用晶圓製作工藝形成重佈線層，重佈線層的第一面上形成有多個第二焊盤，重佈線層的與第一面相對的第二面上形成有多個第三焊盤，第一焊盤與部分第二焊盤一一對應地電接觸，第二電極結構與其餘第二焊盤一一對應地電接觸，重佈線層具有電連接第二焊盤和第三焊盤的走線、以及電連接第二焊盤和第二電極結構的走線；Step 1003: A redistribution layer is formed using a wafer manufacturing process, a plurality of second pads are formed on the first surface of the redistribution layer, and a plurality of third pads are formed on a second surface of the redistribution layer opposite to the first surface. The first pad is in one-to-one electrical contact with part of the second pads, the second electrode structure is in one-to-one electrical contact with the rest of the second pads, and the redistribution layer is electrically connected to the second pad and the third pad. The wiring of the pad, and the wiring electrically connecting the second pad and the second electrode structure;

步驟1004、形成鈍化層；Step 1004, forming a passivation layer;

其中，所述襯底由半導體材料或絕緣材料形成，所述襯底與所述第一被封裝元件內的半導體材料的熱膨脹係數相同或相近。Wherein, the substrate is formed of a semiconductor material or an insulating material, and the coefficient of thermal expansion of the substrate is the same or similar to that of the semiconductor material in the first packaged component.

例如，所述襯底內的半導體材料與所述第一被封裝元件內的半導體材料相同。For example, the semiconductor material in the substrate is the same as the semiconductor material in the first packaged component.

又例如，所述第一被封裝元件內的半導體材料為矽或砷化鎵或氮化鎵或碳化矽，並且所述襯底的材料為玻璃材料。For another example, the semiconductor material in the first packaged component is silicon or gallium arsenide or gallium nitride or silicon carbide, and the material of the substrate is glass material.

由於第一被封裝元件內半導體材料和襯底二者的熱膨脹係數相同或相近，封裝完成之後，半導體封裝結構隨溫度變化而產生的翹曲度相對更小，有利於提高半導體封裝結構的良率以及電學和機械上的可靠性。Since the thermal expansion coefficients of the semiconductor material and the substrate in the first packaged component are the same or similar, after the packaging is completed, the warpage of the semiconductor package structure due to temperature changes is relatively smaller, which is conducive to improving the yield of the semiconductor package structure and electrical and mechanical reliability.

相對而言，半導體材料以及工程耐熱玻璃的熱傳導係數也是要高於傳統的塑封材料的熱傳導係數的，半導體封裝結構的散熱性也會更好。Relatively speaking, the thermal conductivity of semiconductor materials and engineering heat-resistant glass is also higher than that of traditional plastic packaging materials, and the heat dissipation of semiconductor packaging structures will also be better.

進一步，由於重佈線層通過半導體製造工藝（FAB工藝）形成。例如可採用沉積、光刻、刻蝕等工藝形成重佈線層內的走線和電極，以及通過沉積的工藝形成絕緣材料層。這不僅製造工藝成熟，而且重佈線層內的線寬更細且線距更小，從而使得互連密度更高，半導體封裝結構面積更小。Further, since the redistribution layer is formed through a semiconductor manufacturing process (FAB process). For example, processes such as deposition, photolithography, and etching can be used to form wires and electrodes in the rewiring layer, and an insulating material layer can be formed through a deposition process. Not only is the manufacturing process mature, but also the line width in the redistribution layer is thinner and the line spacing is smaller, so that the interconnection density is higher and the semiconductor package structure area is smaller.

例如，採用包括沉積、光刻和刻蝕的晶圓製造工藝形成所述重佈線層內的走線，採用包括沉積的晶圓製造工藝形成所述重佈線層內的絕緣材料。For example, a wafer manufacturing process including deposition, photolithography and etching is used to form wiring in the rewiring layer, and a wafer manufacturing process including deposition is used to form insulating materials in the rewiring layer.

在一些實施例中，所述第一被封裝元件內的絕緣材料以及所述重佈線層內的絕緣材料的熱膨脹係數相同或相近。In some embodiments, the thermal expansion coefficients of the insulating material in the first packaged component and the insulating material in the redistribution layer are the same or similar.

例如，所述重佈線層內的絕緣材料和所述第一被封裝元件內的絕緣材料均包含二氧化矽。For example, the insulating material in the redistribution layer and the insulating material in the first packaged component both contain silicon dioxide.

由於重佈線層與第一被封裝元件均包含熱膨脹係數相同或者相近的絕緣材料，重佈線層與第一被封裝元件的熱膨脹特性也更為接近，這進一步有利於防止半導體封裝結構的翹曲。Since both the redistribution layer and the first packaged component contain insulating materials with the same or similar thermal expansion coefficients, the thermal expansion characteristics of the redistribution layer and the first packaged component are also closer, which is further beneficial to prevent warping of the semiconductor package structure.

在一些實施例中，該封裝方法還包括：In some embodiments, the packaging method also includes:

步驟1005、在鈍化層上形成至少一個過孔，過孔與第三焊盤一一對應，過孔曝露對應的第三焊盤；Step 1005, forming at least one via hole on the passivation layer, the via hole corresponds to the third pad, and the via hole exposes the corresponding third pad;

步驟1006、在第三焊盤上形成與其電接觸的第一電極結構。Step 1006 , forming a first electrode structure in electrical contact with the third pad on the third pad.

在一些實施例中，第一被封裝元件的數量為多個，其所處第一凹槽的深度相同，該封裝方法還包括：對至少部分第一被封裝元件進行減薄，以使各第一被封裝元件的厚度相等。In some embodiments, there are multiple first packaged components, and the depths of the first grooves are the same. The packaging method further includes: thinning at least part of the first packaged components, so that each of the first packaged components A packaged component has equal thickness.

在一些實施例中，第一被封裝元件和第二被封裝元件中至少兩個被封裝元件的厚度不相等，在襯底上形成第一凹槽和第二凹槽時，至少兩個凹槽的深度是不等的，以使各第一被封裝元件的第一焊盤的上表面以及各第二電極結構的上表面平齊。In some embodiments, the thicknesses of at least two packaged components among the first packaged component and the second packaged component are not equal, and when the first groove and the second groove are formed on the substrate, at least two grooves The depths are different, so that the upper surface of the first pad of each first packaged component and the upper surface of each second electrode structure are flush.

在一些實施例中，將至少一個第一被封裝元件一一對應地固定在第一凹槽內，包括：In some embodiments, fixing at least one first packaged component in the first groove in a one-to-one correspondence includes:

在第一凹槽的槽底所形成絕緣黏膠層；an insulating adhesive layer is formed on the groove bottom of the first groove;

將第一被封裝元件黏貼在絕緣黏膠上，其中，第一被封裝元件與所處第一凹槽的側面之間留有空隙；Pasting the first packaged component on the insulating adhesive, wherein there is a gap between the first packaged component and the side of the first groove;

向第一被封裝元件與對應的第一凹槽的側面之間填充絕緣材料。An insulating material is filled between the first packaged component and the side of the corresponding first groove.

在一些實施例中，向第一被封裝元件與對應的第一凹槽側面之間填充絕緣材料，包括：In some embodiments, filling an insulating material between the first packaged component and the corresponding side of the first groove includes:

向第一被封裝元件與對應的第一凹槽側面之間填充並固化樹脂材料，或向第一被封裝元件與對應的第一凹槽側面之間的空隙沉積無機氧化物絕緣材料。Filling and curing the resin material between the first packaged component and the corresponding side of the first groove, or depositing an inorganic oxide insulating material into the gap between the first packaged component and the corresponding side of the first groove.

在一些實施例中，將至少一個第二被封裝元件一一對應地固定在第二凹槽內，包括：In some embodiments, fixing at least one second packaged component in the second groove in a one-to-one correspondence includes:

在第二凹槽的槽底所形成絕緣黏膠層；an insulating adhesive layer is formed on the groove bottom of the second groove;

將第二被封裝元件黏貼在絕緣黏膠上，其中，第二被封裝元件與所處第二凹槽的側面之間留有空隙；Pasting the second packaged component on the insulating adhesive, wherein there is a gap between the second packaged component and the side of the second groove;

向第二被封裝元件與對應的第二凹槽的側面之間填充絕緣材料。An insulating material is filled between the second packaged component and the side of the corresponding second groove.

在一些實施例中，向第二被封裝元件與對應的第二凹槽側面之間填充絕緣材料，包括：In some embodiments, filling an insulating material between the second packaged component and the corresponding side of the second groove includes:

向第二被封裝元件與對應的第二凹槽側面之間填充並固化樹脂材料，或向第二被封裝元件與對應的第二凹槽側面之間的空隙沉積無機氧化物絕緣材料。Filling and curing the resin material between the second packaged component and the corresponding side of the second groove, or depositing an inorganic oxide insulating material into the gap between the second packaged component and the corresponding side of the second groove.

在一些實施例中，形成曝露第一焊盤以及第二電極結構的平整表面，包括：通過磨削工藝去除高出第一焊盤以及第二電極結構的絕緣材料以及襯底材料，隨後進行表面處理。In some embodiments, forming a flat surface that exposes the first pad and the second electrode structure includes: removing the insulating material and the substrate material that are higher than the first pad and the second electrode structure through a grinding process, and then surface deal with.

在一些實施例中，該方法還包括：在所述鈍化層上形成多個過孔，所述過孔與所述第三焊盤一一對應，所述過孔曝露對應的第三焊盤；在所述第三焊盤上形成與其電接觸的第一電極結構。In some embodiments, the method further includes: forming a plurality of via holes on the passivation layer, the via holes corresponding to the third pads one by one, and the via holes exposing the corresponding third pads; A first electrode structure in electrical contact with the third pad is formed on the third pad.

在一些實施例中，襯底的面積較大，其實可以形成大量的第一凹槽以及第二凹槽。該製造還包括：通過切割工藝得到多個半導體封裝結構，其中，至少一個半導體封裝結構包含：至少一個第一被封裝元件、至少一個第二被封裝元件、所含第一被封裝元件所處的第一凹槽、所含第二被封裝元件所處的第二凹槽、與所含第一被封裝元件和所含第二被封裝元件電連接的重佈線層、以及所含重佈線層上方的鈍化層。In some embodiments, the area of the substrate is relatively large, so a large number of first grooves and second grooves can be formed. The manufacturing also includes: obtaining a plurality of semiconductor package structures through a dicing process, wherein at least one semiconductor package structure includes: at least one first packaged component, at least one second packaged component, and the The first groove, the second groove where the second packaged component is located, the redistribution layer electrically connected to the first packaged component and the second packaged component, and the above redistribution layer passivation layer.

在一些實施例中，所述第二被封裝元件為貼片式封裝或為陶瓷封裝。In some embodiments, the second packaged component is a chip package or a ceramic package.

在一些實施例中，參考圖3a至圖3f以及圖1a，半導體封裝方法的具體實現過程如下。In some embodiments, referring to FIG. 3a to FIG. 3f and FIG. 1a, the specific implementation process of the semiconductor packaging method is as follows.

第一步，參考圖3a，採用刻蝕的工藝在襯底1上形成第一凹槽H1以及第二凹槽H2，多個第一凹槽H1的深度相等但與第二凹槽H2的深度不等。In the first step, referring to FIG. 3a, a first groove H1 and a second groove H2 are formed on the substrate 1 by an etching process. wait.

第二步，參考圖3b，在第一凹槽H1和第二凹槽H2的槽底形成絕緣黏膠層111。The second step, referring to FIG. 3 b , is to form an insulating adhesive layer 111 at the bottom of the first groove H1 and the second groove H2 .

第三步，參考圖3b，將第一被封裝元件22a、23a分別放置一個第一凹槽H1內，將被第二被封裝元件21a放在第二凹槽H2內，並且第一被封裝元件22a、23a和第二被封裝元件21a均黏貼在絕緣黏膠111上，其中，第一被封裝元件22a的第一焊盤221a和第一被封裝元件23a的第一焊盤231a朝上，第一被封裝元件22a和第一被封裝元件23a的厚度相等，各第一焊盤221a、231a以及第二電極結構211a的上表面平齊。第一被封裝元件22a、23a和第二被封裝元件21a均與所處凹槽H1、H2的側壁之間留有間距。In the third step, referring to FIG. 3b, the first packaged components 22a, 23a are respectively placed in a first groove H1, the second packaged component 21a is placed in the second groove H2, and the first packaged component 22a, 23a, and the second packaged component 21a are pasted on the insulating adhesive 111, wherein the first pad 221a of the first packaged component 22a and the first pad 231a of the first packaged component 23a face upward, and the first pad 231a of the first packaged component 23a faces upward. The first packaged component 22a and the first packaged component 23a have the same thickness, and the upper surfaces of the first pads 221a, 231a and the second electrode structure 211a are flush. Spaces are left between the first packaged components 22a, 23a and the second packaged components 21a and the sidewalls of the grooves H1, H2 where they are located.

第四步，參考圖3c，向第一凹槽H1以及第二凹槽H2內填充並固化絕緣材料112。例如是將液態狀的環氧樹脂滴入第一凹槽H1與第一被封裝元件22a、23a之間的縫隙，將液態狀的環氧樹脂滴入第二凹槽H2與第二被封裝元件21a之間的縫隙，並通過加熱固化環氧樹脂。或者向第一凹槽H1與第一被封裝元件22a、23a的縫隙沉積無機絕緣材料（例如是二氧化矽），向第二凹槽H2與第二被封裝元件21a的縫隙沉積無機絕緣材料。The fourth step, referring to FIG. 3 c , is to fill and cure the insulating material 112 into the first groove H1 and the second groove H2 . For example, drop liquid epoxy resin into the gap between the first groove H1 and the first packaged components 22a, 23a, and drop liquid epoxy resin into the gap between the second groove H2 and the second packaged component. 21a, and cure the epoxy by heating. Alternatively, an inorganic insulating material (such as silicon dioxide) is deposited in the gap between the first groove H1 and the first packaged component 22a, 23a, and an inorganic insulating material is deposited in the gap between the second groove H2 and the second packaged component 21a.

第五步，參考圖3d，磨削去除高出第一焊盤221a、231a以及第二電極結構211a的絕緣材料112以及高出第一焊盤221a、231a以及第二電極結構211a的襯底材料，隨後進行諸如化學清洗、拋光等的表面處理工藝，得到曝露第一焊盤221a、231a以及第二電極結構211a的平整表面。The fifth step, referring to FIG. 3d, is grinding to remove the insulating material 112 higher than the first pads 221a, 231a and the second electrode structure 211a and the substrate material higher than the first pads 221a, 231a and the second electrode structure 211a , followed by a surface treatment process such as chemical cleaning, polishing, etc., to obtain a flat surface exposing the first pads 221a, 231a and the second electrode structure 211a.

第六步，參考圖3e，在這個平整表面上形成重佈線層3，重佈線層3的第二焊盤31分別與第一焊盤221a、231a以及第二電極結構211a實現電接觸，重佈線層3的第三焊盤32與第二焊盤31進行互連。The sixth step, referring to FIG. 3e, is to form a rewiring layer 3 on this flat surface, and the second pads 31 of the rewiring layer 3 are respectively in electrical contact with the first pads 221a, 231a and the second electrode structure 211a, and the rewiring The third pad 32 of layer 3 is interconnected with the second pad 31 .

具體地，可通過濺射或電鍍、以及光刻、刻蝕、清洗等的圖形化工藝形成第二焊盤31的圖案，然後通過沉積等FAB工藝形成絕緣材料層（例如是二氧化矽層），再在絕緣材料層形成曝露第二焊盤31的過孔，然後通過濺射或電鍍、圖形化的工藝形成連接第二焊盤31的走線33，之後再沉積形成另一側絕緣材料層；再次形成一層走線33和一層絕緣材料層；隨後在最新得到絕緣材料層中形成曝露下層走線33的過孔，最後再經濺射、電鍍和圖形化的工藝得到第三焊盤32的圖案。Specifically, the pattern of the second pad 31 can be formed by sputtering or electroplating, and patterning processes such as photolithography, etching, and cleaning, and then an insulating material layer (such as a silicon dioxide layer) can be formed by FAB processes such as deposition. , and then form a via hole exposing the second pad 31 in the insulating material layer, then form the wiring 33 connecting the second pad 31 by sputtering or electroplating, and patterning, and then deposit and form the insulating material layer on the other side ; Form a layer of wiring 33 and a layer of insulating material again; then form a via hole exposing the lower layer of wiring 33 in the latest insulating material layer, and finally obtain the third pad 32 through the processes of sputtering, electroplating and patterning pattern.

當然，也可以首先採用構圖工藝形成第二焊盤31的圖案，然後形成絕緣材料層，再在絕緣材料層中形成曝露第二焊盤31的過孔，然後形成第一層走線33的圖案。Of course, it is also possible to first form the pattern of the second pad 31 by using a patterning process, then form an insulating material layer, then form a via hole exposing the second pad 31 in the insulating material layer, and then form the pattern of the first layer of wiring 33 .

本領域技術人員可以依據現有技術製備重佈線層。Those skilled in the art can prepare the redistribution layer according to the prior art.

以上方式中，製作重佈線層3的工藝與製作裸芯的工藝是相同的。該重佈線層中有多層走線33。重佈線層3內的走線的線寬和線距能夠製作得非常小。In the above method, the process of making the redistribution layer 3 is the same as the process of making the bare core. There are multiple layers of wires 33 in the redistribution layer. The line width and line pitch of the traces in the redistribution layer 3 can be made very small.

第七步，參考圖3f，在重佈線層3上形成鈍化層4。鈍化層4的材料例如可以是矽的氮化物或者聚醯亞胺（polyimide）等材料。鈍化層4起到保護其下方元件的作用。In the seventh step, referring to FIG. 3 f , a passivation layer 4 is formed on the redistribution layer 3 . The material of the passivation layer 4 can be, for example, silicon nitride or polyimide. The passivation layer 4 plays a role in protecting the components below it.

第八步，參考圖1a，在鈍化層4上刻蝕出過孔，從而曝露各個第三焊盤32，在第三焊盤32上形成第一電極結構5。第一電極結構5例如包括第三焊盤32上方的凸點下金屬（UBM）以及凸點下金屬上方的焊錫球，當然，第一電極結構5也可以是焊盤（Pad）的形態。In the eighth step, referring to FIG. 1 a , via holes are etched on the passivation layer 4 to expose each third pad 32 , and the first electrode structure 5 is formed on the third pad 32 . The first electrode structure 5 includes, for example, an under-bump metallurgy (UBM) above the third pad 32 and a solder ball above the UBM. Of course, the first electrode structure 5 may also be in the form of a pad.

在一些實施例中，參考圖4a至圖4f以及圖1b，半導體封裝方法的過程如下。In some embodiments, referring to FIGS. 4 a to 4 f and FIG. 1 b , the process of the semiconductor packaging method is as follows.

第一步，參考圖4a，控制開槽工藝（比如分步刻蝕或多次刻蝕）在襯底1上形成多個第一凹槽H1以及第二凹槽H2，各凹槽的深度不等。The first step, referring to FIG. 4a, controls the grooving process (such as stepwise etching or multiple etching) to form a plurality of first grooves H1 and second grooves H2 on the substrate 1, and the depth of each groove is different. wait.

第二步，參考圖4b，在第一凹槽H1以及第二凹槽H2的槽底形成絕緣黏膠層111。The second step, referring to FIG. 4 b , is to form an insulating adhesive layer 111 at the bottom of the first groove H1 and the second groove H2 .

第三步，參考圖4b，將第一被封裝元件22a和第一被封裝元件23a分別放在一個第一凹槽H1內，將第二被封裝元件21a放置在第二凹槽H2內，並且第一被封裝元件22a、23a以及第二被封裝元件21a均黏貼在絕緣黏膠111上，其中，第一被封裝元件22a的第一焊盤221a和第一被封裝元件23a的第一焊盤231a朝上，第一焊盤221a、231a以及第二電極結構211a的上表面平齊，第一被封裝元件22a、23a和第二被封裝元件21a的厚度不相等，其所處凹槽的槽深也不相等。In the third step, referring to FIG. 4b, the first packaged component 22a and the first packaged component 23a are respectively placed in a first groove H1, the second packaged component 21a is placed in a second groove H2, and The first packaged components 22a, 23a and the second packaged component 21a are pasted on the insulating adhesive 111, wherein the first pad 221a of the first packaged component 22a and the first pad of the first packaged component 23a 231a facing upward, the upper surfaces of the first pads 221a, 231a and the second electrode structure 211a are flush, the thicknesses of the first packaged components 22a, 23a and the second packaged component 21a are not equal, and the grooves of the grooves where they are located Not equal in depth.

第四步，參考圖4c，向第一凹槽H1以及第二凹槽H2內填充並固化絕緣材料112。例如是將液態狀的環氧樹脂滴入第一凹槽H1與第一被封裝元件22a、23a之間的縫隙，以及滴入第二凹槽H2與第二被封裝元件21a之間的縫隙，並通過加熱固化環氧樹脂。The fourth step, referring to FIG. 4 c , is to fill and cure the insulating material 112 into the first groove H1 and the second groove H2 . For example, liquid epoxy resin is dropped into the gap between the first groove H1 and the first packaged components 22a, 23a, and into the gap between the second groove H2 and the second packaged component 21a, And the epoxy resin is cured by heating.

第五步，參考圖4d，磨削去除高出第一焊盤221a、231a以及第二電極結構211a的絕緣材料以及高出第一焊盤221a、231a以及第二電極結構211a的襯底材料，隨後進行諸如化學清洗、拋光等的表面處理工藝，得到曝露第一焊盤221a、231a以及第二電極結構211a的平整表面。The fifth step, referring to FIG. 4d, is grinding to remove the insulating material higher than the first pads 221a, 231a and the second electrode structure 211a and the substrate material higher than the first pads 221a, 231a and the second electrode structure 211a, Subsequently, a surface treatment process such as chemical cleaning, polishing, etc. is performed to obtain a flat surface exposing the first pads 221a, 231a and the second electrode structure 211a.

第六步，參考圖4e，在這個平整表面上形成重佈線層3，重佈線層3的第二焊盤31分別與第一焊盤221a、231a以及第二電極結構211a實現電接觸，重佈線層3的第三焊盤32與第二焊盤31進行互連。重佈線層3內至少包含一層走線33，以及連接走線33與第二焊盤31的過孔、連接走線33與第三焊盤32的過孔。The sixth step, referring to FIG. 4e, is to form a rewiring layer 3 on this flat surface, and the second pads 31 of the rewiring layer 3 are respectively in electrical contact with the first pads 221a, 231a and the second electrode structure 211a, and the rewiring The third pad 32 of layer 3 is interconnected with the second pad 31 . The redistribution layer 3 includes at least one layer of traces 33 , vias connecting the traces 33 and the second pad 31 , and vias connecting the traces 33 and the third pad 32 .

具體地，可通過濺射或電鍍、以及光刻、刻蝕、清洗等的圖形化工藝形成第二焊盤31的圖案，然後通過沉積等FAB工藝形成絕緣材料層（例如是二氧化矽層），再在絕緣材料層形成曝露第二焊盤31的過孔，然後通過濺射或電鍍、以及圖形化的工藝形成連接第二焊盤31的走線33，之後再沉積形成另一側絕緣材料層；隨後在最新得到絕緣材料層中形成曝露下層走線33的過孔，最後再經濺射或電鍍、以及圖形化的工藝得到第三焊盤32的圖案。Specifically, the pattern of the second pad 31 can be formed by sputtering or electroplating, and patterning processes such as photolithography, etching, and cleaning, and then an insulating material layer (such as a silicon dioxide layer) can be formed by FAB processes such as deposition. , and then form a via hole exposing the second pad 31 in the insulating material layer, and then form a wiring 33 connecting the second pad 31 by sputtering or electroplating, and a patterning process, and then deposit an insulating material on the other side layer; then form a via hole exposing the lower layer wiring 33 in the newly obtained insulating material layer, and finally obtain the pattern of the third pad 32 through sputtering or electroplating and patterning processes.

以上方式中，製作重佈線層的工藝與製作裸芯的工藝是相同的。該重佈線層中包含至少一層走線33。In the above method, the process of making the redistribution layer is the same as the process of making the bare core. The redistribution layer includes at least one layer of wires 33 .

第七步，參考圖4f，在重佈線層3上形成鈍化層4。鈍化層4的材料例如可以是矽的氮化物或者聚醯亞胺（polyimide）等材料。鈍化層4起到保護其下方元件的作用。In the seventh step, referring to FIG. 4 f , a passivation layer 4 is formed on the redistribution layer 3 . The material of the passivation layer 4 can be, for example, silicon nitride or polyimide. The passivation layer 4 plays a role in protecting the components below it.

第八步，參考圖1b，在鈍化層4上刻蝕出過孔，從而曝露各個第三焊盤32，在第三焊盤32上形成第一電極結構5。第一電極結構5例如包括第三焊盤32上方的凸點下金屬（UBM）以及凸點下金屬上方的焊錫球，第一電極結構5也可以是焊盤（Ponding Pad）。In the eighth step, referring to FIG. 1 b , via holes are etched on the passivation layer 4 to expose each third pad 32 , and the first electrode structure 5 is formed on the third pad 32 . The first electrode structure 5 includes, for example, an under bump metallurgy (UBM) above the third pad 32 and a solder ball above the UBM, and the first electrode structure 5 may also be a pad (Ponding Pad).

本申請的實施例還提供一種半導體器件，包括前述的半導體封裝結構。即可以對前述的半導體封裝結構進行進一步加工，例如是和其他的半導體封裝結構組合成元件或模組。An embodiment of the present application further provides a semiconductor device, including the aforementioned semiconductor package structure. That is, the aforementioned semiconductor package structure can be further processed, for example, combined with other semiconductor package structures to form a component or a module.

本申請的實施例還提供一種電子產品，包括：前述的半導體器件。電子產品例如是手機、電腦、伺服器、智慧手錶等各種類型的電子產品。An embodiment of the present application also provides an electronic product, including: the foregoing semiconductor device. Electronic products are, for example, various types of electronic products such as mobile phones, computers, servers, and smart watches.

得益於上述半導體封裝結構的穩定性的提升，這些半導體器件、電子產品的穩定性也相應得到提升。Thanks to the improvement of the stability of the above-mentioned semiconductor packaging structure, the stability of these semiconductor devices and electronic products is also correspondingly improved.

本申請中的各個實施例均採用遞進的方式描述，各個實施例之間相同相似的部分互相參見即可，每個實施例重點說明的都是與其他實施例的不同之處。Each embodiment in the present application is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.

本申請的保護範圍不限於上述的實施例，顯然，本領域的技術人員可以對本申請進行各種改動和變形而不脫離本申請的範圍和精神。倘若這些改動和變形屬於本申請請求項及其等同技術的範圍，則本申請的意圖也包含這些改動和變形在內。The protection scope of the present application is not limited to the above-mentioned embodiments. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope and spirit of the present application. If these changes and modifications fall within the scope of the claims of this application and their equivalent technologies, the intent of this application is to also include these changes and modifications.

步驟1000:在襯底上形成至少一個第一凹槽和至少一個第二凹槽 步驟1001:將至少一個第一被封裝元件一一對應地固定在第一凹槽內，將至少一個第二被封裝元件一一對應地固定在第二凹槽內，其中，第一被封裝元件呈裸芯狀態，第二被封裝元件呈封裝狀態且具有外露的第二電極結構，第一被封裝元件的有源表面背向襯底，第一被封裝元件與其所處第一凹槽之間由絕緣材料隔開，第二被封裝元件與其所處第二凹槽之間由絕緣材料隔開，各第一被封裝元件均具有位於其有源表面上的第一焊盤，全部第一焊盤以及全部第二電極結構的背向襯底的表面平齊 步驟1002:形成曝露第一焊盤以及第二電極結構的平整表面 步驟1003:採用晶圓製作工藝形成重佈線層，重佈線層的第一面上形成有多個第二焊盤，重佈線層的與第一面相對的第二面上形成有多個第三焊盤，第一焊盤與部分第二焊盤一一對應地電接觸，第二電極結構與其餘第二焊盤一一對應地電接觸，重佈線層具有電連接第二焊盤和第三焊盤的走線、以及電連接第二焊盤和第二電極結構的走線 步驟1004:形成鈍化層 步驟1005:在鈍化層上形成至少一個過孔，過孔與第三焊盤一一對應，過孔曝露對應的第三焊盤 步驟1006:在第三焊盤上形成與其電接觸的第一電極結構 1:襯底 10:凹槽 111:絕緣黏膠層 112:絕緣材料 21a:第二被封裝元件 22a、23a:第一被封裝元件 211a:第二電極結構 221a、231a:第一焊盤 3:重佈線層 31:第二焊盤 32:第三焊盤 33:走線 4:鈍化層 5:電極結構 H1:第一凹槽 H2:第二凹槽 Step 1000: forming at least one first groove and at least one second groove on the substrate Step 1001: Fix at least one first packaged component in the first groove one by one, and fix at least one second packaged component in the second groove one by one, wherein the first packaged component It is in a bare core state, the second packaged component is in a packaged state and has an exposed second electrode structure, the active surface of the first packaged component faces away from the substrate, and the first packaged component is located between the first groove Separated by an insulating material, the second packaged component and the second groove where it is located are separated by an insulating material, each first packaged component has a first pad located on its active surface, and all the first pads The surface of the disk and all second electrode structures facing away from the substrate is flush Step 1002: forming a flat surface exposing the first pad and the second electrode structure Step 1003: A redistribution layer is formed using a wafer manufacturing process, a plurality of second pads are formed on the first surface of the redistribution layer, and a plurality of third pads are formed on a second surface of the redistribution layer opposite to the first surface. The first pad is in one-to-one electrical contact with part of the second pads, the second electrode structure is in one-to-one electrical contact with the rest of the second pads, and the redistribution layer is electrically connected to the second pad and the third pad. The wiring of the pad and the wiring electrically connecting the second pad and the second electrode structure Step 1004: forming a passivation layer Step 1005: forming at least one via hole on the passivation layer, the via hole corresponds to the third pad one by one, and the via hole exposes the corresponding third pad Step 1006: forming a first electrode structure in electrical contact with the third pad on the third pad 1: Substrate 10: Groove 111: insulating adhesive layer 112: insulating material 21a: the second packaged component 22a, 23a: the first packaged component 211a: Second electrode structure 221a, 231a: the first pad 3: Rewiring layer 31: The second pad 32: The third pad 33: Routing 4: Passivation layer 5: Electrode structure H1: first groove H2: second groove

[圖1a和圖1b]是根據本申請實施例的兩種半導體封裝結構的結構示意圖。 [圖2]是根據本申請實施例的半導體封裝方法的流程示意圖。 [圖3a至圖3f]是圖1a所示半導體封裝結構在封裝的不同階段的產品狀態示意圖。 [圖4a至圖4f]是圖1b所示半導體封裝結構在封裝的不同階段的產品狀態示意圖。 [FIG. 1a and FIG. 1b] are structural schematic diagrams of two semiconductor packaging structures according to embodiments of the present application. [ FIG. 2 ] is a schematic flowchart of a semiconductor packaging method according to an embodiment of the present application. [FIG. 3a to FIG. 3f] are schematic diagrams of product states of the semiconductor package structure shown in FIG. 1a at different stages of packaging. [FIG. 4a to FIG. 4f] are schematic diagrams of product states of the semiconductor package structure shown in FIG. 1b at different stages of packaging.

1:襯底 1: Substrate

111:絕緣黏膠層 111: insulating adhesive layer

112:絕緣材料 112: insulating material

21a:第二被封裝元件 21a: the second packaged component

22a、23a:第一被封裝元件 22a, 23a: the first packaged component

211a:第二電極結構 211a: Second electrode structure

221a、231a:第一焊盤 221a, 231a: the first pad

3:重佈線層 3: Rewiring layer

31:第二焊盤 31: The second pad

32:第三焊盤 32: The third pad

33:走線 33: Routing

4:鈍化層 4: Passivation layer

5:電極結構 5: Electrode structure

Claims (29)

一種半導體封裝結構，其中，包括：襯底、至少一個第一被封裝元件、至少一個第二被封裝元件、重佈線層和鈍化層，所述襯底上開設有至少一個第一凹槽和至少一個第二凹槽，所述第一被封裝元件一一對應地固定在所述第一凹槽內，所述第二被封裝元件一一對應地固定在所述第二凹槽內，所述第一被封裝元件呈裸芯狀態，所述第二被封裝元件呈封裝狀態且具有外露的第二電極結構； 所述第一被封裝元件的有源表面背向所述襯底，所述第一被封裝元件與其所處第一凹槽之間由絕緣材料隔開，所述第二被封裝元件與其所處第二凹槽之間由絕緣材料隔開，各所述第一被封裝元件均具有位於其有源表面上的第一焊盤，全部所述第一焊盤背向所述襯底的表面以及全部第二電極結構背向所述襯底的表面平齊； 所述重佈線層位於所述第一被封裝元件和所述第二被封裝元件背向所述襯底一側，所述重佈線層的第一面上形成有多個第二焊盤，所述重佈線層的與所述第一面相對的第二面上形成有多個第三焊盤，所述第一焊盤與部分第二焊盤一一對應地電接觸，所述第二電極結構與其餘第二焊盤一一對應地電接觸，所述重佈線層還具有電連接第二焊盤和第三焊盤的走線、以及電連接第二焊盤和第二電極結構的走線； 所述鈍化層位於所述重佈線層背向所述襯底一側； 其中，所述襯底由半導體材料或絕緣材料形成，所述襯底與所述第一被封裝元件內的半導體材料的熱膨脹係數相同或相近，所述重佈線層由晶圓製造工藝形成。 A semiconductor packaging structure, including: a substrate, at least one first packaged component, at least one second packaged component, a rewiring layer and a passivation layer, and at least one first groove and at least one a second groove, the first packaged components are fixed in the first groove one by one, the second packaged components are fixed in the second groove one by one, the The first packaged component is in a bare core state, and the second packaged component is in a packaged state and has an exposed second electrode structure; The active surface of the first packaged component faces away from the substrate, the first packaged component is separated from the first groove where it is located by an insulating material, and the second packaged component is separated from the first groove where it is located. The second grooves are separated by an insulating material, each of the first packaged components has a first pad located on its active surface, all of the first pads face away from the surface of the substrate, and all second electrode structures are flush with the surface facing away from the substrate; The redistribution layer is located on the side of the first packaged component and the second packaged component facing away from the substrate, and a plurality of second pads are formed on the first surface of the redistribution layer, so A plurality of third pads are formed on the second surface of the redistribution layer opposite to the first surface, the first pads are in electrical contact with part of the second pads in one-to-one correspondence, and the second electrode The structure is in one-to-one electrical contact with the rest of the second pads, and the redistribution layer also has a wiring that electrically connects the second pad and the third pad, and a wiring that electrically connects the second pad and the second electrode structure. Wire; The passivation layer is located on the side of the redistribution layer facing away from the substrate; Wherein, the substrate is formed of a semiconductor material or an insulating material, the thermal expansion coefficient of the substrate is the same or similar to that of the semiconductor material in the first packaged component, and the rewiring layer is formed by a wafer manufacturing process. 如請求項1所述的半導體封裝結構，其中，所述襯底內的半導體材料與所述第一被封裝元件內的半導體材料相同。The semiconductor package structure according to claim 1, wherein the semiconductor material in the substrate is the same as the semiconductor material in the first packaged component. 如請求項1所述的半導體封裝結構，其中，所述第一被封裝元件內的半導體材料為矽或砷化鎵或氮化鎵或碳化矽，並且所述襯底的材料為玻璃材料。The semiconductor package structure according to claim 1, wherein the semiconductor material in the first packaged component is silicon or gallium arsenide or gallium nitride or silicon carbide, and the material of the substrate is glass material. 如請求項1所述的半導體封裝結構，其中，所述重佈線層內的走線由包括光刻和刻蝕的晶圓製造工藝形成，所述重佈線層內的絕緣材料由包括沉積的晶圓製造工藝形成。The semiconductor package structure according to claim 1, wherein the wiring in the redistribution layer is formed by a wafer manufacturing process including photolithography and etching, and the insulating material in the redistribution layer is formed by including a deposited wafer Circle manufacturing process formation. 如請求項1所述的半導體封裝結構，其中，所述第一被封裝元件內的絕緣材料以及所述重佈線層內的絕緣材料的熱膨脹係數相同或相近。The semiconductor package structure according to claim 1, wherein the thermal expansion coefficients of the insulating material in the first packaged component and the insulating material in the redistribution layer are the same or similar. 如請求項5所述的半導體封裝結構，其中，所述重佈線層內的絕緣材料和所述第一被封裝元件內的絕緣材料均包含二氧化矽。The semiconductor package structure according to claim 5, wherein both the insulating material in the redistribution layer and the insulating material in the first packaged component contain silicon dioxide. 如請求項1所述的半導體封裝結構，其中，所述第一被封裝元件的數量為多個且厚度相等，各所述第一凹槽的深度相等。The semiconductor package structure according to claim 1, wherein the number of the first packaged components is multiple and the thickness is equal, and the depth of each of the first grooves is equal. 如請求項1所述的半導體封裝結構，其中，所述第一被封裝元件的數量為多個，且至少兩個第一被封裝元件的厚度不相等，其中，至少兩個第一凹槽的深度不同，以使各所述第一被封裝元件的第一焊盤的上表面平齊。The semiconductor package structure according to claim 1, wherein the number of the first packaged components is multiple, and the thicknesses of at least two first packaged components are not equal, wherein the at least two first grooves The depths are different, so that the upper surfaces of the first pads of the first packaged components are flush. 如請求項1所述的半導體封裝結構，其中，還包括位於所述鈍化層背向所述襯底一側的第一電極結構，所述鈍化層上與所述第三焊盤相對的區域開設有過孔，所述第一電極結構與所述第三焊盤一一對應，所述第一電極結構通過所述過孔與對應第三焊盤電連接。The semiconductor package structure according to claim 1, further comprising a first electrode structure located on the side of the passivation layer facing away from the substrate, an area on the passivation layer opposite to the third pad is opened There are via holes, the first electrode structures correspond to the third pads one by one, and the first electrode structures are electrically connected to the corresponding third pads through the via holes. 如請求項1所述的半導體封裝結構，其中，所述第一被封裝元件與所處第一凹槽的槽底之間由絕緣黏膠層隔開，所述第二被封裝元件與所處第二凹槽的槽底之間由絕緣黏膠層隔開。The semiconductor package structure according to claim 1, wherein the first packaged component is separated from the groove bottom of the first groove where it is located by an insulating adhesive layer, and the second packaged component is separated from the bottom of the first groove where it is located. The groove bottoms of the second grooves are separated by an insulating glue layer. 如請求項1所述的半導體封裝結構，其中，所述第一被封裝元件與所處第一凹槽的側面之間由固化的樹脂材料或無機絕緣材料隔開，所述第二被封裝元件與所處第二凹槽的側面之間由固化的樹脂材料或無機絕緣材料隔開。The semiconductor package structure according to claim 1, wherein the first packaged component is separated from the side of the first groove by cured resin material or inorganic insulating material, and the second packaged component It is separated from the side of the second groove by cured resin material or inorganic insulating material. 如請求項1所述的半導體封裝結構，其中，所述第二被封裝元件為貼片式封裝或為陶瓷封裝。The semiconductor package structure according to claim 1, wherein the second packaged component is a chip package or a ceramic package. 一種半導體封裝方法，其中，包括： 在襯底上形成至少一個第一凹槽和至少一個第二凹槽； 將至少一個第一被封裝元件一一對應地固定在所述第一凹槽內，將至少一個第二被封裝元件一一對應地固定在所述第二凹槽內，其中，所述第一被封裝元件呈裸芯狀態，所述第二被封裝元件呈封裝狀態且具有外露的第二電極結構，所述第一被封裝元件的有源表面背向所述襯底，所述第一被封裝元件與其所處第一凹槽之間由絕緣材料隔開，所述第二被封裝元件與其所處第二凹槽之間由絕緣材料隔開，各所述第一被封裝元件均具有位於其有源表面上的第一焊盤，全部所述第一焊盤以及全部第二電極結構的背向所述襯底的表面平齊； 形成曝露所述第一焊盤以及所述第二電極結構的平整表面； 採用晶圓製作工藝形成重佈線層，所述重佈線層的第一面上形成有多個第二焊盤，所述重佈線層的與所述第一面相對的第二面上形成有多個第三焊盤，所述第一焊盤與部分第二焊盤一一對應地電接觸，所述第二電極結構與其餘第二焊盤一一對應地電接觸，所述重佈線層具有電連接第二焊盤和第三焊盤的走線、以及電連接第二焊盤和第二電極結構的走線； 形成鈍化層； 其中，所述襯底由半導體材料或絕緣材料形成，所述襯底與所述第一被封裝元件內的半導體材料的熱膨脹係數相同或相近。 A semiconductor packaging method, comprising: forming at least one first groove and at least one second groove on the substrate; fixing at least one first packaged component in the first groove in a one-to-one correspondence, and fixing at least one second packaged component in the second groove in a one-to-one correspondence, wherein the first The packaged component is in a bare core state, the second packaged component is in a packaged state and has an exposed second electrode structure, the active surface of the first packaged component faces away from the substrate, and the first packaged component The packaging component is separated from the first groove where it is located by an insulating material, and the second packaged component is separated from the second groove where it is located by an insulating material. Each of the first packaged components has a The first pad on its active surface, the surfaces of all the first pads and all the second electrode structures facing away from the substrate are flush; forming a flat surface exposing the first pad and the second electrode structure; A redistribution layer is formed by using a wafer manufacturing process, a plurality of second pads are formed on the first surface of the redistribution layer, and multiple pads are formed on a second surface of the redistribution layer opposite to the first surface. a third pad, the first pad is in one-to-one electrical contact with part of the second pads, the second electrode structure is in one-to-one electrical contact with the rest of the second pads, and the redistribution layer has a wiring electrically connecting the second pad and the third pad, and a wiring electrically connecting the second pad and the second electrode structure; form a passivation layer; Wherein, the substrate is formed of a semiconductor material or an insulating material, and the coefficient of thermal expansion of the substrate is the same as or similar to that of the semiconductor material in the first packaged component. 如請求項13所述的方法，其中，所述襯底內的半導體材料與所述第一被封裝元件內的半導體材料相同。The method of claim 13, wherein the semiconductor material in the substrate is the same as the semiconductor material in the first packaged component. 如請求項13所述的方法，其中，所述第一被封裝元件內的半導體材料為矽或砷化鎵或氮化鎵或碳化矽，並且所述襯底的材料為玻璃材料。The method according to claim 13, wherein the semiconductor material in the first packaged component is silicon or gallium arsenide or gallium nitride or silicon carbide, and the material of the substrate is glass material. 如請求項13所述的方法，其中，採用包括光刻和刻蝕的晶圓製造工藝形成所述重佈線層內的走線，採用包括沉積的晶圓製造工藝形成所述重佈線層內的絕緣材料。The method according to claim 13, wherein the wiring in the redistribution layer is formed by a wafer fabrication process including photolithography and etching, and the wiring in the redistribution layer is formed by a wafer fabrication process including deposition. Insulation Materials. 如請求項13所述的方法，其中，所述重佈線層內的絕緣材料和所述第一被封裝元件內的絕緣材料均包含二氧化矽。The method according to claim 13, wherein both the insulating material in the redistribution layer and the insulating material in the first packaged component contain silicon dioxide. 如請求項13所述的方法，其中，所述第一被封裝元件的數量為多個，其所處第一凹槽的深度相同，所述方法還包括：對至少部分第一被封裝元件進行減薄，以使各第一被封裝元件的厚度相等。The method according to claim 13, wherein the number of the first packaged components is multiple, and the depths of the first grooves are the same, and the method further includes: conducting at least part of the first packaged components Thinning, so that the thickness of each first packaged component is equal. 如請求項13所述的方法，其中，所述第一被封裝元件和所述第二被封裝元件中且至少兩個被封裝元件的厚度不相等，在所述襯底上形成所述第一凹槽和所述第二凹槽時，至少兩個凹槽的深度是不等的，以使各所述第一被封裝元件的第一焊盤的上表面以及各第二電極結構的上表面平齊。The method according to claim 13, wherein at least two of the first packaged component and the second packaged component have unequal thicknesses, and the first packaged component is formed on the substrate. When the groove and the second groove are used, the depths of at least two grooves are not equal, so that the upper surface of the first pad of each of the first packaged components and the upper surface of each second electrode structure flush. 如請求項13所述的方法，其中，將至少一個第一被封裝元件一一對應地固定在所述第一凹槽內，包括： 在所述第一凹槽的槽底所形成絕緣黏膠層； 將所述第一被封裝元件黏貼在所述絕緣黏膠上，其中，所述第一被封裝元件與所處第一凹槽的側面之間留有空隙； 向所述第一被封裝元件與對應的第一凹槽的側面之間填充絕緣材料。 The method according to claim 13, wherein fixing at least one first packaged component in the first groove in a one-to-one correspondence comprises: an insulating adhesive layer formed on the bottom of the first groove; Paste the first packaged component on the insulating adhesive, wherein there is a gap between the first packaged component and the side of the first groove; An insulating material is filled between the first packaged component and the side of the corresponding first groove. 如請求項20所述的方法，其中，向所述第一被封裝元件與對應的第一凹槽側面之間填充絕緣材料，包括： 向所述第一被封裝元件與對應的第一凹槽側面之間填充並固化樹脂材料，或向所述第一被封裝元件與對應的第一凹槽側面之間的空隙沉積無機氧化物絕緣材料。 The method according to claim 20, wherein filling an insulating material between the first packaged component and the corresponding side of the first groove comprises: filling and curing a resin material between the first packaged component and the corresponding side of the first groove, or depositing an inorganic oxide insulation in the gap between the first packaged component and the corresponding side of the first groove Material. 如請求項13所述的方法，其中，將至少一個第二被封裝元件一一對應地固定在所述第二凹槽內，包括： 在所述第二凹槽的槽底所形成絕緣黏膠層； 將所述第二被封裝元件黏貼在所述絕緣黏膠上，其中，所述第二被封裝元件與所處第二凹槽的側面之間留有空隙； 向所述第一被封裝元件與對應的第一凹槽的側面之間填充絕緣材料。 The method according to claim 13, wherein fixing at least one second packaged component in the second groove in a one-to-one correspondence comprises: an insulating adhesive layer formed on the bottom of the second groove; sticking the second packaged component on the insulating adhesive, wherein there is a gap between the second packaged component and the side of the second groove; An insulating material is filled between the first packaged component and the side of the corresponding first groove. 如請求項22所述的方法，其中，向所述第二被封裝元件與對應的第二凹槽側面之間填充絕緣材料，包括： 向所述第二被封裝元件與對應的第二凹槽側面之間填充並固化樹脂材料，或向所述第二被封裝元件與對應的第二凹槽側面之間的空隙沉積無機氧化物絕緣材料。 The method according to claim 22, wherein filling an insulating material between the second packaged component and the corresponding side of the second groove comprises: Filling and curing a resin material between the second packaged component and the corresponding side of the second groove, or depositing an inorganic oxide insulation in the gap between the second packaged component and the corresponding side of the second groove Material. 如請求項13所述的方法，其中，形成曝露所述第一焊盤以及所述第二電極結構的平整表面，包括： 通過磨削工藝去除高出所述第一焊盤以及所述第二電極結構的絕緣材料以及襯底材料，隨後進行表面處理。 The method according to claim 13, wherein forming a flat surface exposing the first pad and the second electrode structure comprises: The insulating material and the substrate material higher than the first pad and the second electrode structure are removed through a grinding process, followed by surface treatment. 如請求項13所述的方法，其中，還包括： 在所述鈍化層上形成多個過孔，所述過孔與所述第三焊盤一一對應，所述過孔曝露對應的第三焊盤； 在所述第三焊盤上形成與其電接觸的第一電極結構。 The method as described in claim item 13, further comprising: forming a plurality of via holes on the passivation layer, the via holes correspond to the third pads one by one, and the via holes expose the corresponding third pads; A first electrode structure in electrical contact with the third pad is formed on the third pad. 如請求項13或25所述的方法，其中，還包括： 通過切割工藝得到多個半導體封裝結構，其中，至少一個半導體封裝結構包含：至少一個所述第一被封裝元件、至少一個所述第二被封裝元件、所含第一被封裝元件所處的第一凹槽、所含第二被封裝元件所處的第二凹槽、與所含第一被封裝元件和所含第二被封裝元件電連接的重佈線層、以及所含重佈線層上方的鈍化層。 The method as described in claim 13 or 25, further comprising: A plurality of semiconductor package structures are obtained through a dicing process, wherein at least one semiconductor package structure includes: at least one of the first packaged components, at least one of the second packaged components, and a first packaged component where the first packaged component is located. A groove, a second groove where the second packaged component is located, a redistribution layer electrically connected to the first packaged component and the second packaged component, and the redistribution layer above the redistribution layer passivation layer. 如請求項13所述的方法，其中，所述第二被封裝元件為貼片式封裝或為陶瓷封裝。The method according to claim 13, wherein the second packaged component is a patch package or a ceramic package. 一種半導體器件，其中，包括：如請求項1至12任意一項所述的半導體封裝結構。A semiconductor device, including: the semiconductor package structure according to any one of Claims 1 to 12. 一種電子產品，其中，包括：如請求項28所述的半導體器件。An electronic product, including: the semiconductor device as claimed in claim 28.
TW111104271A 2021-04-01 2022-02-07 Semiconductor packaging structure, method, device and electronic product TWI818429B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110352884.7A CN113097201B (en) 2021-04-01 2021-04-01 Semiconductor packaging structure, method, device and electronic product
CN202110352884.7 2021-04-01

Publications (2)

Publication Number Publication Date
TW202303918A true TW202303918A (en) 2023-01-16
TWI818429B TWI818429B (en) 2023-10-11

Family

ID=76672163

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111104271A TWI818429B (en) 2021-04-01 2022-02-07 Semiconductor packaging structure, method, device and electronic product

Country Status (3)

Country Link
KR (1) KR102647098B1 (en)
CN (1) CN113097201B (en)
TW (1) TWI818429B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117038629A (en) * 2023-10-09 2023-11-10 之江实验室 Plastic-package-free embedded system-on-a-chip structure based on glass carrier plate and preparation method

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3196434B2 (en) * 1993-06-23 2001-08-06 オムロン株式会社 Method for manufacturing multi-chip IC
US5602423A (en) * 1994-11-01 1997-02-11 Texas Instruments Incorporated Damascene conductors with embedded pillars
JP3840761B2 (en) * 1997-09-25 2006-11-01 株式会社日立製作所 Multichip module and manufacturing method thereof
US20080142946A1 (en) * 2006-12-13 2008-06-19 Advanced Chip Engineering Technology Inc. Wafer level package with good cte performance
JP2012199494A (en) * 2011-03-23 2012-10-18 Teramikros Inc Manufacturing method of semiconductor device and manufacturing method of semiconductor device packaging structure
US9252172B2 (en) * 2011-05-31 2016-02-02 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region
CN103346097B (en) * 2013-06-25 2016-12-28 华进半导体封装先导技术研发中心有限公司 Three-dimension packaging method based on TSV and encapsulating structure
JP2015056458A (en) * 2013-09-10 2015-03-23 株式会社東芝 Semiconductor device
US9881850B2 (en) * 2015-09-18 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
JP2017183635A (en) * 2016-03-31 2017-10-05 ソニー株式会社 Semiconductor device, method of manufacturing the same, integrated substrate, and electronic equipment
US9922845B1 (en) * 2016-11-03 2018-03-20 Micron Technology, Inc. Semiconductor package and fabrication method thereof
KR102059814B1 (en) * 2018-07-12 2019-12-27 삼성전기주식회사 Antenna module
KR102538180B1 (en) * 2018-10-01 2023-05-31 삼성전자주식회사 Opened pad structure and semiconductor package comprising the same
JP6621951B1 (en) * 2018-12-28 2019-12-18 長瀬産業株式会社 Manufacturing method of semiconductor device
US11456287B2 (en) * 2019-08-28 2022-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
DE102020108481B4 (en) * 2019-09-27 2023-07-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die package and manufacturing process
CN112117258A (en) * 2020-10-14 2020-12-22 立讯电子科技（昆山）有限公司 Chip packaging structure and packaging method thereof

Also Published As

Publication number Publication date
KR102647098B1 (en) 2024-03-15
TWI818429B (en) 2023-10-11
KR20220137537A (en) 2022-10-12
CN113097201A (en) 2021-07-09
CN113097201B (en) 2023-10-27

Similar Documents

Publication Publication Date Title
TWI441285B (en) Recessed semiconductor substrates for package apparatus and method thereof
CN107768351A (en) Semiconductor package part with heat engine electrical chip and forming method thereof
TWI254425B (en) Chip package structure, chip packaging process, chip carrier and manufacturing process thereof
JP2017022398A (en) Window interposed die packaging
TW201709455A (en) Microelectronic assemblies with cavities, and methods of fabrication
TWI544599B (en) Fabrication method of package structure
KR101605600B1 (en) Manufacturing method of semiconductor device and semiconductor device thereof
TW201603235A (en) Integrated circuit assemblies with reinforcement frames, and methods of manufacture
KR20140130395A (en) Method of manufacturing semiconductor device
CN108074896A (en) Semiconductor devices and method
US20120286408A1 (en) Wafer level package with thermal pad for higher power dissipation
TW201405735A (en) Grid fan-out wafer level package and methods of manufacturing a grid fan-out wafer level package
JP2007110117A (en) Wafer level chip scale package of image sensor, and method of manufacturing same
JP2008537355A (en) Passive element using metal flake and method of manufacturing semiconductor package
KR102241696B1 (en) Integrated fan-out packages and methods of forming the same
JP3673094B2 (en) Multi-chip semiconductor device
TWI245350B (en) Wafer level semiconductor package with build-up layer
TWI574333B (en) Electronic package and method for fabricating the same
TWI818429B (en) Semiconductor packaging structure, method, device and electronic product
TW201539596A (en) Mediator and method of manufacturing same
KR101095055B1 (en) Method for manufacturing semiconductor device
TWI787085B (en) Semiconductor packaging structure, semiconductor packaging method, semiconductor packaging device and electronic product
TWI821894B (en) Semiconductor packaging structure, method, device and electronic product
US20220320028A1 (en) Semiconductor packaging structure, method, device and electronic product
US20220293504A1 (en) Semiconductor packaging structure, method, device and electronic product