TW202247129A - Spliced display apparatus - Google Patents

Abstract

A spliced display apparatus includes a plurality of display panels. The display panel includes a first display panel and a second display panel. Each of the display panels has a first side facing one of the neighboring display panels and a second side crossing the first side. Each of the display panels has an outer lead bonding region and includes a substrate, a pixel array and data lines. Outer lead bonding region is between the pixel array and the second side. The pixel array includes a first pixel column. The first pixel column is adjacent to the first side. The data lines include a first fan out line and a second fan out line. The first fan out line is electrically connected to the first pixel column of the first display panel. The second fan out line is electrically connected to the first pixel column of the second display panel. The second fan out line is across the first side of the second display panel and the first side of the first display panel and extends to the outer lead bonding region of the first display panel.

Description

tiled display device

The invention relates to a spliced display device.

The micro light emitting diode (micro LED) display has the advantages of low power consumption and high brightness, and is one of the key projects that many panel manufacturers are actively developing. At present, the maximum size of a single micro-LED display module is only 12 to 14 inches. If it is larger than 55 inches or even 100 inches, it needs to be achieved by splicing multiple micro-light-emitting diode displays. However, it is difficult to avoid visible stitching seams, such as bright seams, dark seams, or poor display (mura) of modules in bright and dark states, which reduces the visual taste of the display.

The invention provides a splicing display device, the splicing seam of which is invisible.

The invention provides a spliced display device, which includes a plurality of display panels. Each of the display panels has at least one first side facing one of the adjacent display panels and a second side intersecting the first side, and each display panel has an outer lead bonding area. Each display panel includes a substrate, a pixel array and a plurality of data lines. The pixel array is located on the substrate, and the outer pin bonding area is located between the pixel array and the second side. The data line is located on the substrate and is electrically connected to the pixel array. The pixel array includes a first pixel row adjacent to the first side. The display panel includes a first display panel and a second display panel. The data line includes multiple A first fan-out line and a plurality of second fan-out lines. The first fan-out line is electrically connected to the first pixel row of the first display panel. The second fan-out line is electrically connected to the first pixel row of the second display panel, the second fan-out line crosses the first side of the second display panel to the first side of the first display panel and extends to the outside of the first display panel on the pin land.

The present invention provides a spliced display device, which includes a plurality of display panels and circuit boards, and the display panels include a first display panel and a second display panel. Each display panel has at least one first side facing one of the adjacent display panels and a second side intersecting with the first side, each display panel has an outer pin bonding area, and each display panel includes a substrate, a pixel array and Multiple data lines. The pixel array is located on the substrate, and the outer pin bonding area is located between the pixel array and the second side. The data line is located on the substrate and is electrically connected to the pixel array. The pixel array includes a first pixel row adjacent to the first side. The circuit board is arranged on the outer pin bonding area of the first display panel and the outer pin bonding area of the second display panel. The circuit board has a plurality of wires, and the wires are electrically connected to the first pixel row of the second display panel. The outer pin land of the second display panel spans from the first side of the second display panel to the first side of the first display panel and extends onto the outer pin land of the first display panel.

The invention provides a spliced display device, which includes a motherboard and a plurality of display panels. The motherboard has a support substrate and a plurality of wires located on the support substrate. The display panels are located on the motherboard and each has at least one first side facing one of the adjacent display panels and a second side intersecting the first side, each display panel has an outer pin bonding area, and each display panel includes a substrate and pixel arrays. The substrate has a plurality of conductive vias. The pixel array is located on the substrate, the outer pin bonding area is located between the pixel array and the second side, the pixel array includes a first pixel row, and the first pixel row is adjacent to the first side, and the display panel includes the first display panel and The second display panel, the wire is electrically connected to the first pixel row of the second display panel through the conductive via hole, and the wire crosses the first side of the second display panel from the outer pin bonding area of the second display panel to the first display panel of the first display panel. The first side extends to the outer pin bonding area of the first display panel.

Based on the above, in a spliced display device according to an embodiment of the present invention, each display panel has at least one first side facing one of the adjacent display panels, and the first fan-out line is electrically connected to the first side of the first display panel. Pixel row. The second fan-out line is electrically connected to the first pixel row of the second display panel, the second fan-out line crosses the first side of the second display panel to the first side of the first display panel and extends to the outside of the first display panel on the pin land. Thereby, the first pixel rows on the left and right sides of the seam between the first side of the first display panel and the first side of the second display panel can be controlled by a single external circuit. Adjusting the gray scale of the first pixel row by a single external circuit can make the stitching seam invisible.

FIG. 1 is a schematic top view of a spliced display device 10 according to an embodiment of the present invention. Please refer to FIG. 1 , the spliced display device 10 includes a plurality of display panels 100 . Each of the display panels 100 has at least one first side a1 facing one of the adjacent display panels 100 and a second side a2 intersecting the first side a1 . For the convenience of illustration, the first direction D1 and the second direction D2 are shown in the first figure, and the first direction D1 intersects with the second direction D2. For example, the first direction D1 is perpendicular to the second direction D2, but the invention is not limited thereto. In this embodiment, the first side a1 is parallel to the first direction D1, and the second side a2 is parallel to the second direction D2.

Each display panel 100 includes a substrate 102 , a pixel array AR and a plurality of data lines DL. The pixel array AR is located on the substrate 102 . The data line DL is located on the substrate 102 and is electrically connected to the pixel array AR. The material of the substrate 102 is, for example, glass, quartz, plastic, organic polymer, opaque/reflective material (eg, conductive material, metal, wafer, ceramic, or other applicable materials) or other applicable materials. In some embodiments, the substrate 102 can also be a flexible substrate, and its material includes organic polymers, such as polyimide (polyimide, PI), polyethylene naphthalate (polyethylene naphthalate, PEN) or other suitable materials, the present invention is not limited thereto. For example, the substrate 102 can be a yellow polyimide substrate.

Each display panel 100 has an external pin bonding area 103 for connecting external circuits. The external circuit is, for example, a driver chip, a control circuit, a flexible printed circuit (flexible printed circuit, FPC) or a printed circuit board (printed circuit board, PCB) equipped with a driver chip, etc. The flexible printed circuit can be, for example, a liquid crystal polymer flexible printed circuit Board (Liquid Crystal Polymer (LCP) FPC board), so that the pixel array AR can be driven. The outer pin bonding area 103 is located between the pixel array AR and the second side a2.

For example, the display panel 100 includes a first display panel 100A and a second display panel 100B, and the mosaic display device 10 further includes a driving element 104 , and the driving element 104 includes a first driving element 104A and a second driving element 104B. The first driving element 104A is located on the outer pin bonding area 103 of the first display panel 100 , and the second driving element 104B is located on the outer pin bonding area 103 of the second display panel 100B. The outer pin bonding area 103 of the first display panel 100B is connected to the first driving element 104A. The outer pin bonding area 103 of the second display panel 100B is connected to the second driving element 104B, and the first driving element 104A and the second driving element 104B are electrically independent from each other.

In this embodiment, the pixel array AR includes a first pixel row 106 adjacent to the first side a1. The data lines DL include a plurality of first fan-out lines 108 and a plurality of second fan-out lines 110 . The first fan-out line 108 is electrically connected to the first pixel row 106 of the first display panel 100A. The second fan-out line 110 is electrically connected to the first pixel row 106 of the second display panel 100B, and the second fan-out line 110 crosses the first side a1 of the second display panel 100B to the first side a1 of the first display panel 100A and extending to the outer pin bonding area 103 of the first display panel 100A. Thus, the first pixel rows 106 on the left and right sides of the seam 112 on the first side a1 of the first display panel 100A and the first side a1 of the second display panel 100B are all controlled by the first driving element 104A, in other words , controlled by a single drive element. Adjusting the grayscale (ie, brightness) of the first pixel row 106 by a single driving element can make the splicing seam 112 invisible.

Each display panel 100 may include a plurality of pads 113, the pads 113 are located in the outer pin bonding area 103, and the first portion 113A of the pads 113 can be used to connect the first fan-out line 108 and the second fan-out line 110 to the first driver. Element 104A. Since the size of the pad 113 is much larger than the line width of the first fan-out line 108 and the second fan-out line 110 , for example, the area of the pad 113 is hundreds of square micrometers. Therefore, the second fan-out line 110 can be wire-bonded to the first driving element 104A without consuming an extra lithography process, thereby simplifying the process. In other embodiments, the second fan-out line 110 can be formed by ink jet printing (IJP). Based on the consideration of conductivity, the material of the first fan-out line 108 and the second fan-out line 110 is metal (such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum , zinc, alloys of the aforementioned metals or stacked layers of the aforementioned metals). However, the present invention is not limited thereto.

Each pixel array AR also includes a plurality of second pixel rows 114, the second pixel rows 114 are located on one side of the first pixel row 106, and the second pixel rows 114 are used to display pictures, the second picture of the first display panel 100A The pixel row 114A is electrically connected to the outer pin bonding area 103 of the first display panel 100A, and the second pixel row 114B of the second display panel 100B is electrically connected to the outer pin bonding area 103 of the second display panel 100B. That is to say, the second pixel row 114A of the first display panel 100A and the second pixel row 114B of the second display panel 100B are respectively controlled by the first driving element 104A and the second driving element 104B, so that each second pixel row 114A , 114B can display the picture independently.

In this embodiment, the spliced display device 10 further includes a plurality of light-shielding portions 116 and a light-shielding layer 118 . The light shielding portion 116 is respectively located between the adjacent second pixel rows 114A and 114B and between the first pixel row 106 and the second pixel row 114 . For example, the first pixel row 106 and the second pixel row 114A, 114B each include red light emitting elements, green light emitting elements and blue light emitting elements. The light-shielding part 116 is commonly known as a black matrix (Black Matrix, BM). The material of the light-shielding portion 116 and the light-shielding layer 118 is, for example, black resin, but the invention is not limited thereto.

The light shielding layer 118 covers the first side a1 of the first display panel 100A and the first side a1 of the second display panel 100B, and can be formed by inkjet coating technology. The light-shielding layer 118 has a first light-shielding layer 120 and a second light-shielding layer 122. The width w1 of the first light-shielding layer 120 is less than or equal to the width w2 of each light-shielding portion 116, and is used to divide the first pixel row 106 and the first pixel row 106 of the first display panel 100A. The first pixel rows 106 of the second display panel 100B are spaced apart.

In one embodiment, the mosaic display device 10 further includes a motherboard 124 on which the first display panel 100A and the second display panel 100B are located and fixed to the motherboard 124 through an adhesive 126 . The second light-shielding layer 122 is located on the motherboard 124, and the second fan-out line 110 is located on the second light-shielding layer 122. Therefore, even if the current precision of the splicing machine is not enough to achieve the width of the splicing seam 112 to be zero, The splicing seam 112 causes a height difference between the first display panel 100A and the second display panel 100B, and the second light-shielding layer 122 can fill the splicing seam 112 to support the second fan-out line 110 and improve its reliability. . The adhesive 126 can be optical clear adhesive.

FIG. 3 is a schematic top view of a spliced display device 10a according to another embodiment of the present invention. The main difference between the spliced display device 10a in FIG. 3 and the spliced display device 10 in FIG. 1 is that each of the first fan-out lines 108 includes a first branch 108Y, and each first branch 108Y straddles the first branch of the first display panel 100A. One side a1 extends to the first side a1 of the second display panel 100B and extends to the outer pin bonding area 103 of the second display panel 100B. Accordingly, the first pixel row 106 of the first display panel 100A can also be controlled by the second driving element 104B.

In one embodiment, each of the second fan-out lines 110 includes a second branch 110Y, and each second branch 110Y extends to the outer pin bonding area 103 of the second display panel 100B. Accordingly, the first pixel row 106 of the second display panel 100B can also be controlled by the second driving element 104B. In this way, the first pixel rows 106 on the left and right sides of the splicing seam 112 on the first side a1 of the first display panel 100A and the first side a1 of the second display panel 100B can also be controlled by the second driving element 104B. , in other words, controlled by a single external circuit. Adjusting the gray scale (ie brightness) of the first pixel row 106 by a single external circuit can make the seam 112 invisible.

FIG. 4 is a schematic top view of a spliced display device 10b according to another embodiment of the present invention. The main difference between the spliced display device 10b in FIG. 4 and the spliced display device 10 in FIG. 1 is that the pixel array AR of the second display panel 100B also includes a third pixel row 128, and the data line DL also includes a plurality of first pixel rows. Three fan-out lines 130, the third fan-out line 130 is electrically connected to the third pixel row 128 of the second display panel 100B, the third fan-out line 130 spans the first side a1 of the second display panel 100B to the first display panel 100A The first side a1 of the first display panel 100A extends to the outer pin bonding area 103 of the first display panel 100A. Thus, the first pixel row 106 and the third pixel row 128 of the second display panel 100B are controlled by the first driving element 104A. In other words, the leftmost two pixel rows of the second display panel 100B can be controlled by a single external circuit. Adjusting the grayscale (ie brightness) of the first pixel row 106 and the third pixel row 128 by a single external circuit can make the splicing seam 112 invisible. And with such a configuration, the gray levels of multiple pixel rows can be adjusted according to product requirements.

FIG. 5 is a schematic top view of a spliced display device 20 according to another embodiment of the present invention. Fig. 6 is a schematic cross-sectional view along the section line 6-6' of Fig. 5, and the embodiments of Fig. 5 and Fig. 6 follow the component numbers and parts of the embodiments of Fig. 1 to Fig. 2, wherein The same or similar reference numerals denote the same or similar elements, and descriptions of the same technical contents are omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

The spliced display device 20 includes a plurality of display panels 200 . The display panels 200 each have at least one first side a1 facing one of the adjacent display panels 200 and a second side a2 intersecting the first side a1, each display panel 200 has an outer pin bonding area 203, and each display The panel 200 includes a substrate 202, a pixel array AR and a plurality of data lines DL. The pixel array AR is located on the substrate 202, and the outer pin bonding area 203 is located between the pixel array AR and the second side a2. A plurality of data lines DL are located on the substrate 202 and are electrically connected to the pixel array AR. The pixel array AR includes a first pixel row 206, and the first pixel row 206 is adjacent to the first side a1. The display panel 200 includes a first display panel 200A and a second display panel 200B.

The circuit board 208 is disposed on the outer pin bonding area 203 of the first display panel 200A and the outer pin bonding area 203 of the second display panel 200B, the circuit board 208 has a substrate SB and a plurality of pads PD located on the substrate SB, Each pad PD corresponds to the pad 213 of the first display panel 200A and the second display panel 200B. The circuit board 208 has a plurality of wires 210 on the substrate SB. The wires 210 are electrically connected to the first panel of the second display panel 200B. Element row 206, wires 210 cross the first side a1 of the second display panel 200B from the outer pin bonding area 203 of the second display panel 200B to the first side a1 of the first display panel 200A and extend to the outside of the first display panel 200A on the pin land 203 . Thus, the first pixel rows 206 on the left and right sides of the seam 212 on the first side a1 of the first display panel 200A and the first side a1 of the second display panel 200B are all controlled by the first driving element 204A, in other words , controlled by a single drive element. Adjusting the grayscale (ie, brightness) of the first pixel row 206 by a single driving element can make the splicing seam 212 invisible.

The second light-shielding layer 122 is located on the motherboard 224. Therefore, even if the splicing accuracy is not high, the width of the splicing seam 212 is not zero, and the splicing seam 212 causes a gap between the first display panel 200A and the second display panel 200B. Poor, the second light-shielding layer 122 can fill up the splicing seam 212 to support the circuit board 208 and improve its reliability.

In this embodiment, the spliced display device 20 further includes an anisotropic conductive adhesive 214, and the anisotropic conductive adhesive 214 is located between the circuit board 208 and the first display panel 200A, and is located between the circuit board 208 and the second display panel 200B. Between them, it is used to fix the circuit board 208 on the first display panel 200A and the second display panel 200B.

FIG. 7 is a schematic top view of a tiled display device 30 according to an embodiment of the present invention, and FIG. 8 is an enlarged schematic view of a region R in FIG. 7 . Fig. 9 is a schematic cross-sectional view along the section lines 9a-9a' and 9b-9b' in Fig. 8 . The embodiments in Fig. 7 to Fig. 9 continue to use the component numbers and partial contents of the embodiments in Fig. 1 to Fig. 2, wherein the same or similar symbols are used to represent the same or similar components, and the same technical contents are omitted. illustrate. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

The spliced display device 30 includes a motherboard 324 and a plurality of display panels 300 . The motherboard 324 has a supporting substrate 326 and a plurality of wires 328 on the supporting substrate 326 . In one embodiment, the motherboard 324 further includes a plurality of pads 305 located on the wires 328 .

Based on the consideration of conductivity, the material of the wire 328 is metal (such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, alloys of the aforementioned metals, or combinations of the aforementioned metals. stacked layers). However, the present invention is not limited thereto.

The display panels 300 are located on the motherboard 324 and each has at least one first side a1 facing one of the adjacent display panels 300 and a second side a2 intersecting the first side a1, and each display panel 300 has an external pin joint region 303 , and each display panel 300 includes a substrate 302 and a pixel array AR. The substrate 302 has a plurality of conductive vias V. As shown in FIG.

The pixel array AR is located on the substrate 302, the outer pin bonding area 303 is located between the pixel array AR and the second side a2, the pixel array AR includes a first pixel row 306, and the first pixel row 306 is adjacent to the first side a1 , the display panel 300 includes a first display panel 300A and a second display panel 300B.

Each display panel 300 may include a plurality of pads 314, and the pads 314 are located in the outer pin bonding area 303. The data line DL also includes a plurality of first fan-out lines 308 and a plurality of second fan-out lines 310. The pads 314 include The first part 314A is used to connect the second fan-out line 310 to the first driving element 304A. The first portion 314A of the pad 314 overlaps the pad 305 of the motherboard 324 , and the first portion 314A of the pad 314 is electrically connected to the pad 305 of the motherboard 324 through the conductive via V.

The wire 328 crosses the first side a1 of the second display panel 300A from the outer pin bonding area 303 of the second display panel 300B to the first side a1 of the first display panel 300B and extends to the outer pin bonding area of the first display panel 300A. On the region 303 , the wire 328 is electrically connected to the first pixel row 306 of the second display panel 300B through the conductive via V.

For example, the signal of the first driving element 304A is transmitted from the first portion 314A of the pad 314 of the first display panel 300A to the conductive via V and the pad 305 of the motherboard 324 along the arrow 316, and then passes through the pad 305 of the motherboard 324. The wire 328 is then transmitted to the pad 305 and the conductive via V of the motherboard 324, and finally transmitted to the first part 314A of the pad 314 of the second display panel 300B, so that the first pixel row 306 of the second display panel 300B receives signal.

Thus, the first pixel rows 306 on the left and right sides of the seam 312 on the first side a1 of the first display panel 300A and the first side a1 of the second display panel 300B are all controlled by the first driving element 304A, in other words , controlled by a single drive element. Adjusting the gray scale (ie, brightness) of the first pixel row 306 by a single driving element can make the splicing seam 312 invisible.

To sum up, in the spliced display device according to an embodiment of the present invention, the second fan-out line is electrically connected to the first pixel row of the second display panel, and the second fan-out line crosses the first side of the second display panel to the first side of the first display panel and extend to the outer pin bonding area of the first display panel. Thereby, the first pixel rows on the left and right sides of the seam between the first side of the first display panel and the first side of the second display panel can be controlled by a single external circuit. Adjusting the gray scale of the first pixel row by a single external circuit can make the stitching seam invisible.

2-2', 6-6': split line 9a-9a', 9b-9b': broken line 10, 10a, 10b: Mosaic display device 20,30: Mosaic display device 100: display panel 100A: The first display panel 100B: second display panel 102: Substrate 103: Outer pin land 104: drive element 104A: the first driving element 104B: the second driving element 106: The first pixel line 108: The first fan out 108Y: the first branch 110: Second fan outlet 110Y: the second branch 112: stitching seam 113: Pad 113A: Part I 114, 114A, 114B: the second pixel row 116: shading part 118: shading layer 120: the first shading layer 122: the second shading layer 124: motherboard 126: viscose 128: The third pixel line 130: The third fan out 200: display panel 202: Substrate 203: Outer pin land 204A: first driving element 206: The first pixel row 208: circuit board 210: wire 212: stitching seam 214: Anisotropic conductive adhesive 300: display panel 302: Substrate 303: Outer pin land 304A: first driving element 305: Pad 306,306B: the first pixel line 308: The first fan out 310: The second fan out 314: Pad 314A: Part I 316: arrow 324: motherboard 326: supporting substrate 328: wire a1: first side a2: second side AR: pixel array D1: the first direction D2: Second direction DL: data line PD: Pad SB: Substrate V: Conductive Via w1, w2: width

Read the following detailed description and match the corresponding diagrams to understand the multiple aspects of this disclosure. It should be noted that many features in the drawings are not drawn to scale in accordance with standard practice in this industry. In fact, the dimensions of the described features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a schematic top view of a spliced display device according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view along line 2-2' of Fig. 1 . FIG. 3 is a schematic top view of a spliced display device according to another embodiment of the present invention. FIG. 4 is a schematic top view of a spliced display device according to another embodiment of the present invention. FIG. 5 is a schematic top view of a spliced display device according to another embodiment of the present invention. Fig. 6 is a schematic cross-sectional view along line 6-6' of Fig. 5 . FIG. 7 is a schematic top view of a spliced display device according to another embodiment of the present invention. Fig. 8 is an enlarged schematic view of the region R in Fig. 7 . Fig. 9 is a schematic cross-sectional view along the section line 9a-9a' and section line 9b-9b' in Fig. 8.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

2-2': section line

10: Mosaic display device

100: display panel

100A: The first display panel

100B: second display panel

102: Substrate

103: Outer pin land

104: drive element

104A: the first driving element

104B: the second driving element

106: The first pixel row

108: The first fan out

110: Second fan outlet

112: stitching seam

113: Pad

113A: Part I

114, 114A, 114B: the second pixel row

116: shading part

118: shading layer

120: the first shading layer

122: the second shading layer

124: motherboard

a1: first side

a2: second side

AR: pixel array

D1: the first direction

D2: Second direction

DL: data line

w1, w2: width

Claims (10)

A spliced display device, comprising: A plurality of display panels, the display panels include a first display panel and a second display panel, each having at least one first side facing one of the adjacent display panels and a first side intersecting the first side Two sides, wherein each of the display panels has an outer pin land, and each of the display panels includes: a substrate; an array of pixels on the substrate, wherein the outer pin lands are located between the array of pixels and the second side; and A plurality of data lines located on the substrate and electrically connected to the pixel array, wherein the pixel array includes a first pixel row adjacent to the first side, wherein the data lines include: a plurality of first fan-out lines electrically connected to the first pixel row of the first display panel; and A plurality of second fan-out lines electrically connected to the first pixel row of the second display panel, wherein the second fan-out lines cross the first side of the second display panel to the first display panel The first side extends to the outer pin bonding area of the first display panel. The spliced display device according to claim 1, wherein each of the first fan-out lines includes a first branch, and each of the first branches spans from the first side of the first display panel to the side of the second display panel The first side extends to the outer pin bonding area of the second display panel. The spliced display device as claimed in claim 1, wherein each of the second fan-out lines includes a second branch, and each of the second branches extends to the outer pin bonding area of the second display panel. The spliced display device as described in claim 1, wherein each of the pixel arrays further includes a plurality of second pixel rows, and the second pixel rows are located on one side of the first pixel row, and the first display panel The second pixel rows are electrically connected to the outer pin bonding area of the first display panel, and the second pixel rows of the second display panel are electrically connected to the outer pin bonding area of the second display panel. The spliced display device as described in claim 1, wherein the pixel array of the second display panel further includes a third pixel row, and the data lines also include a plurality of third fan-out lines, and the third fan-out lines The outgoing lines are electrically connected to the third pixel row of the second display panel, and the third fan-out lines cross the first side of the second display panel to the first side of the first display panel and extend to the on the outer pin bonding area of the first display panel. The mosaic display device as described in claim 1, further comprising: A plurality of light-shielding parts are respectively located between the adjacent second pixel rows. The mosaic display device as described in claim 6, further comprising: A light-shielding layer covers the first side of the first display panel and the first side of the second display panel, and the width of the light-shielding layer is less than or equal to the width of each of the light-shielding parts. The mosaic display device as described in claim 1, further comprising: A driving element is located on the outer pin bonding area of the first display panel, wherein the second fan-out lines are wire bonded to the driving element. A spliced display device, comprising: A plurality of display panels, the display panels include a first display panel and a second display panel, each having at least one first side facing one of the adjacent display panels and a first side intersecting the first side Two sides, wherein each of the display panels has an outer pin land, and each of the display panels includes: a substrate; an array of pixels on the substrate, wherein the outer pin land is located between the array of pixels and the second side; and a plurality of data lines on the substrate and electrically connected to the pixel array, wherein the pixel array includes a first pixel row adjacent to the first side; and A circuit board, disposed on the outer pin bonding area of the first display panel and the outer pin bonding area of the second display panel, wherein the circuit board has a plurality of wires, and the wires are electrically connected to the first display panel The first pixel row of the second display panel, the wires extend from the outer pin bonding area of the second display panel across the first side of the second display panel to the first side of the first display panel to the outer pin bonding area of the first display panel. A spliced display device, comprising: a motherboard having a support substrate and a plurality of wires on the support substrate; and A plurality of display panels, located on the motherboard and each having at least one first side facing one of the adjacent display panels and a second side intersecting the first side, wherein each of the display panels has an outer pin lands, and each of the display panels includes: a substrate having a plurality of conductive vias; and A pixel array located on the substrate, wherein the outer pin bonding area is located between the pixel array and the second side, the pixel array includes a first pixel row adjacent to the second pixel row On one side, the display panels include a first display panel and a second display panel, the wires are electrically connected to the first pixel row of the second display panel through the conductive vias, and the wires are connected from the first pixel row to the second display panel. The outer pin bonding area of the two display panels spans from the first side of the second display panel to the first side of the first display panel and extends to the outer pin bonding area of the first display panel.

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