TW202234639A - 多高度互連結構及相關系統及方法 - Google Patents

多高度互連結構及相關系統及方法 Download PDF

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TW202234639A
TW202234639A TW111118947A TW111118947A TW202234639A TW 202234639 A TW202234639 A TW 202234639A TW 111118947 A TW111118947 A TW 111118947A TW 111118947 A TW111118947 A TW 111118947A TW 202234639 A TW202234639 A TW 202234639A
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height
die
pillars
conductive pillar
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TW111118947A
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凱爾 K 克比
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美商美光科技公司
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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Abstract

本文中提供用於一半導體裝置之多高度互連結構之系統及方法。該多高度互連結構通常包括具有一初級導電柱及一次級導電柱之一初級層級半導體晶粒，其中該初級導電柱相比於該次級導電柱具有一較大高度。該半導體裝置可進一步包括：一基板，其經由該初級導電柱電耦接至該初級層級半導體晶粒；及一次級層級半導體晶粒，其經由該次級導電柱電耦接至該初級層級半導體晶粒。可使用單一光阻遮罩或多個光阻遮罩形成該等多高度柱。在一些組態中，該初級導電柱及該次級導電柱可僅配置於該等晶粒及/或該基板之正面上。

Description

多高度互連結構及相關系統及方法
本發明大體上係關於半導體裝置，且在若干實施例中，更特定地係關於形成用於晶粒至晶粒、晶粒至基板及/或三維積體電路互連之多高度互連結構之系統及方法。
諸如記憶體裝置、微處理器及發光二極體之微電子裝置通常包括安裝至基板且包覆於保護性覆蓋物中之一或多個半導體晶粒。半導體晶粒包括功能特徵，諸如記憶體胞元、處理器電路、互連電路系統等等。半導體晶粒製造商面臨著愈來愈大的壓力來減小由半導體晶粒佔據之體積，同時增加所得經囊封總成之容量及/或速度。為了滿足此等及其他需求，半導體晶粒製造商常常將多個半導體晶粒豎直地堆疊於彼此頂部上，以增加安裝有半導體晶粒之電路板或其他元件上的有限體積內之微電子裝置的容量或效能。在豎直半導體晶粒堆疊總成中，矽通孔(TSV)常常用以進行通過晶粒之電連接。
個別或堆疊式半導體晶粒通常經由基板上之晶粒或跡線上之金屬接合襯墊在具有不同大小之焊球的晶粒至多晶粒(D2MD)或晶粒至基板(D2S)組態處電耦接。運用在接合襯墊上形成之柱來進行一些晶粒至晶粒(D2D)互連。在組裝期間，回焊柱之端上之焊球及/或焊料凸塊以自D2D、D2MD及D2S電連接形成連接。使用不同大小之焊球的習知組裝方法限制可能的晶粒組態。
本發明之一個態樣係關於一種半導體裝置，其包含：一初級層級半導體晶粒，其具有一初級導電柱及一次級導電柱，該初級導電柱相比於該次級導電柱具有一較大高度；一基板，其藉由該初級導電柱電耦接至該初級層級半導體晶粒；及一次級層級半導體晶粒，其經由該次級導電柱電耦接至該初級層級半導體晶粒，其中基於該初級導電柱及該次級導電柱之該高度，該初級層級半導體晶粒與該基板之間的距離大於該初級層級半導體晶粒與該次級層級半導體晶粒之間的距離。
本發明之另一態樣提供一種用於在一半導體晶粒上形成多高度導電柱之方法，該方法包含：將一第一光阻遮罩施加至該半導體晶粒之一表面，該光阻遮罩具有經組態以部分地形成一初級導電柱之一第一抗蝕劑開口及經組態以形成一次級導電柱之一第二抗蝕劑開口；藉由一電化學鍍敷製程通過該第一抗蝕劑開口將金屬電化學地鍍敷至該半導體晶粒上以將該初級導電柱部分地形成至一第一高度，且通過該第二抗蝕劑開口將金屬電化學地鍍敷至該半導體晶粒上以將該次級導電柱形成至該第一高度；自該半導體晶粒移除該第一光阻遮罩以曝露該部分初級導電柱及該次級導電柱；將一第二光阻遮罩施加至覆蓋該次級導電柱的該半導體晶粒之該表面，該光阻遮罩具有與該部分初級柱對準且經組態以部分地形成該初級導電柱之一第三抗蝕劑開口；藉由一電化學鍍敷製程通過該第三抗蝕劑開口將金屬電化學地鍍敷至該半導體晶粒上以將該初級導電柱部分地形成至大於該第一高度的一第二高度；及自該半導體晶粒移除該第二光阻遮罩以曝露延伸至該第二高度的該初級導電柱及延伸至該第一高度的該次級導電柱。
本發明之另一態樣係關於一種製造具有多高度導電柱之一半導體總成之方法，其包含：將一第一光阻遮罩施加至一第一半導體晶粒之一表面，該光阻遮罩具有經組態以形成一初級導電柱之一第一抗蝕劑開口及經組態以形成一次級導電柱之一第二抗蝕劑開口；藉由一電化學鍍敷製程通過該第一抗蝕劑開口將金屬電化學地鍍敷至該第一半導體晶粒上以將該初級導電柱形成至一第一高度，且通過該第二抗蝕劑開口將金屬電化學地鍍敷至該第一半導體晶粒上以將該次級導電柱形成至一第二高度；自該第一半導體晶粒移除該第一光阻遮罩以曝露該部分初級導電柱及該次級導電柱；經由該等初級柱將該第一半導體晶粒電耦接至一基板；及經由該等次級柱將該第一半導體晶粒電耦接至一第二半導體晶粒。
本文中所揭示之技術係關於半導體裝置、具有半導體裝置之系統，及用於製造半導體裝置之相關方法。術語「半導體裝置」通常係指包括一或多種半導體材料之固態裝置。半導體裝置之實例包括邏輯裝置、記憶體裝置及二極體等等。此外，術語「半導體裝置」可指成品裝置或在變為成品裝置之前的各種處理階段時的總成或其他結構。
取決於術語「基板」被使用之上下文，該術語可指支撐電子組件(例如晶粒)之結構，諸如晶圓級基板、單體化晶粒級基板，或用於晶粒堆疊應用之另一晶粒。一般熟習相關技術者將認識到，本文中所描述之方法之合適步驟可在晶圓級下或在晶粒級下執行。此外，可使用習知半導體製造技術形成本文中所揭示之結構，除非上下文另有指示。可例如使用化學氣相沈積、物理氣相沈積、原子層沈積、旋塗、鍍敷及/或其他合適技術來沈積材料。相似地，可例如使用電漿蝕刻、濕式蝕刻、化學機械平坦化或其他合適技術來移除材料。
本發明技術包括由單一晶粒上之不同長度(例如高度)之柱界定以實現同時D2D、D2MD及/或D2S連接的多高度互連結構。與本發明技術對比，當大小及間隔不允許用於焊球之直徑之互連件之間的餘隙時，尤其係隨著半導體組件之間的間隔增大，具有不同大小之焊球的習知半導體裝置封裝限制半導體封裝之組態，從而需要較大直徑之焊球及接合襯墊之間的對應較大空間。在其他習知組態中，焊球之使用可限制製造製程選項，且可能需要TSV及背面處理。隨著晶粒之大小及間隔變得愈來愈緊密，多高度柱允許在將半導體組件互連的同時使接合襯墊間隔較接近。
多高度柱可用於薄晶粒(通常具有低於150微米之晶圓厚度)、超薄晶粒(通常具有低於50微米之晶圓厚度)及超薄接合線(通常具有低於15微米之接合厚度)多晶片封裝(MCP)應用以及其他應用中。此類MCP應用中之晶粒厚度及間隔產生短分離距離，使得柱可用以形成某些D2D、D2MD及D2S電連接。在一些實施例中，連接至PCB或其他組件之基板或最下部晶粒仍可使用焊球連接；然而，焊球可太寬而不能用於某些組態中。圖1A至圖3所繪示之柱組態係例示性的，且所展示及描述之柱可具有不同高度以產生晶粒與基板之間的所要間隔組態，或可具有不同寬度及/或數量。
圖1A及圖1B展示具有電連接D2D、D2MD及D2S組態之多高度柱之半導體裝置總成100 (「裝置100」)。裝置100包括使用焊球112電耦接至諸如印刷電路板(PCB) 150之組件之基板110。裝置100包括直接或間接電耦接至基板110之多個半導體晶粒。在所繪示之實施例中，裝置100具有初級層級晶粒120、次級層級晶粒130及三級層級晶粒140 (由參考編號140a、140b及140c個別地識別)。裝置100具有將初級層級晶粒120電耦接至基板110之初級柱122，及將次級層級晶粒130電耦接至初級層級晶粒120之次級柱132。如所展示，第一柱122及第二柱132具有不同高度，使得初級層級晶粒120可形成至基板110 (D2S)及次級層級晶粒130 (D2D)兩者之電連接，兩者均具有與初級層級晶粒120不同之間隔組態。
裝置100亦可包括三級柱142以將三級層級晶粒140a-c電連接至次級層級晶粒130 (D2D)。第三柱142可具有恆定高度以用於在次級層級晶粒130與三級層級晶粒140a-c之間形成連接，使得三級層級晶粒140a-c全部與次級層級晶粒130隔開相同距離。
次級柱132可取決於製造製程及/或設計偏好而形成於初級層級晶粒120或次級層級晶粒130上。在次級柱132形成於次級層級晶粒130上之實施例中，次級柱132及三級柱142在D2MD組態中形成電連接，其中次級層級晶粒130電耦接至初級層級晶粒120及三級層級晶粒140a-c兩者。初級柱122、次級柱132及三級柱142分別具有合適長度及寬度以形成電連接且提供裝置100之組件之間的所要間隔。在圖1A中，初級柱122可形成於基板110之正面上，次級柱132可形成於初級層級晶粒120之正面上，且三級柱142可形成於第三晶粒140a-c之正面上。在此配置中，焊球112經由基板110之背面將第一基板110電耦接至PCB 150。
圖2展示相比於裝置100呈不同配置之半導體裝置總成200 (「裝置200」)，其具有電連接D2D、D2MD及D2S組態之多高度柱。在裝置200中，基板110使用焊球112電耦接至PCB 150。裝置200亦包括直接或間接電耦接至基板110之多個半導體晶粒。裝置200與圖1A中所展示之裝置100不同之處在於，裝置200具有第一及第二次級層級晶粒130a、130b以及兩種不同類型之三級層級晶粒140a-b及240。舉例而言，三級層級晶粒140a-b可界定第一類型之三級晶粒，且三級層級晶粒240可界定第二類型之三級晶粒。類似參考編號係指圖1A至圖2中之相似特徵，但該等特徵可不同且具有不同大小。
裝置200亦包括如上文關於裝置100所描述用於將初級層級晶粒120電耦接至基板110之初級柱122，但裝置200之初級柱122長於裝置100之初級柱。初級層級晶粒120亦(a)藉由第一次級柱132電耦接至第一次級層級晶粒130a，及(b)藉由短於第一次級柱132之第二次級柱134電耦接至第二次級層級晶粒130b。
三級層級晶粒140a-b藉由第一三級柱142電耦接至第一次級層級晶粒130a，可使用正面處理技術形成該等第一三級柱。三級層級晶粒140a亦藉由穿過第二次級層級晶粒130b之TSV 148直接耦接至初級層級晶粒120。三級層級晶粒140b藉由第二三級柱144耦接至第二次級晶粒130b。因而，裝置200之第二次級層級晶粒130b可包括用於D2MD連接之正面及背面處理。
在裝置200之所繪示組態中，初級層級晶粒120藉由多層級柱146進一步電耦接至三級層級晶粒240。就此而言，初級層級晶粒120經由初級柱122形成D2S電連接；分別經由第一次級柱、第二次級柱及多層級柱132、134及146形成D2MD電連接；及經由TSV 148形成D2D電連接。
圖3展示半導體裝置總成300 (「裝置300」)，其具有電連接具有全正面處理之多板面晶片(COB)組態之多高度柱。裝置300包括基板，該基板具有使用焊球112電耦接至PCB 150之第一基板部分110a及第二基板部分110b。基板亦可在第一及第二基板部分110a-b之間具有孔隙170，互連件可穿過該孔隙。儘管圖3展示具有孔隙170之單一基板或PCB，但對於等效功能性，其他實施例可具有之間具有間隙之分離的第一基板及第二基板。第一及第二基板部分110a-b具有正面111及背面113。裝置300進一步包括第一COB 160a及第二COB 160b。第一COB 160a藉由初級柱162電耦接至第一及第二基板100a-b兩者，且第二COB 160b藉由次級柱164電耦接至第一COB 160a。在此實施例中，次級柱164電耦接至第一COB 160a之正面及第二COB 160b之正面。裝置300之配置允許沒有TSV或背面處理之多COB組態。
本發明技術包括優於使用不同大小之焊球的習知晶粒堆疊技術的若干優點。在一些實施例中，本發明技術之多高度柱組態使能夠僅運用正面處理來堆疊兩種或多於兩種不同類型之晶粒。對於此類組態，習知技術需要TSV及/或背面處理。另外，本發明技術提供(a)較短封裝及堆疊高度、(b)較緊密間距、(c)較快製造，及(d)較大數目個組態及應用。所繪示實施例描繪使用本發明技術之多高度柱組態的半導體裝置之若干實例；然而，具有多高度柱之另外裝置組態係在本發明技術之範疇內。
多高度柱可由諸如銅(Cu)之合適導電材料形成，且具有用以形成電連接之焊料蓋(例如錫銀(SnAg)焊料蓋)。在組裝期間，使用成組回焊、音波回焊或其他技術來回焊焊料蓋。多高度柱可形成於單一晶粒上。取決於柱高度差，可使用多種遮罩處理技術形成具有大高度差之多高度柱。然而，若多高度柱之高度差微小，則可使用直徑變化之抗蝕劑開口之單一遮罩。形成柱之接合襯墊通常為銅襯墊，使得銅柱使用銅至銅接合而耦接至接合襯墊。在其他實施例中，多高度柱可由與接合襯墊不同之材料形成，或可由材料之組合形成。將參考圖4A至圖5C描述用於使用直徑變化之抗蝕劑開口之單一光阻遮罩及/或多種光阻遮罩處理技術形成多高度柱的方法。
圖4A及圖4B展示使用單一光阻遮罩形成多高度柱之一個組態的放大平面圖及橫截面圖。光阻遮罩480可包括初級抗蝕劑開口482，及相比於初級抗蝕劑開口482具有較小直徑之次級抗蝕劑開口484。光阻遮罩480遮蔽除將形成柱之部分以外的晶粒表面之部分。在將光阻遮罩480施加至晶粒之後，將金屬電化學地鍍敷至初級抗蝕劑開口482及次級抗蝕劑開口484上以分別形成初級柱422及次級柱432。初級抗蝕劑開口482與次級抗蝕劑開口484之間的不同直徑使不同速率之金屬通過初級抗蝕劑開口482及次級抗蝕劑開口484而沈積。此在初級柱422與次級柱432之間產生不同高度。接著自晶粒移除光阻遮罩480以曝露初級柱422及次級柱432，如圖4B中所展示。相比於次級柱432，初級柱422自基板410延伸至較大高度，此可用以形成圖1A中所展示之初級柱122及次級柱132，以及其他可能的多高度柱組態。
圖5A至圖5C展示使用多個光阻遮罩形成多高度柱之一個組態的放大平面圖及橫截面圖。如圖5A中所展示，第一光阻遮罩580可包括通常具有相等直徑之第一抗蝕劑開口582。在將第一光阻遮罩580施加至晶粒之後，將金屬電化學地鍍敷至第一抗蝕劑開口582上以分別形成部分初級柱523及次級柱532。就此而言，第一抗蝕劑開口582可經組態以將部分初級柱523形成至以虛線所展示之中間高度(參見圖5C)。在使用第一光阻遮罩580鍍敷金屬之後，部分初級柱523及次級柱532具有實質上相等高度，其中部分初級柱523之中間高度與次級柱532之高度實質上相同。接著自晶粒移除第一光阻遮罩580以在中間高度處曝露部分初級柱523且在完全高度處曝露次級柱522。
接下來，如圖5B中所展示，第二光阻遮罩590可包括與使用第一光阻遮罩580而形成之部分初級柱523對準的第二抗蝕劑開口586。如所展示，可不存在與次級柱532對準之抗蝕劑開口，使得無其他金屬沈積於次級柱532上。第二抗蝕劑開口586之直徑可相似於或不同於第一抗蝕劑開口582之直徑。在將第二光阻遮罩590施加至晶粒之後，將金屬電化學地鍍敷至第二抗蝕劑開口586中以繼續形成初級柱522，從而相比於次級柱532將部分初級柱523延伸至較大高度，如圖5C中所展示。初級柱522相比於次級柱532自基板510延伸至較大高度，且相比於使用單一光阻遮罩而製成之初級柱422及次級柱432通常可具有較大高度差。在一個實例中，運用多個光阻遮罩可能產生之較大高度差可用以形成圖3中所展示之初級柱162及次級柱164，以及其他可能的多高度柱組態。
圖6係繪示併有根據本發明技術之實施例之半導體裝置之系統的方塊圖。具有上文參考圖1A至圖5C所描述之特徵的半導體裝置中之任一者可併入至多種較大及/或較複雜系統中之任一者中，其代表性實例為在圖6中示意性地所展示之系統600。系統600可包括處理器602、記憶體604 (例如SRAM、DRAM、快閃記憶體及/或其他記憶體裝置)、輸入/輸出裝置606，及/或其他子系統或組件608。上文參考圖1A至圖5C所描述之半導體總成、裝置及裝置封裝可包括於圖6中所展示之元件中之任一者中。所得系統600可經組態以執行廣泛多種合適計算、處理、儲存、感測、成像及/或其他功能中之任一者。因此，系統600之代表性實例包括但不限於電腦及/或其他資料處理器，諸如桌上型電腦、膝上型電腦、網際網路設備、手持型裝置(例如掌上型電腦、可穿戴式電腦、蜂巢式或行動電話、個人數位助理、音樂播放器等等)、平板電腦、多處理器系統、基於處理器之或可程式化消費型電子裝置、網路電腦，及小型電腦。系統600之額外代表性實例包括燈、攝影機、車輛等等。在此等及其他實例中，系統600可容納於單一單元中或例如經由通信網路遍及多個互連單元而分佈。系統600之組件可因此包括本端及/或遠端記憶體儲存裝置，及廣泛多種合適電腦可讀媒體中之任一者。
如前述描述中所使用，術語「豎直」、「橫向」、「上部」及「下部」可指鑒於諸圖中所展示之定向的半導體裝置中之特徵之相對方向或位置。舉例而言，「上部」或「最上部」可指相比於另一特徵較接近頁面之頂部而定位的特徵。然而，此等術語應被廣泛地解釋為包括具有諸如反向或傾斜定向之其他定向之半導體裝置，其中可取決於定向而互換頂部/底部、之上/之下、上方/下方、向上/向下、左/右及遠側/近側。此外，為了易於參考，在整個本發明中使用相同參考編號來識別相似或類似組件或特徵，但使用相同參考編號並不暗示特徵應被解釋為相同。實際上，在本文中所描述之許多實例中，相同編號之特徵具有在結構及/或功能上彼此不同之複數個實施例。此外，相同陰影可用以指示可在組成上相似之橫截面中的材料，但使用相同陰影並不暗示該等材料應解釋為相同，除非本文中有特定指出。
前述揭示內容亦可參考數量及數目。除非有特定陳述，否則此類數量及數目不應被視為限制性的，而是例示與新技術相關之可能數量或數目。又，就此而言，本發明可使用術語「複數個」來參考數量或數目。就此而言，術語「複數個」意謂多於一個之任何數目，例如兩個、三個、四個、五個等等。出於本發明之目的，片語「A、B及C中之至少一者」例如意謂(A)、(B)、(C)、(A及B)、(A及C)、(B及C)或(A、B及C)，當列出多於三個元件時包括所有其他可能的排列。
自前文應瞭解，本文中已出於說明之目的而描述新技術之特定實施例，但可在不偏離本發明之情況下進行各種修改。因此，本發明不受除隨附申請專利範圍以外的內容限制。此外，在其他實施例中，亦可組合或消除在特定實施例之上下文中所描述的新技術之某些態樣。此外，儘管與新技術之某些實施例相關之優點已在彼等實施例之上下文中予以描述，但其他實施例亦可展現此類優點，且並非所有實施例必定需要展現屬於本發明之範疇內的此類優點。因此，本發明及相關技術可涵蓋未在本文中明確地展示或描述之其他實施例。
1B:圖 4B:圖 5C:圖 100:半導體裝置總成 110:基板 110a:第一基板部分 110b:第二基板部分 111:正面 112:焊球 113:背面 120:初級層級晶粒 122:初級柱 130:次級層級晶粒 130a:第一次級層級晶粒 130b:第二次級層級晶粒 132:次級柱 134:第二次級柱 140a:初級層級晶粒 140b:次級層級晶粒 140c:三級層級晶粒 142:第一三級柱 144:第二三級柱 146:多層級柱 148:矽通孔(TSV) 150:印刷電路板(PCB) 160a:第一板面晶片(COB) 160b:第二板面晶片(COB) 162:初級柱 164:次級柱 170:孔隙 200:半導體裝置總成 240:三級層級晶粒 300:半導體裝置總成 410:基板 422:初級柱 432:次級柱 480:光阻遮罩 482:初級抗蝕劑開口 484:次級抗蝕劑開口 510:基板 522:次級柱 523:初級柱 532:次級柱 580:第一光阻遮罩 582:第一抗蝕劑開口 586:第二抗蝕劑開口 590:第二光阻遮罩 600:系統 602:處理器 604:記憶體 606:輸入/輸出裝置 608:其他子系統或組件
圖1A係展示根據本發明技術之實施例而組態的具有多高度互連結構之半導體裝置的放大橫截面圖。
圖1B係展示圖1A之半導體裝置之放大部分的細節視圖。
圖2係展示根據本發明技術之另一實施例而組態的具有多高度互連結構之半導體裝置的放大橫截面圖。
圖3係展示根據本發明技術之另一實施例而組態的具有多高度互連結構之多板面晶片(COB)半導體裝置的放大橫截面圖。
圖4A係展示根據本發明技術之另一實施例而組態的具有直徑不同之初級抗蝕劑開口及次級抗蝕劑開口之光阻遮罩的放大平面圖。
圖4B係具有使用圖4A之光阻遮罩而形成之多高度互連結構之半導體裝置的橫截面圖。
圖5A及圖5B係展示根據本發明技術之另一實施例而組態的具有第一抗蝕劑開口及第二抗蝕劑開口之第一光阻遮罩及第二光阻遮罩的放大平面圖。
圖5C係具有使用圖5A及圖5B之光阻遮罩而形成之多高度互連結構之半導體裝置的橫截面圖。
圖6係包括根據本發明技術之實施例而組態之半導體裝置之系統的示意圖。
1B:圖
100:半導體裝置總成
110:基板
112:焊球
120:初級層級晶粒
122:初級柱
130:次級層級晶粒
132:次級柱
140a:初級層級晶粒
140b:次級層級晶粒
140c:三級層級晶粒
142:第一三級柱
150:印刷電路板(PCB)

Claims (4)

  1. 一種用於在一半導體晶粒上形成多高度導電柱之方法，該方法包含： 將一第一光阻遮罩施加至該半導體晶粒之一表面，該光阻遮罩具有經組態以部分地形成一初級導電柱之一第一抗蝕劑開口及經組態以形成一次級導電柱之一第二抗蝕劑開口； 藉由一電化學鍍敷製程通過該第一抗蝕劑開口將金屬電化學地鍍敷至該半導體晶粒上以將該初級導電柱部分地形成至一第一高度，且通過該第二抗蝕劑開口將金屬電化學地鍍敷至該半導體晶粒上以將該次級導電柱形成至該第一高度； 自該半導體晶粒移除該第一光阻遮罩以曝露該部分初級導電柱及該次級導電柱； 將一第二光阻遮罩施加至覆蓋該次級導電柱的該半導體晶粒之該表面，該光阻遮罩具有與該部分初級柱對準且經組態以部分地形成該初級導電柱之一第三抗蝕劑開口； 藉由一電化學鍍敷製程通過該第三抗蝕劑開口將金屬電化學地鍍敷至該半導體晶粒上以將該初級導電柱部分地形成至大於該第一高度的一第二高度；及 自該半導體晶粒移除該第二光阻遮罩以曝露延伸至該第二高度的該初級導電柱及延伸至該第一高度的該次級導電柱。
  2. 如請求項1之方法，其中該第一抗蝕劑開口及該第二抗蝕劑開口具有相等直徑。
  3. 如請求項2之方法，其中： 該第一光阻遮罩進一步包含經組態以形成一三級導電柱之一第四抗蝕劑開口；且 該方法進一步包含藉由一電化學鍍敷製程通過該第四抗蝕劑開口將金屬電化學地鍍敷至該半導體晶粒上以將該三級導電柱形成至小於該第一高度及該第二高度的一第三高度。
  4. 如請求項3之方法，其中該第四抗蝕劑開口相比於該第一抗蝕劑開口及該第二抗蝕劑開口具有一較小直徑。
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