TW202234591A - 高效能3d垂直電晶體裝置的改善設計 - Google Patents

高效能3d垂直電晶體裝置的改善設計 Download PDF

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TW202234591A
TW202234591A TW111102354A TW111102354A TW202234591A TW 202234591 A TW202234591 A TW 202234591A TW 111102354 A TW111102354 A TW 111102354A TW 111102354 A TW111102354 A TW 111102354A TW 202234591 A TW202234591 A TW 202234591A
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channel
transistor
epitaxial
forming
shell
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TW111102354A
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馬克 Ｉ 加德納
Ｈ 吉姆 富爾福德
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日商東京威力科創股份有限公司
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Abstract

一種微製造的電晶體裝置包含半導體基板上之場效電晶體的二或更多通道的垂直堆疊體。該等通道之各者具有相對於該半導體基板之表面的一垂直導電路徑。該等通道中之至少一者包含圍繞芯部材料形成的殼層，該殼層包含磊晶材料。該垂直堆疊體可包括用於PMOS場效電晶體的通道及用於NMOS場效電晶體的通道。

Description

高效能3D垂直電晶體裝置的改善設計
本發明係關於包括半導體裝置、電晶體、及積體電路之微電子裝置，包括微製造方法。 [相關申請案之交互參照]
本申請案主張2021年1月26日提交的美國臨時申請案第63/141,551號、及2021年9月30日提交的非臨時申請案第17/490,182號的優先權，在此將其全部內容引入以供參照。
在半導體裝置之製造中(尤其是在微小尺度上)，可執行諸多製造製程，例如成膜沉積、蝕刻遮罩形成、圖案化、材料蝕刻與去除、以及摻雜處理。可重複執行此些製程以在基板上形成所欲半導體裝置元件。歷史上，利用微製造，已在一平面中形成電晶體，且佈線/金屬化形成於主動裝置平面上方，因此已被表徵為二維(2D)電路或2D製造。微縮方面的努力已大幅增加2D電路中每單位面積電晶體的數量，但隨著微縮進入個位數奈米半導體裝置製造節點，微縮方面的努力正面臨更大的挑戰。半導體裝置製造商已表達對電晶體彼此堆疊之三維(3D)半導體電路的需求。
第一例示性態樣為一種形成電晶體裝置的方法，其包含：提供具有膜層堆疊體的基板，該膜層堆疊體包含由一中間層所分隔的複數半導體通道層；由該複數半導體通道層分別形成複數芯部通道結構，該複數芯部通道結構各自具有相對於該基板之表面的一垂直導電路徑，並且包含垂直堆疊在該基板上且被由該中間層形成之隔離結構所分隔的第一及第二芯部通道結構；以及在該第一芯部通道結構周圍形成第一磊晶殼層，使得該第一磊晶殼層形成待由該第一芯部通道結構形成之第一電晶體之第一電晶體通道的至少一部分。
第二例示性態樣更包含：在該第一磊晶殼層上形成第一源極/汲極(S/D)區域及第一閘極結構以完成該第一電晶體；以及在該等芯部通道結構中之第二者上形成第二S/D區域及第二閘極結構，以完成在該基板上與該第一電晶體垂直堆疊的第二電晶體，其中該第一電晶體的該第一電晶體通道包含該第一磊晶殼層，且該第二電晶體的第二電晶體通道係由該第二芯部通道結構製成。
第三例示性態樣為其中形成第一磊晶殼層之步驟包含利用與該第一芯部通道結構相同的材料形成第二磊晶殼層，使得該第一及第二電晶體具有相同的導電性類型。
第四例示性態樣為其中形成第一磊晶殼層之步驟包含利用與該第一芯部通道結構不同的材料形成第二磊晶殼層，使得該第一及第二電晶體具有不同的導電性類型。
第五例示性態樣更包含：在該等芯部通道結構中之第二者周圍形成第二磊晶殼層，使得該第二磊晶殼層形成待由該第二芯部通道結構形成之第二電晶體之第二電晶體通道的至少一部分；以及分別在該第一及第二磊晶殼層之各者上形成第一源極/汲極(S/D)區域及閘極結構以完成第一及第二相應電晶體。
第六例示性態樣為其中形成第二磊晶殼層之步驟包含利用與該第一磊晶殼層相同的材料形成該第二磊晶殼層，使得該第一及第二電晶體具有相同的導電性類型。
第七例示性態樣為其中形成第二磊晶殼層之步驟包含利用與該第一磊晶殼層不同的材料形成該第二磊晶殼層，使得該第一及第二電晶體具有不同的導電性類型。
第八例示性態樣為其中提供具有膜層堆疊體的基板之步驟包含：在該基板上磊晶式地生長該複數半導體通道層的第一半導體通道層；在該第一半導體通道層上磊晶式地生長該中間層；以及在該中間層上磊晶式地生長該複數半導體通道層的半導體通道層。
第九例示性態樣更包含藉由利用介電材料替代該中間層而形成該隔離結構。
第十例示性態樣為其中提供具有膜層堆疊體的基板之步驟包含：提供第一基板，該第一基板具有形成於該第一基板之第一絕緣層上之該複數半導體通道層的第一半導體通道層；提供第二基板，該第二基板具有形成於該第二基板之第二絕緣層上之該複數半導體通道層的第二半導體通道層；以及將該第一絕緣層晶圓接合至該第二絕緣層以形成具有該膜層堆疊體的組合式基板，該膜層堆疊體包含由形成該中間層之接合的該第一及第二絕緣層所分隔的該複數半導體通道層。
第十一例示性態樣為其中提供基板之步驟包含提供具有包括多個半導體通道層之膜層堆疊體的基板，該多個半導體通道層係經由相應的中間層而彼此分隔開；並且形成複數芯部通道結構之步驟包含分別由該多個半導體通道層形成多個芯部通道結構，該多個芯部通道結構各自具有相對於該基板之表面的一垂直導電路徑，並且包含該第一及第二芯部通道結構以及至少一個第三通道結構，該至少一個第三通道結構係垂直堆疊在該基板上且被由相應的該中間層形成的隔離結構所分隔，其中各個隔離結構係由晶圓接合界面或替代該中間層的替代性絕緣材料所形成。
第十二例示性態樣為一種電晶體裝置的微製造方法，該方法包含：由膜層堆疊體在一基板上形成通道結構，該等通道結構各自具有相對於該基板之表面的一垂直導電路徑，該等通道結構包括二或更多通道結構階層的垂直堆疊體；以及藉由磊晶生長而在該等通道結構階層之至少一者中圍繞通道結構形成殼層，使得該等殼層之各者為待於該等通道結構階層之該至少一者中形成的對應電晶體之相應電晶體通道的一部分。
第十三例示性態樣為其中形成殼層之步驟包含：利用介電質覆蓋一或更多第一通道結構階層，而一或更多第二通道結構階層未經覆蓋；以及自該一或更多第二通道結構階層形成該等殼層以成為圍繞各個未經覆蓋之通道結構的第一殼層，該等第一殼層係各自藉由磊晶生長而形成，且為待形成之對應電晶體的電晶體通道結構的一部分。
第十四例示性態樣更包含：覆蓋該等第一殼層，且使該一或更多第一通道結構階層露出；以及自該一或更多第一通道結構階層形成圍繞未經覆蓋之通道結構的第二殼層，該等第二殼層之各者係藉由磊晶生長而形成，且為待形成之對應電晶體的相應電晶體通道結構的一部分。
第十五例示性態樣為其中形成殼層之步驟包含：藉由磊晶生長而在該等通道結構階層之各者中圍繞各個通道結構形成殼層，使得該等殼層之各者為待形成之對應電晶體的相應電晶體通道的一部分；利用介電質覆蓋一或更多第一通道結構階層，而一或更多第二通道結構階層未經覆蓋；以及從該一或更多第二通道結構階層的通道結構去除該等殼層。
第十六例示性態樣更包含藉由磊晶生長及接合二或更多晶圓之其中至少一者以形成該膜層堆疊體。
第十七例示性態樣為一種微製造的電晶體裝置，其包含半導體基板上之場效電晶體的二或更多通道的垂直堆疊體，該等通道之各者具有相對於該半導體基板之表面的一垂直導電路徑，該等通道中之至少一者包含圍繞芯部材料形成的殼層，該殼層包含磊晶材料。
第十八例示性態樣為其中該等通道之各者包含圍繞芯部材料形成的殼層，該等殼層之各者包含磊晶材料。
第十九例示性態樣為其中該垂直堆疊體的該二或更多通道係經由一隔離體而彼此分隔。
第二十例示性態樣為其中該垂直堆疊體包括用於PMOS場效電晶體的通道及用於NMOS場效電晶體的通道。
應注意，此發明內容之章節並未指明本發明或申請專利範圍之所有實施例及/或漸增之新穎態樣。而應為，此發明內容僅提供相對於習知技術的不同實施例及新穎性對應點的初步討論。關於本發明及實施例之額外的細節及/或可能的觀點，讀者將被導向如下進一步討論之本發明的實施方式之章節及對應之圖式。
如本文所述之不同步驟的討論順序已基於清楚目的來呈現。一般而言，此些步驟可依任何合適的順序來執行。另外，雖然本文之每一不同特徵、技術、配置等可能在本發明不同地方進行討論，但其用意為每一概念可彼此獨立地或彼此組合來執行。據此，可以許多不同方式來具體實施並概觀本發明。
雖然2D半導體技術正臨近3 nm節點(且可能臨近2 nm節點)，但3D半導體技術因更小的覆蓋面積而提供高效能。3D整合(亦即，多個裝置的垂直堆疊)的目標在於藉由增加電晶體在體積上(而非面積上)的密度而克服在平面裝置中所遭遇的微縮限制。雖然隨著3D NAND的採用，快閃記憶體產業已成功演示和實施裝置堆疊，但應用在隨機邏輯設計係明顯更為困難的。正尋求邏輯晶圓(CPU(中央處理器)、GPU(圖形處理單元)、FPGA(現場可程式閘陣列)、SoC(系統單晶圓))的3D 整合。
本文之技術包括用於形成垂直通道電晶體之有成本效益的處理，其中該等垂直通道電晶體具有透過磊晶生長的殼層。從3D電晶體的通用半導體芯部開始，磊晶材料係選擇性地垂直生長，從而產生最佳的材料通道結構。此技術提供顯著的遷移率提升，因為對於垂直堆疊的NMOS及PMOS裝置而言，各個通道的材料類型可能有所不同。在為各個晶圓生長3D垂直奈米片之後，本文可使用兩個或更多個接合的晶圓。這在將3D電晶體圖案化之前提供了360度旋轉對稱性(亦即，對於對齊公差沒有限制)。本文之技術可用於3D並列式CMOS及CFET CMOS設計兩者。此外，可實現並列和CFET的組合、以及垂直堆疊體中的一對電晶體或許多電晶體之堆疊體。本文的磊晶殼層/芯部可用於定制垂直通道的區段以滿足各個區段的裝置需求。範例包括本文所揭示的許多元素，但許多另外的組合亦係可能的。本文之裝置對於磊晶殼層沒有厚度限制，因為針對垂直奈米片形成360度通道。此外，利用該等技術能實現垂直通道之複數區段之間的穩健且垂直的擴散中斷。
本文之具有磊晶(epi)殼層之電晶體的技術包括許多例示實施例。這使得能夠以降低的成本生產更高密度的電路。藉由從3D電晶體之通用半導體芯部開始，可選擇性地垂直(相對於晶圓表面)生長磊晶殼層(或磊晶殼層之堆疊體)，以產生最佳的材料通道結構。這可提供顯著的遷移率提升，因為材料類型係針對NMOS及PMOS裝置而加以最佳優化。擴散中斷及隔離係利用在z方向上相隔開的垂直奈米片而實現。在無需使用晶圓堆疊體之間的精確對準之情況下實現360度對稱(亦即，使用奈米片的晶圓堆疊體)。
圖1及圖2顯示根據本揭示內容之例示性態樣的垂直3D電晶體堆疊體的一個範例。圖1顯示具有一個第一材料之磊晶殼層及另一個第二材料之磊晶殼層的垂直場效電晶體之剖視圖。圖2為圖1之結構的俯視平面圖。例示性結構包括位在具有介電層104之基板102上的兩個相鄰的垂直3D電晶體堆疊體101a及101b。在圖1及2的範例中，堆疊體101a及101b之各者具有相同的結構。出於說明之目的，僅描述電晶體堆疊體101b。
如圖所示，電晶體堆疊體101b包括經由垂直隔離(亦稱為垂直擴散中斷)106而分隔的下部3D垂直電晶體103a及上部3D垂直電晶體103b。經由垂直隔離而分隔的額外電晶體可包含在堆疊體101a及/或101b中。下部電晶體103a包含垂直半導體芯部(亦稱為通道結構)202a、磊晶殼層(亦稱為epi殼層)110、源極/汲極區域(亦稱為S/D區域)124及126、以及閘極堆疊體128。垂直半導體芯部 202a及/或磊晶殼層110用作電晶體通道，其在S/D區域124與126之間提供一垂直電流路徑(相對於基板102的表面)。如下文中所進一步討論，半導體芯部202a可磊晶式地生長。在圖1及圖2的實施例中，閘極堆疊體128包括閘極介電質122及閘極導體123。任何已知的介電質及導體材料皆可用於閘極堆疊體128中，且閘極堆疊體128中可包含額外的閘極堆疊體膜層。
上部電晶體103b類似地包含垂直半導體芯部306、磊晶殼層108、S/D區域114及116、以及閘極堆疊體118。垂直半導體芯部306及/或磊晶殼層108用作在S/D區域114與116之間提供垂直電流路徑(相對於基板102的表面)的電晶體通道。半導體芯部306可磊晶式地生長，且閘極堆疊體118包括閘極介電質112及閘極導體113。任何合適的介電質及導體材料皆可用於閘極堆疊體128中，且閘極堆疊體128中可包含額外的閘極堆疊體膜層。此外，任何合適的介電質皆可用於垂直隔離106。
下部3D垂直電晶體103a及上部3D垂直電晶體103b可為相同類型或不同類型。亦即，垂直3D電晶體堆疊體101b可包括全PMOS裝置、全NMOS裝置、或PMOS與NMOS裝置之組合。雖然圖1及2的範例顯示各自包含磊晶殼層的下部3D垂直電晶體103a及上部3D垂直電晶體103b，但該等電晶體中之一者可不具有磊晶殼層並且使用半導體芯部202a或306作為電晶體通道。亦即，垂直3D電晶體堆疊體101b可包括各自具有磊晶殼層的複數電晶體、或具有和不具有磊晶殼層之電晶體的組合。
如上所述，可磊晶式地生長垂直半導體芯部202a、306及磊晶殼層110、108。磊晶材料可為週期表的12種元素(來自III、IV、及V族)中之任一者，且可在本文中用於芯部磊晶或殼層磊晶以及其任何組合。III族包括硼(B)、鋁(Al)、鎵(Ga)、及銦(In)。IV族包括碳(C)、矽(Si)、鍺(Ge)、及錫(Sn)。V族包括氮(N)、磷(P)、砷(As)、及銻(Sb)。在磊晶芯部上生長的獨立磊晶芯部或殼層可包括例如Si、Si xC y、Ge、Si xGe y、Ge xSn y、(此外，針對磊晶芯部或磊晶殼層，IV欄可包含磊晶生長的IV欄中的2個元素，範例為SiC、SiGe、GeSn、GeC、SnC、SiSn)。
關於磊晶芯部的一些磊晶堆疊體範例包括：(1) Si、Si x1Ge x1、Ge；(2) Si x1Ge yx、Si；(3) Si、SiC；(4) Ge、Ge xSn y；(5) Si、Si xGe y、GaB；(6) Si、Si x、Ge y、GaN。其他磊晶芯部或磊晶殼層為可原位磊晶摻雜(作為芯部或磊晶殼層)或摻雜有以下者的垂直奈米片層：III欄或V欄並結合IV欄 SiAs、SiP、SiSb、SiIn、SiGa、SiB、SiGaB、GeAs、GeP、GeSb、GeIn、GeB、SiCAs、SiCP、SiCAs、SiCSb、SiCIn、SiCB、以及GexSny，且具有例如As、P、Sb、In、Ga、B之原位摻雜。其他可與Si及Ge芯部一起使用的磊晶殼層包括使用過渡磊晶層(使用III、V之對)的GaAs、InP、GaP、GaN、InGaAs。應注意，本文之給定的磊晶殼層/芯部磊晶殼層可用於針對裝置需求而定制各個堆疊通道。並未列出使用所示之12個元素的所有組合。如可理解的，本文考量了其他組合。
本文所使用的介電質通常為氧化物，例如二氧化矽。本文所使用的複數裝置區域之間的垂直隔離為介電質。在裝置尺寸很關鍵的某些情況下，可使用高k介電質。高k介電質的範例包括氮氧化物、二氧化鉿、矽酸鉿、矽酸鋯、及二氧化鋯。
通道芯部202a、306可為不同的形狀及尺寸，其對於不同類型的裝置係有用的。圖2顯示在介電質150內(其中閘極堆疊體被介電質150覆蓋)的圖1之電晶體堆疊體的俯視圖。此處的通道芯部202a、306可為中空並且填充有金屬，或者可包含矽或磊晶材料。此外，芯部202a、306的水平截面形狀可為如圖2所示的圓形、矩形、或其他形狀。磊晶殼層108、110可形成於相應芯部202a、306的表面上。可針對不同的裝置設計而形成不同的直徑或寬度。
其餘的圖式包括用於各種實施例的五個例示性流程：處理流程A、處理流程B、處理流程C、處理流程D、及處理流程E。
在一實施例中，3D垂直奈米片裝置可形成為在垂直3D電晶體堆疊體上具有一個磊晶殼層，使得另一個電晶體為芯部磊晶電晶體。處理流程A(圖3A-3I)顯示形成3D VFET的結構，其具有在垂直3D電晶體堆疊體上的一個epi(磊晶)殼層、一個芯部epi電晶體，其中N=2電晶體。起始基板或晶圓可為矽102/介電質104/矽202晶圓，如圖3A所示。在圖3B中，Si 202a/SiGe 304/Si 306的分層磊晶堆疊體係生長在基板或晶圓上。
在圖3A-3I的實施例中，通道結構係由層狀磊晶堆疊體在基板或晶圓上形成，該等通道結構具有相對於基板表面的垂直導電路徑。通道結構包括兩層或多層通道結構的垂直堆疊體。光阻蝕刻遮罩402可用於蝕刻膜層堆疊體以形成圖3C中顯示的所得通道結構。光阻蝕刻遮罩402可為圓形、方形、矩形、或其他形狀的矩陣圖案，以根據需要而適應沿所得垂直通道芯部之側邊的電晶體結構。垂直通道芯部呈圓柱或矩形柱的形狀。可去除蝕刻遮罩402，然後進行介電質沉積502及化學機械平坦化(CMP)以提供圖3D中的結構。藉由利用介電材料替代堆疊體的SiGe部分304以形成用於兩個裝置矽區域的垂直隔離106，可將裝置結構或元件隔離，如圖3E所示。用於形成隔離區域的技術係在以下文獻中揭示：2020年11月11日提交的美國專利申請案序號17/094,947之「Method of Making 3D Isolation」，在此將其全部內容引入以供參照。
圖3E顯示在透過3D隔離步驟完成矽的本質芯部(或P+或N+摻雜的芯部)之後的處理流程。在介電質802沉積之後進行CMP，然後進行回蝕或受控深度蝕刻以使頂部矽區域306露出，俾提供圖3E的結構。與用於垂直隔離106的材料相比，介電質802可為不同的材料。接著，在用於未來PMOS區域的上部3D垂直電晶體(未經覆蓋的半導體部分306)上生長Si xGe y磊晶殼層108，如圖3G所示。磊晶殼層108係圍繞未經覆蓋的半導體部分306之芯部306而形成。接著，藉由選擇性介電質1002沉積或生長而覆蓋磊晶殼層以保護SiGe區域108，如圖3H所示。在圖3I中，介電質802及介電質1002被去除。此時，為了形成NMOS及PMOS電晶體的堆疊體，界定兩種類型的垂直通道區域及S/D區域。因此，在圖3A-3I的實施例中，下部垂直電晶體使用半導體芯部202a作為其電晶體通道結構，而上部垂直電晶體使用磊晶殼層108作為其電晶體通道結構的一部分。接著，可在半導體芯部202a及磊晶殼層108上形成S/D區域及閘極堆疊體，以提供類似於圖1所示者的完整電晶體。
處理流程B提供3D垂直場效電晶體(3D VFET)，其具有一個材料1之磊晶殼層(PMOS)及另一個材料2之磊晶殼層(NMOS)，其中N=2電晶體。處理流程B以與處理流程A類似的方式開始，但包含如圖4所示的額外步驟。在完成圖3A-3H所示的步驟之後，將介電質802去除，然後進行Ge或SiC的磊晶殼層110形成，其係形成在用於下部NMOS電晶體的流動通道之下部區域周圍，如圖4所示。可將介電質1002去除，並且可完成NMOS及PMOS閘電極及S/D區域，以形成如圖1所示的垂直電晶體堆疊體。
處理流程C(圖5A-5D)顯示具有用於一個電晶體的一個磊晶殼層之3D VFET，其使用可棄式SiGe磊晶殼層，使得僅有PMOS具有Si xGe y磊晶殼層。處理流程C以與處理流程A類似的方式開始。圖3A-3H中所示的步驟在透過3D隔離完成矽的本質芯部(或經摻雜的芯部)之後提供堆疊的垂直流動通道。在圖5A中，圍繞流動通道而形成SiGe磊晶殼層108、108a以覆蓋NMOS及PMOS區域兩者。應注意，在後續步驟中，將會在NMOS區域中去除SiGe殼層。在圖5B中，介電質1802沉積將底部(PMOS區域)覆蓋。在圖5C中，從用於未來NMOS裝置的頂部區域去除Si xGe y108。因此，在圖5A-5D的範例中，下部垂直電晶體包括作為其通道結構的一部分的磊晶殼層，而上部垂直電晶體僅使用半導體芯部306作為其通道結構。接著，可形成S/D區域114、116、124、126及閘極堆疊體118及128以提供如圖5D所示之完整的垂直電晶體。
例如，上文中圖3-5中所描述的處理流程可用於製造垂直奈米片。該等處理流程之各者藉由在基板上依序磊晶生長含矽材料而提供垂直電晶體堆疊體的初始電晶體芯部或通道結構，如圖3A-3F所述。在其他實施例中，可藉由對分離的晶圓進行晶圓接合(wafer bonding)而提供垂直電晶體堆疊體的初始電晶體芯部或通道結構。處理流程D(圖6A-6G)顯示二或更多晶圓的接合，用以製造具有雙磊晶殼層晶體殼層的垂直奈米片，其係在每個晶圓上從用於PMOS的Si/SiGe/Ge及用於NMOS的Si之3D奈米平面開始(每個晶圓N = 1個電晶體)。對於2個晶圓接合的範例，N=2。這可為CFET或n-on-n、p-on-p、或任何其他組合。亦針對PMOS考量單一磊晶殼層。此流程提供垂直擴散中斷作為接合處理的一部分，其與隔離相結合以大幅簡化成本及與垂直奈米片的整合。
在圖6A中，奈米片的膜層堆疊體係在第一晶圓610上由矽Si或鍺Ge 202a形成。此範例提供N＝1之電晶體堆疊體，但N可為五層、十層、或更多層高，接著為介電質覆蓋層2304。此外，此特定範例使用兩個接合晶圓，但接合晶圓的數量可多於兩個。將具有相似基板堆疊的第二晶圓620翻轉並使用薄介電層2402作為界面而接合至第一晶圓610。接著去除第二矽基板202b的一部分，然後形成覆蓋層2406(其可為諸如TiN的硬遮罩材料)以提供圖6B的結構。可對晶圓進行退火(例如400C)以接合兩個接合晶圓610、620。
如圖6C所示，形成蝕刻遮罩2504以將呈垂直奈米片形式的通道結構圖案化。如所見，兩個晶圓的接合形成上部與下部垂直電晶體之間的垂直擴散中斷或垂直隔離2502。在圖6D中，執行氧化物沉積2602、CMP、及蝕刻處理以使頂部的電晶體或頂層電晶體(在兩個電晶體堆疊體中)暴露。接著，在通道結構202b周圍生長Si xGe y2604之磊晶殼層。此處理對於PMOS裝置而言包括生長Si xGe y之殼層然後生長Ge。替代方案包括Si xGe y然後Ge xSn y或任何其他可由前述的各種組合及元素所形成的PMOS相容殼層。可根據裝置要求或性能規格而選擇各種組合。
在圖6E中，選擇性地沉積介電質2702以覆蓋用於PMOS裝置的磊晶殼層2604，然後將覆蓋底部電晶體的材料去除。接著，如圖6F所示，在用於NMOS裝置的底層中圍繞通道結構而生長磊晶殼層2802。例如，可生長SiCP之磊晶殼層2802。磊晶殼層的其他選項包括但不限於SiC、SiCA、SiCSb等，其可基於性能設計。可去除介電質2702，接著垂直通道裝置的堆疊體可具有針對NMOS及PMOS垂直奈米片而完成的源極/汲極區域2904、2906、2914、2916，例如圖6G中所示的CFET。用於閘極堆疊體2908、2918的介電質可包括高k閘極介電質2902、2912。圖7顯示圖6G的電晶體堆疊體之俯視圖，其中周圍的介電質150覆蓋閘極堆疊體。此處的通道芯部202a、202b可為中空的，並且可填充有金屬，或者可包含矽、或磊晶材料。此外，芯部202a、202b的水平截面形狀為矩形，作為一奈米片。磊晶殼層108、110可形成於相應芯部202a、202b的表面上。可針對不同的裝置而形成不同的寬度。圖8顯示如何可形成具有磊晶殼層的複數垂直通道電晶體。在此範例中，利用強健的整合流程將四個晶圓接合，其針對每個電晶體而具有一垂直隔離/擴散中斷。如所見，垂直電晶體堆疊體801a及801b各自包括由垂直擴散中斷所分隔的四個垂直通道電晶體。針對NMOS/PMOS順序，各個堆疊體可有所變化，從而引致N=4之電晶體。類似地，針對堆疊體中的複數電晶體之間包含磊晶殼層的情況，各個堆疊體可有所變化。
處理流程E(圖9A-9G)顯示二或更多晶圓的接合，用以製造具有雙磊晶晶體殼層的垂直奈米片，其係在每個晶圓上從用於PMOS的Si/SiGe/Ge及用於NMOS的Si之3D奈米平面開始(每個晶圓N=2個電晶體)。對於2個晶圓接合的範例，N=4。應注意，N個晶圓可在各個晶圓上的3D奈米平面的蝕刻處理之前接合在一起。此外，藉由在切割3D垂直奈米平面之前接合晶圓而實現360度旋轉對稱(亦即，對準精度對於本文技術而言不成問題)。
如圖9A中所示，具有SiGe 3108及(Si或Ge 3110)之交替層的3D奈米片堆疊體係生長在第一晶圓910的矽3102/介電質3104/矽3106基板上。本文所述的範例顯示N＝2之電晶體，但堆疊體可具有10至20層或更多層。圖9B顯示具有相似基板堆疊體的第二晶圓920，其被翻轉並使用薄介電層3224作為界面而接合，然後可從組合的晶圓的一側去除主體矽，使得僅有一側具有主體矽102。可將覆蓋層3232或硬遮罩添加至相反側。如圖9C所示，組合的基板可具有形成於其上的蝕刻遮罩3302，並且執行定向蝕刻以形成通道結構。層之間的垂直隔離3224、3112係由接合介電質提供，如圖9D所示，其中遮罩3302被移除。垂直隔離3408、3428亦可使用例如美國專利申請案序號17/094,947中所揭示的替代技術而如上述地提供。
另一實施例包括製造頂部兩個電晶體PMOS及底部兩個電晶體NMOS。另一選項為具有頂部兩個的NMOS與底部兩個的PMOS之鏡像。於是可將堆疊體一般化為N個電晶體，並且可使用本文所揭示的選擇性磊晶殼層技術製造任何序列的NMOS、PMOS、或組合。圖9E顯示利用介電質覆蓋物3502覆蓋底部的兩個電晶體/通道，以在頂部電晶體上生長Si xGe y3524、3526之磊晶殼層。接著將覆蓋物3502去除，如圖9F所示。可在底部通道結構上設置額外的磊晶殼層，然後形成各個堆疊體901a及901b中之四個垂直電晶體(PMOS及NMOS裝置)的S/D及閘極區域，如圖9G所示。如所見，垂直堆疊體之各者包括藉由替換而形成的垂直隔離及藉由晶圓接合而形成的隔離。
在前述中，已提出特定細節，例如處理系統之特定幾何以及其中所使用之各種元件及處理之敘述。然而，吾人應了解，本文之技術可實行於不同於這些特定細節之其他實施例，且此等細節係用於解釋之目的而非用以設限制。本文揭露之實施例已參照附圖敘述。同樣地，為了作解釋，已提到特定數目、材料、及配置以供徹底理解。然而，在無這些特定細節的情況下，亦可能實行實施例。實質上具有相同功能性結構之元件係由類似的參考符號表示，因此可能省略所有多餘的敘述。
已將各種技術描述為多重的分散操作以協助理解各實施例。不應將描述之順序解釋為隱含有這些操作必須係順序相依之意。這些操作確實並不需依描述之順序執行。所述之操作可依不同於所述之實施例的順序執行。在額外之實施例中，可執行各種額外之操作及/或可省略所述之操作。
本文所提及之「基板」或「目標基板」基本上指涉依據本發明受處理之物體。該基板可包含任何材料部分或元件之結構，特別係半導體或其他電子元件，以及可係例如一基底基板結構，如半導體晶圓、標線片，或是在基底基板結構之上方或覆蓋其上之膜層例如一薄膜。因此，基板並不限於任何特定基底結構、基底層或覆蓋層、經圖案化或未經圖案化，而係考量包含任何此類膜層或基底結構，以及任何膜層及/或基底結構之組合。該敘述可參考基板之特定類型，但僅為了說明之目的。
熟悉本技藝者亦將理解，可對前述之該技術之操作做出許多變化，而依然能達到本發明之相同目的。本發明之範圍擬包含此類變化。因此，不擬將本發明之實施例之以上敘述視為限制性者。而擬將對於本發明之實施例的任何限制於以下申請專利範圍說明。
101a:堆疊體 101b:堆疊體 102:基板 103a:下部電晶體 103b:上部電晶體 104:介電層 106:垂直隔離 108:磊晶殼層 108a:磊晶殼層 110:磊晶殼層 112:閘極介電質 113:閘極導體 114:S/D區域 116:S/D區域 118:閘極堆疊體 122:閘極介電質 123:閘極導體 124:S/D區域 126:S/D區域 128:閘極堆疊體 150:介電質 202:矽 202a:芯部 202b:芯部 304:SiGe部分 306:芯部 402:蝕刻遮罩 502:介電質沉積 610:第一晶圓 620:第二晶圓 801a:垂直電晶體堆疊體 801b:垂直電晶體堆疊體 802:介電質 901a:堆疊體 901b:堆疊體 910:第一晶圓 920:第二晶圓 1002:介電質 1802:介電質 2304:介電質覆蓋層 2402:薄介電層 2406:覆蓋層 2502:垂直擴散中斷或垂直隔離 2504:蝕刻遮罩 2602:氧化物沉積 2604:磊晶殼層 2702:介電質 2802:磊晶殼層 2902:閘極介電質 2904:源極/汲極區域 2906:源極/汲極區域 2908:閘極堆疊體 2912:閘極介電質 2914:源極/汲極區域 2916:源極/汲極區域 2918:閘極堆疊體 3102:矽 3104:介電質 3106:矽 3112:垂直隔離 3224:垂直隔離 3232:覆蓋層 3302:遮罩 3408:垂直隔離 3428:垂直隔離 3502:覆蓋物
對本揭示內容及其許多伴隨優點的更完整理解將會係容易獲得，因為其係藉由結合附圖考量而參照以下詳細描述以變得更佳地理解，其中：
圖1顯示根據本揭示內容的一個實施例之例示性垂直場效電晶體的剖視圖；
圖2顯示圖1的電晶體堆疊體之俯視圖；
圖3A、3B、3C、3D、3E、3F、3G、3H、及3I顯示根據本揭示內容的一個實施例之用於形成3D電晶體堆疊體的程序中的中間結構；
圖4顯示根據本揭示內容的另一實施例之用於形成3D電晶體堆疊體的程序中的中間結構；
圖5A、5B、5C、及5D顯示根據本揭示內容的另一實施例之用於形成3D電晶體堆疊體的程序中的中間結構；
圖6A、6B、6C、6D、6E、6F、及6G顯示根據本揭示內容的另一實施例之用於形成3D電晶體堆疊體的程序中的中間結構；
圖7顯示圖6G的電晶體堆疊體的俯視圖；
圖8顯示由多個晶圓形成的3D垂直場效電晶體堆疊體；以及
圖9A、9B、9C、9D、9E、9F、及9G顯示根據本揭示內容的另一實施例之用於形成3D電晶體堆疊體的程序中的中間結構。
102:基板
104:介電層
202a:芯部
202b:芯部
2502:垂直擴散中斷或垂直隔離
2604:磊晶殼層
2802:磊晶殼層
2902:閘極介電質
2904:源極/汲極區域
2906:源極/汲極區域
2908:閘極堆疊體
2912:閘極介電質
2914:源極/汲極區域
2916:源極/汲極區域
2918:閘極堆疊體

Claims (20)

  1. 一種形成電晶體裝置的方法，包含： 提供具有膜層堆疊體的基板，該膜層堆疊體包含由一中間層所分隔的複數半導體通道層； 由該複數半導體通道層分別形成複數芯部通道結構，該複數芯部通道結構各自具有相對於該基板之表面的一垂直導電路徑，並且包含垂直堆疊在該基板上且被由該中間層形成之隔離結構所分隔的第一及第二芯部通道結構；以及 在該第一芯部通道結構周圍形成第一磊晶殼層，使得該第一磊晶殼層形成待由該第一芯部通道結構形成之第一電晶體之第一電晶體通道的至少一部分。
  2. 如請求項1之形成電晶體裝置的方法，更包含： 在該第一磊晶殼層上形成第一源極/汲極(S/D)區域及第一閘極結構以完成該第一電晶體；以及 在該第二芯部通道結構上形成第二S/D區域及第二閘極結構，以完成在該基板上與該第一電晶體垂直堆疊的第二電晶體，其中該第一電晶體的該第一電晶體通道包含該第一磊晶殼層，且該第二電晶體的第二電晶體通道係由該第二芯部通道結構製成。
  3. 如請求項2之形成電晶體裝置的方法，其中形成第一磊晶殼層之步驟包含利用與該第一芯部通道結構相同的材料形成第二磊晶殼層，使得該第一及第二電晶體具有相同的導電性類型。
  4. 如請求項2之形成電晶體裝置的方法，其中形成第一磊晶殼層之步驟包含利用與該第一芯部通道結構不同的材料形成第二磊晶殼層，使得該第一及第二電晶體具有不同的導電性類型。
  5. 如請求項1之形成電晶體裝置的方法，更包含： 在該第二芯部通道結構周圍形成第二磊晶殼層，使得該第二磊晶殼層形成待由該第二芯部通道結構形成之第二電晶體之第二電晶體通道的至少一部分；以及 分別在該第一及第二磊晶殼層之各者上形成第一源極/汲極(S/D)區域及閘極結構以完成相應的該第一及第二電晶體。
  6. 如請求項5之形成電晶體裝置的方法，其中形成第二磊晶殼層之步驟包含利用與該第一磊晶殼層相同的材料形成該第二磊晶殼層，使得該第一及第二電晶體具有相同的導電性類型。
  7. 如請求項5之形成電晶體裝置的方法，其中形成第二磊晶殼層之步驟包含利用與該第一磊晶殼層不同的材料形成該第二磊晶殼層，使得該第一及第二電晶體具有不同的導電性類型。
  8. 如請求項1之形成電晶體裝置的方法，其中提供具有膜層堆疊體的基板之步驟包含： 在該基板上磊晶式地生長該複數半導體通道層的第一半導體通道層； 在該第一半導體通道層上磊晶式地生長該中間層；以及 在該中間層上磊晶式地生長該複數半導體通道層的半導體通道層。
  9. 如請求項8之形成電晶體裝置的方法，更包含藉由利用介電材料替代該中間層而形成該隔離結構。
  10. 如請求項1之形成電晶體裝置的方法，其中提供具有膜層堆疊體的基板之步驟包含： 提供第一基板，該第一基板具有形成於該第一基板之第一絕緣層上之該複數半導體通道層的第一半導體通道層； 提供第二基板，該第二基板具有形成於該第二基板之第二絕緣層上之該複數半導體通道層的第二半導體通道層；以及 將該第一絕緣層晶圓接合至該第二絕緣層以形成具有該膜層堆疊體的組合式基板，該膜層堆疊體包含由形成該中間層之接合的該第一及第二絕緣層所分隔的該複數半導體通道層。
  11. 如請求項1之形成電晶體裝置的方法，其中： 提供基板之步驟包含提供具有包括多個半導體通道層之膜層堆疊體的基板，該多個半導體通道層係經由相應的中間層而彼此分隔開；並且 形成複數芯部通道結構之步驟包含分別由該多個半導體通道層形成多個芯部通道結構，該多個芯部通道結構各自具有相對於該基板之表面的一垂直導電路徑，並且包含該第一及第二芯部通道結構以及至少一個第三通道結構，該至少一個第三通道結構係垂直堆疊在該基板上且被由相應的該中間層形成的隔離結構所分隔，其中各個隔離結構係由晶圓接合界面或替代該中間層的替代性絕緣材料所形成。
  12. 一種電晶體裝置的微製造方法，包含： 由膜層堆疊體在一基板上形成通道結構，該等通道結構各自具有相對於該基板之表面的一垂直導電路徑，該等通道結構包括二或更多通道結構階層的垂直堆疊體；以及 藉由磊晶生長而在該等通道結構階層之至少一者中圍繞通道結構形成殼層，使得該等殼層之各者為待於該等通道結構階層之該至少一者中形成的對應電晶體之相應電晶體通道的一部分。
  13. 如請求項12之電晶體裝置的微製造方法，其中形成殼層之步驟包含： 利用介電質覆蓋一或更多第一通道結構階層，而一或更多第二通道結構階層未經覆蓋；以及 自該一或更多第二通道結構階層形成該等殼層以成為圍繞各個未經覆蓋之通道結構的第一殼層，該等第一殼層係各自藉由磊晶生長而形成，且為待形成之對應電晶體的電晶體通道結構的一部分。
  14. 如請求項13之電晶體裝置的微製造方法，更包含： 覆蓋該等第一殼層，且同時使該一或更多第一通道結構階層露出；以及 自該一或更多第一通道結構階層形成圍繞未經覆蓋之通道結構的第二殼層，該等第二殼層之各者係藉由磊晶生長而形成，且為待形成之對應電晶體的相應電晶體通道結構的一部分。
  15. 如請求項12之電晶體裝置的微製造方法，其中形成殼層之步驟包含： 藉由磊晶生長而在該等通道結構階層之各者中圍繞各個通道結構形成殼層，使得該等殼層之各者為待形成之對應電晶體的相應電晶體通道的一部分； 利用介電質覆蓋一或更多第一通道結構階層，而一或更多第二通道結構階層未經覆蓋；以及 從該一或更多第二通道結構階層的通道結構去除該等殼層。
  16. 如請求項12之電晶體裝置的微製造方法，更包含藉由磊晶生長及接合二或更多晶圓之其中至少一者以形成該膜層堆疊體。
  17. 一種微製造的電晶體裝置，包含： 半導體基板上之場效電晶體的二或更多通道的垂直堆疊體，該等通道之各者具有相對於該半導體基板之表面的一垂直導電路徑，該等通道中之至少一者包含圍繞芯部材料形成的殼層，該殼層包含磊晶材料。
  18. 如請求項17之微製造的電晶體裝置，其中該等通道之各者包含圍繞芯部材料形成的殼層，該等殼層之各者包含磊晶材料。
  19. 如請求項17之微製造的電晶體裝置，其中該垂直堆疊體的該二或更多通道係經由一隔離體而彼此分隔。
  20. 如請求項17之微製造的電晶體裝置，其中該垂直堆疊體包括用於PMOS場效電晶體的通道及用於NMOS場效電晶體的通道。
TW111102354A 2021-01-26 2022-01-20 高效能3d垂直電晶體裝置的改善設計 TW202234591A (zh)

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