TW202230651A - 半導體封裝 - Google Patents
半導體封裝 Download PDFInfo
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- TW202230651A TW202230651A TW110126887A TW110126887A TW202230651A TW 202230651 A TW202230651 A TW 202230651A TW 110126887 A TW110126887 A TW 110126887A TW 110126887 A TW110126887 A TW 110126887A TW 202230651 A TW202230651 A TW 202230651A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 133
- 239000000758 substrate Substances 0.000 claims abstract description 190
- 230000017525 heat dissipation Effects 0.000 claims abstract description 23
- 229920005989 resin Polymers 0.000 claims description 30
- 239000011347 resin Substances 0.000 claims description 30
- 230000001681 protective effect Effects 0.000 claims description 19
- 230000004888 barrier function Effects 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 148
- 235000012431 wafers Nutrition 0.000 description 21
- 239000004020 conductor Substances 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 15
- 239000000853 adhesive Substances 0.000 description 12
- 230000001070 adhesive effect Effects 0.000 description 12
- 239000000470 constituent Substances 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- 239000010949 copper Substances 0.000 description 8
- 239000003822 epoxy resin Substances 0.000 description 7
- 239000011810 insulating material Substances 0.000 description 7
- 230000000149 penetrating effect Effects 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 239000010931 gold Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 239000011295 pitch Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 238000003491 array Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000003365 glass fiber Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 230000036961 partial effect Effects 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 229920005992 thermoplastic resin Polymers 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 3
- 239000011256 inorganic filler Substances 0.000 description 3
- 229910003475 inorganic filler Inorganic materials 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000011324 bead Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920006336 epoxy molding compound Polymers 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- -1 inductors Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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Abstract
一種半導體封裝包括:基礎基板,包括配線圖案;中介基板,包括下部重佈線圖案及上部重佈線圖案;半導體結構;散熱結構;多個外部連接凸塊,設置於基礎基板的下表面上;多個下部連接凸塊,設置於基礎基板與中介基板之間;以及多個上部連接凸塊,設置於中介基板與半導體結構之間。
Description
本揭露的實施例是有關於一種半導體封裝。
[相關申請案的交叉參考]
本申請案主張於2020年10月7日在韓國智慧財產局提出申請的韓國專利申請案第10-2020-0129209號的優先權及權益,所述韓國專利申請案全文併入本案供參考。
根據半導體晶片更高效能的趨勢,在半導體封裝領域中,正在開發用於在大面積封裝基板上安裝多個半導體晶片的系統級封裝(system-in-package,SIP)技術。在此種情形中,需要一種在用於大面積封裝的基板上形成用於與半導體晶片的精細凸塊節距(pitch)一起使用的配線(wiring)的技術。
根據本揭露的一個態樣,提供一種具有降低的製造成本及極佳的良率(yield)的半導體封裝。
根據一或多個實施例,提供一種半導體封裝。所述半導體封裝包括:基礎基板,具有彼此相對的上表面與下表面,且包括配線圖案;中介基板,設置於所述基礎基板的所述上表面上,且具有彼此相對的上表面與下表面,且包括電性連接至所述配線圖案的至少一個下部重佈線圖案,且更包括設置於所述至少一個下部重佈線圖案上且電性連接至所述至少一個下部重佈線圖案的至少一個上部重佈線圖案;半導體結構,設置於所述中介基板的所述上表面上,且電性連接至所述至少一個上部重佈線圖案;散熱結構,設置於所述基礎基板的所述上表面上,且覆蓋所述中介基板及所述半導體結構;多個外部連接凸塊,設置於所述基礎基板的所述下表面上,且連接至所述配線圖案;多個下部連接凸塊,設置於所述基礎基板與所述中介基板之間,且對所述配線圖案與所述至少一個下部重佈線圖案進行連接;以及多個上部連接凸塊,設置於所述中介基板與所述半導體結構之間,且對所述至少一個上部重佈線圖案與所述半導體結構進行連接。所述多個外部連接凸塊中彼此鄰近的一對外部連接凸塊之間的距離在0.8毫米至1.5毫米的範圍內,所述多個下部連接凸塊中彼此鄰近的一對下部連接凸塊之間的距離在0.1毫米至0.7毫米的範圍內,且所述多個上部連接凸塊中彼此鄰近的一對上部連接凸塊之間的距離在50微米至150微米的範圍內。
根據一或多個實施例,提供一種半導體封裝。所述半導體封裝包括:基礎基板,包括配線圖案;中介基板,包括設置於不同水平上且電性連接至所述配線圖案的多個下部重佈線圖案,且更包括電性連接至所述多個下部重佈線圖案的多個上部重佈線圖案,所述中介基板設置於所述基礎基板上;以及半導體結構,設置於所述中介基板上且電性連接至所述多個上部重佈線圖案。所述多個上部重佈線圖案中的最上上部重佈線圖案包括自所述中介基板的上表面突出的上部連接墊,所述多個上部重佈線圖案中設置於所述上部連接墊下方的至少一者包括與所述上部連接墊交疊的著陸墊,且所述上部連接墊的最大寬度小於所述著陸墊的最大寬度。
根據一或多個實施例,提供一種半導體封裝。所述半導體封裝包括:基礎基板,包括配線圖案;中介基板,包括電性連接至所述配線圖案的多個下部重佈線圖案,且更包括電性連接至所述多個下部重佈線圖案的多個上部重佈線圖案,所述中介基板設置於所述基礎基板上;以及半導體結構,設置於所述中介基板上且電性連接至所述多個上部重佈線圖案。所述多個下部重佈線圖案及所述多個上部重佈線圖案在第一方向上延伸,所述多個下部重佈線圖案在垂直於所述第一方向的第二方向上的線寬在7微米至20微米的範圍內,且所述多個上部重佈線圖案在所述第二方向上的線寬在5微米至10微米的範圍內。所述多個下部重佈線圖案中設置於同一水平上且在所述第二方向上彼此鄰近的一對下部重佈線圖案之間的距離在10微米至20微米的範圍內,且所述多個上部重佈線圖案中設置於同一水平上且在所述第二方向上彼此鄰近的一對上部重佈線圖案之間的距離在5微米至10微米的範圍內。
在下文中,將參照附圖闡述本揭露的非限制性示例性實施例如下。
圖1A至圖1C是示出根據本揭露示例性實施例的半導體封裝1000A的剖視圖、平面圖及局部放大圖,且圖2A及圖2B是示出圖1所示基礎基板100的經修改實例的剖視圖,圖3A及圖3B是示出圖1所示中介基板200的組件的局部放大平面圖,且圖4A至圖4D是示意性地示出圖1所示中介基板200的製造製程的剖視圖。圖1A是沿圖1B所示的線I-I’截取的剖視圖。圖1C是圖1所示的區域「A」的放大圖。
參照圖1A至圖1C,根據示例性實施例的半導體封裝1000A可包括基礎基板100、中介基板200及半導體晶片(或半導體結構)300。另外,半導體封裝1000A可更包括覆蓋中介基板200及半導體晶片300的散熱結構400。
基礎基板100可為上面安裝有中介基板200、半導體晶片300及散熱結構400的支撐基板,且可為包括電性連接至中介基板200的重佈線電路及半導體晶片300的連接墊的配線電路的封裝基板。封裝基板可包括印刷電路板(printed circuit board,PCB)、陶瓷基板、玻璃基板、帶狀配線板(tape wiring board)及類似物。
基礎基板100可為上面安裝有中介基板200及半導體晶片300的大面積基板。基礎基板100的水平寬度及垂直寬度可分別為40毫米或大於40毫米。舉例而言,基礎基板100的最小寬度可在約40毫米至約80毫米的範圍內。安裝於基礎基板100上的中介基板200及半導體晶片300的水平寬度及垂直寬度可分別為10毫米或大於10毫米。舉例而言,中介基板200及半導體晶片300的最小寬度的範圍可介於約10毫米至30毫米。
基礎基板100可具有彼此相對的上表面100S1與下表面100S2,且可包括核心基板部分110、上部基板部分120、下部基板部分130、上部覆蓋層140A及下部覆蓋層140B。基礎基板100可包括位於上表面100S1與下表面100S2之間的配線電路,所述配線電路包括配線圖案及配線通孔。
核心基板部分110可包括核心絕緣層111、設置於核心絕緣層111的兩個表面(上表面及下表面)上的多個核心配線圖案112以及穿透過核心絕緣層111且將所述多個核心配線圖案112彼此連接的穿孔113。核心基板部分110可具有其中根據配線電路的設計堆疊多個核心絕緣層111的多層式核心基板結構。
核心絕緣層111可藉由改善基板的剛性(rigidity)來抑制基板的翹曲(warpage)。核心絕緣層111的厚度可大於上部構成絕緣層121及下部構成絕緣層131中的每一者的厚度。核心絕緣層111可包含例如:熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺;或者包含無機填料及/或玻璃纖維的預浸體(prepreg)、味之素構成膜(Ajinomoto Build-up Film,ABF)、弗朗克功能調節劑4(Frankel’s function regulator 4,FR-4)、雙馬來醯亞胺三嗪(Bismaleimide Triazine,BT)及環氧模製化合物(Epoxy Molding Compound,EMC)。核心絕緣層111可使用例如覆銅疊層體(copper clad laminate,CCL)、無包覆(unclad)覆銅疊層體(CCL)、玻璃基板、陶瓷基板或類似物形成。
所述多個核心配線圖案112可包含導電材料,例如銅(Cu)、鋁(Al)、鎳(Ni)、銀(Ag)、金(Au)、鉑(Pt)、錫(Sn)、鉛(Pb)、鈦(Ti)、鉻(Cr)、鈀(Pd)、銦(In)、鋅(Zn)及碳(C)中的至少一種金屬或者包含二或更多種金屬的合金。端視設計而定,所述多個核心配線圖案112可包括接地(ground,GND)圖案、電源(power,PWR)圖案、訊號(signal,S)圖案及類似物。
穿孔113可被形成為使得穿透過核心絕緣層111的通孔孔洞被利用導電材料完全填充,或者導電材料被形成為沿通孔孔洞的壁共形。當穿孔113被形成為使得導電材料沿通孔孔洞的壁形成時,通孔孔洞內部的空間可被利用絕緣材料(例如環氧樹脂或類似物)填充。
上部基板部分120可包括堆疊於核心絕緣層111的上表面上的上部構成絕緣層121、設置於上部構成絕緣層121上的上部配線圖案122以及穿透過上部構成絕緣層121且對上部配線圖案122與核心配線圖案112進行連接的上部配線通孔123。
上部構成絕緣層121可具有其中由絕緣材料形成的多個核心絕緣層111在垂直方向(Z軸方向)上堆疊的結構。所述多個絕緣層可被整合成使得所述多個絕緣層中的每一者之間的邊界可能不清楚。絕緣材料可包括例如:熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺;或者包含無機填料及/或玻璃纖維的預浸體、味之素構成膜(ABF)、FR-4及類似物。
上部配線圖案122可包括設置於不同水平上的多個上部配線圖案。上部配線圖案122可電性連接至核心配線圖案112及下部配線圖案132中的至少一者。類似於核心配線圖案112,上部配線圖案122可包括接地圖案、電源圖案、訊號圖案及類似物。上部配線圖案122可包含上述導電材料中的一者。
上部配線通孔123可穿透過上部構成絕緣層121的至少部分,且對設置於不同層中的上部配線圖案進行連接,或者對上部配線圖案122與核心配線圖案112進行連接。相似於上部配線圖案122,上部配線通孔123可包含導電材料。上部配線通孔123可具有其中通孔孔洞的內部被利用金屬材料填充的填充通孔(filled via)的形式或者其中金屬材料沿通孔孔洞的內壁形成的共形通孔(conformal via)的形式。
下部基板部分130可包括堆疊於核心絕緣層111的下表面上的下部構成絕緣層131、設置於下部構成絕緣層131上的下部配線圖案132以及穿透過下部構成絕緣層131且對下部配線圖案132與核心配線圖案112進行連接的下部配線通孔133。由於下部基板部分130具有與上部基板部分120的技術特性相似的技術特性,因此將省略對下部構成絕緣層131、下部配線圖案132及下部配線通孔133的說明。下部基板部分130可具有相對於核心基板部分110與上部基板部分120對稱的結構。舉例而言,下部配線通孔133與上部配線通孔123二者均可具有其寬度朝核心基板部分110減小的錐化形狀(tapered shape)。因此,下部配線通孔133與上部配線通孔123可具有在彼此相反的方向上錐化的形狀。
上部基板部分120及下部基板部分130上可分別設置有上部覆蓋層140A及下部覆蓋層140B。上部覆蓋層140A可在其最上側上具有暴露出上部配線圖案122的至少部分的開口,且下部覆蓋層140B可在其最下側上具有暴露出下部配線圖案132的至少部分的開口。上部覆蓋層140A及下部覆蓋層140B可包含上述絕緣材料中的一者。舉例而言,上部覆蓋層140A及下部覆蓋層140B可包含阻焊劑(solder resist)。
在下文中,將參照圖2A及圖2B闡述基礎基板100的經修改實例。圖2A及圖2B僅示出圖1A所示基礎基板100的局部區域。
參照圖2A,在經修改實例中,基礎基板100a可更包括設置於上部基板部分120上的連接導體150。連接導體150可連接至藉由上部覆蓋層140A的開口暴露出的上部配線圖案122。作為連接導體150,可使用導電柱或焊球。連接導體150可改善中介基板200的連接可靠性,以改善半導體封裝1000A的良率。
參照圖2B,在經修改實例中,基礎基板100b可不包括核心基板部分110及下部基板部分130。基礎基板100b可僅包括在一個方向(Y軸方向)上堆疊的上部基板部分120,且上部基板部分120的下表面上可形成有下部基板接墊132P及將下部基板接墊132P連接至上部配線圖案122的下部通孔132C。基礎基板100可具有除圖1A、圖2A及圖2B中所示結構以外的各種結構。具有在水平方向及垂直方向中的每一者上為40毫米或大於40毫米的面積的基板可無限制地用作示例性實施例的基礎基板100。
在下文中,將參照圖3A及圖3B以及圖1A至圖1C闡述中介基板200。圖3A及圖3B示出中介基板200的設置於X-Y平面上的上部重佈線圖案222。
中介基板200可設置於基礎基板100的上表面100S1上,且可具有彼此相對設置的上表面200S1與下表面200S2。中介基板200可包括鄰近於基礎基板100的下部重佈線結構210及設置於下部重佈線結構210的上表面上的上部重佈線結構220。中介基板200可更包括設置於下部重佈線結構210的下表面上的保護絕緣層230。
下部重佈線結構210可包括至少一個下部絕緣層211、設置於下部絕緣層211的兩個表面上的下部重佈線圖案212以及穿透過所述至少一個下部絕緣層211且對不同層中的下部重佈線圖案進行內連的下部重佈線通孔213。
下部絕緣層211可包含絕緣材料。舉例而言,絕緣材料可包括:熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺;或者其中無機填料及/或玻璃纖維(玻璃纖維、玻璃布、玻璃纖維布)與上述樹脂混合的樹脂。舉例而言,可使用味之素構成膜(ABF)、預浸體或類似物。下部絕緣層211可具有單層或多層式結構。舉例而言,參照圖式,下部絕緣層211可具有其中堆疊多個下部絕緣層211(例如,兩層)的形式。在此種情形中,下部重佈線圖案212可作為設置於不同水平上的多個下部重佈線圖案212(例如,三層)來提供。舉例而言,參照圖式,所述多個下部重佈線圖案212(例如,三層)中的最上一者可隱埋於所述多個下部絕緣層211(例如,兩層)中的最上一者的上表面中,所述多個下部重佈線圖案212中的中間一者可設置於所述多個下部絕緣層211中的最上一者的下表面上,且所述多個下部重佈線圖案212中的最下一者可設置於所述多個下部絕緣層211中的最下一者的下表面上,從而覆蓋所述多個下部重佈線圖案212中的中間一者。在此種情形中,所述多個下部絕緣層211中的最上一者的上表面與所述多個下部重佈線圖案212中的最上一者的上表面可實質上共面。
下部重佈線圖案212可藉由下部連接凸塊21電性連接至核心配線圖案112、上部配線圖案122及下部配線圖案132。下部重佈線圖案212可設置於下部絕緣層211上,且可為設置於不同水平上的多個下部重佈線圖案212。所述多個下部重佈線圖案212中位於最下側上的下部重佈線圖案212可包括藉由保護絕緣層230的開口230H至少局部地暴露出的下部連接墊212P1。下部連接墊212P1的下表面的至少部分可由保護絕緣層230覆蓋。因此,下部連接墊212P1可設置於較中介基板200的下表面200S2高的水平上。
下部重佈線圖案212可包含上述導電材料中的至少一者。類似於基礎基板100的配線圖案,下部重佈線圖案212可包括接地圖案、電源圖案及訊號圖案。下部重佈線圖案212可藉由鍍覆製程形成,且可包括晶種層及位於晶種層上的導電層。
下部重佈線通孔213可穿透過下部絕緣層211,且對形成於不同層中的所述多個下部重佈線圖案212進行電性連接。下部重佈線通孔213可包含相似於下部重佈線圖案212的導電材料。下部重佈線通孔213可為其中穿透下部絕緣層211的通孔孔洞被利用金屬材料填充的填充型通孔或者沿通孔孔洞的壁表面形成的共形型通孔。
上部重佈線結構220可包括至少一個上部絕緣層221、分別設置於所述至少一個上部絕緣層221上的上部重佈線圖案222以及穿透過所述至少一個上部絕緣層221且對不同層的多個上部重佈線圖案222進行內連或將所述至少一個上部重佈線圖案222中的最下一者連接至所述至少一個下部重佈線圖案212中的最上一者的上部重佈線通孔223。
上部絕緣層221可包含絕緣材料,例如感光性樹脂(例如感光成像介電(photoimageable dielectric,PID)樹脂)。在此種情形中,上部絕緣層221可被形成得更薄,且上部重佈線通孔223可被更精細地形成。上部絕緣層221可具有單層或多層式結構。舉例而言,參照圖式,所述至少一個上部絕緣層221可為堆疊的多個上部絕緣層221(例如,三層)。在此種情形中,上部重佈線圖案222可作為設置於不同水平上的多個上部重佈線圖案222(例如,兩層或三層)來提供。舉例而言,參照圖式,所述多個上部重佈線圖案222(例如,三層)中的最下一者可設置於所述多個上部絕緣層221(例如,三層)中的最下一者的上表面上,且所述多個上部重佈線圖案222中的中間一者可設置於所述多個上部絕緣層221中的中間一者的上表面上,且所述多個上部重佈線圖案222中的最上一者可設置於所述多個上部絕緣層221中的最上一者的上表面上。在此種情形中,所述多個上部重佈線圖案222中的最上一者可為柱電極形式的上部連接墊222P1,且所述多個上部重佈線圖案222可包括實質上位於下層及中間層上的兩個重佈線圖案(例如,兩層)。端視製程而定,不同水平的所述多個上部絕緣層221之間的邊界可能不清楚。
上部重佈線圖案222可為電性連接至下部重佈線圖案212且設置於不同水平上的多個上部重佈線圖案222。所述多個上部重佈線圖案222中位於最上側上的上部重佈線圖案222可包括自中介基板200的上表面200S1進一步突出的上部連接墊222P1。
連同圖1C一起參照圖3A,設置於上部連接墊222P1下方的至少一個上部重佈線圖案222c可包括藉由上部重佈線通孔223連接至位於所述至少一個上部重佈線圖案222c或上部連接墊222P1下方的另一上部重佈線圖案的至少一個著陸墊222P2。著陸墊222P2可在垂直方向(Z軸方向)上被上部連接墊222P1交疊。上部連接墊222P1的最大寬度d1可小於著陸墊222P2的最大寬度d2。舉例而言,上部連接墊222P1的最大寬度可在約40微米至50微米的範圍內,且著陸墊222P2的最大寬度可在約50微米至60微米的範圍內。上部連接墊222P1可包括與上部重佈線通孔223一體形成的本體層222P1a以及設置於本體層222P1a上的障壁層222P1b,且障壁層222P1b的厚度可小於本體層222P1a的厚度。本體層222P1a可具有包含銅(Cu)或鎳(Ni)的單層結構,且障壁層222P1b可具有包含鎳(Ni)及/或金(Au)的單層或多層式結構。障壁層222P1b可用於防止上部連接凸塊31與本體層222P1a之間的擴散。
類似於下部重佈線通孔213,上部重佈線通孔223可為填充型通孔或共形型通孔。下部重佈線通孔213可透過藉由例如光刻製程形成通孔孔洞且藉由鍍覆製程填充金屬材料來形成。
上部重佈線結構220與下部重佈線結構210可相對於上部絕緣層221與下部絕緣層211之間的邊界線bs在相反的方向上堆疊。舉例而言,上部重佈線結構220可基於邊界線bs在+Z軸方向上堆疊,且下部重佈線結構210可基於邊界線bs在-Z軸方向上堆疊。因此,所述多個下部重佈線圖案212及所述多個上部重佈線圖案222可基於至少一個下部絕緣層211與至少一個上部絕緣層221之間的邊界線bs在相反的方向上突出。另外,下部重佈線通孔213與上部重佈線通孔223可具有在彼此相反的方向上錐化的形狀。
安裝於大面積封裝基板上的具有高效能的半導體晶片300可具有以精細節距整合的多個連接墊302,且對於與其對應的封裝基板,可使用具有精細節距的配線或者重佈線電路。在本揭露的示例性實施例中,基礎基板100的核心配線圖案112、上部配線圖案122及下部配線圖案(亦稱為「配線圖案」)與中介基板200的下部重佈線圖案212及上部重佈線圖案222可具有不同的線及空間標準。因此,根據示例性實施例的半導體封裝1000A可實施對應於具有高效能的半導體晶片300的線及空間,且可以高良率製造,進而使得產品成本可顯著降低。
在示例性實施例中,核心配線圖案112、上部配線圖案122、下部配線圖案132、下部重佈線圖案212及上部重佈線圖案222可分別具有預定的線及空間標準。核心配線圖案112、上部配線圖案122及下部配線圖案132的線及空間可為40微米或大於40微米及40微米或大於40微米,下部重佈線圖案212的線及空間可為7微米或大於7微米及10微米或大於10微米,且上部重佈線圖案222的線及空間可為5微米或大於5微米及5微米或大於5微米。根據示例性實施例,可藉由最小化精細節距的圖案形成、降低產品的良率以及逐漸調整線及空間來實施對應於具有高效能的半導體晶片的線及空間。
在下文中,將參照圖3B闡述核心配線圖案112、上部配線圖案122、下部配線圖案132、下部重佈線圖案212及上部重佈線圖案222的線及空間。圖3B示出在X-Y平面上在第一方向(X軸方向)上延伸且在第二方向(Y軸方向)上彼此鄰近的一對第一上部重佈線圖案222a與第二上部重佈線圖案222b。
參照圖3B,線(L)及空間(S)可被定義為金屬配線(或重佈線圖案)的線寬L及彼此鄰近的配線之間的距離(或「間隔距離」)(S)。舉例而言,當彼此鄰近的所述一對第一上部重佈線圖案222a與第二上部重佈線圖案222b中的每一者的部分在第一方向(X軸方向)上延伸時,第一上部重佈線圖案222a或第二上部重佈線圖案222b在第二方向(Y軸方向)上的線寬L可在約5微米至10微米的範圍內,且第一上部重佈線圖案222a與第二上部重佈線圖案222b之間在第二方向(例如,Y軸方向)上的空間S可在約5微米至10微米的範圍內。
相似地,當彼此鄰近的一對下部重佈線圖案212中的每一者的部分在第一方向(X軸方向)上延伸時,下部重佈線圖案212在第二方向(Y軸方向)上的線寬L可在約7微米至20微米的範圍內,且所述一對下部重佈線圖案212之間在第二方向(例如,Y軸方向)上的距離S可在約10微米至20微米的範圍內。
相似地,當核心配線圖案112、上部配線圖案122及下部配線圖案132在第一方向(X軸方向)上延伸時,配線圖案中的每一者在第二方向(Y軸方向)上的線寬L可在約40微米至70微米的範圍內,且核心配線圖案112、上部配線圖案122及下部配線圖案132中設置於同一水平上且在第二方向(Y軸方向)上彼此鄰近的一對之間的距離S可在40微米至70微米的範圍內。
另外,在示例性實施例中,中介基板200中的下部重佈線通孔213及上部重佈線通孔223的大小可不同。上部重佈線通孔223的直徑可小於下部重佈線通孔213的直徑。舉例而言,下部重佈線通孔213的最大直徑可在約60微米至80微米的範圍內,且上部重佈線通孔223的最大直徑可在約10微米至30微米的範圍內。
半導體封裝1000A可更包括外部連接凸塊11、下部連接凸塊21及上部連接凸塊31(亦稱為「連接凸塊」)。外部連接凸塊11可設置於基礎基板100的下表面100S2上,且可電性連接至核心配線圖案112、上部配線圖案122及下部配線圖案132。下部連接凸塊21可設置於基礎基板100與中介基板200之間,且可將核心配線圖案112、上部配線圖案122及下部配線圖案132與下部重佈線圖案212連接。上部連接凸塊31可設置於半導體晶片300與中介基板200之間,且可對半導體晶片300的連接墊302與上部重佈線圖案222進行連接。連接凸塊可具有倒裝晶片連接結構,所述倒裝晶片連接結構具有焊球、導電凸塊或例如引腳柵陣列(pin grid array)、球柵陣列(ball grid array)及接腳柵陣列(land grid array)等柵陣列。
根據本揭露的實施例,用於連接半導體晶片300的凸塊節距(即,高效能)可藉由逐漸改變配線圖案、下部重佈線圖案及上部重佈線圖案的線及空間來實施。舉例而言,彼此鄰近的一對外部連接凸塊11之間的距離在約0.8毫米至1.5毫米的範圍內,彼此鄰近的一對下部連接凸塊21之間的距離在約0.1毫米至0.7毫米的範圍內,且彼此鄰近的一對上部連接凸塊31之間的距離可在約50微米至150微米的範圍內。下部連接凸塊21及上部連接凸塊31可分別由包含環氧樹脂的下部底部填充樹脂22及上部底部填充樹脂32保護。
在示例性實施例中,當電性訊號穿過核心配線圖案112、上部配線圖案122、下部配線圖案132、下部重佈線圖案212、上部重佈線圖案222、外部連接凸塊11、下部連接凸塊21及上部連接凸塊31時,可能發生阻抗失配(impedance mismatch)。因此,核心配線圖案112、上部配線圖案122及下部配線圖案132可包括用於補償電訊號的阻抗失配的阻抗匹配電路。阻抗匹配電路可包括於設置於相對較低層上的下部配線圖案132及/或核心配線圖案112中,以便增加傳輸線的長度。
保護絕緣層230可設置於與下部絕緣層211的上面設置有上部絕緣層221的一個表面相對的另一表面上。保護絕緣層230可覆蓋所述多個下部重佈線圖案212中的最下一者的至少部分。保護絕緣層230可包含例如:熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺;或者絕緣樹脂,例如其中無機填料及/或玻璃纖維與該些樹脂混合的樹脂。保護絕緣層230可包含不同於下部絕緣層211及上部絕緣層221的絕緣樹脂。舉例而言,保護絕緣層230可包含ABF,下部絕緣層211可包含預浸體,且上部絕緣層221可包含PID。
在下文中,將參照圖4A至圖4D闡述中介基板200的製造製程。圖4A至圖4D是示意性地示出圖1A及圖1C所示中介基板200的製造製程的剖視圖。
參照圖4A,可在第一載體C1上形成下部重佈線圖案212。圖4A中所示下部重佈線圖案212可對應於鄰近於圖1C所示的「bs」線的最上下部重佈線圖案。下部重佈線圖案212可藉由鍍覆製程及蝕刻製程形成。
參照圖4B,可在圖4A所示下部重佈線圖案212上形成多個下部絕緣層211、多個下部重佈線通孔213及多個下部重佈線圖案212。舉例而言,如圖式中所示,可形成兩層下部絕緣層211、三層下部重佈線圖案212及兩層下部重佈線通孔213。可藉由對絕緣膜進行疊層且然後對其進行固化來形成下部絕緣層211。可使用例如預浸體來形成下部絕緣層211。參照圖4B,可在自多個下部絕緣層211中的最上一者突出的下部重佈線圖案212上形成保護絕緣層230。亦可使用絕緣膜來形成保護絕緣層230。舉例而言,可使用ABF來形成保護絕緣層230。
參照圖4C,在移除圖4B所示第一載體C1之後,可將下部重佈線結構210翻轉且貼合至第二載體C2。在圖4B中,面對第一載體C1的表面可為與稍後欲形成的上部重佈線結構220的邊界線bs。參照圖4C,所述多個下部重佈線圖案212中的最上一者的上表面與所述多個下部絕緣層211中的最上一者的上表面可彼此共面。
參照圖4D,可在下部重佈線結構210上形成多個上部絕緣層221、多個上部重佈線圖案222及多個上部重佈線通孔223。在圖式中,可不包括自所述多個上部絕緣層221中的最上一者突出的上部連接墊221P1以及將所述上部連接墊221P1連接至上部重佈線圖案222的通孔。舉例而言,如圖式中所示,可形成三層上部絕緣層221、兩層上部重佈線圖案222及兩層上部重佈線通孔223。此後,可移除第二載體C2,且可形成用於自保護絕緣層230暴露出所述多個下部重佈線圖案212中的最下一者的開口。亦可在固化圖4B中的保護絕緣層230之後形成保護絕緣層230的所述開口。
如在圖4A至圖4D中所述,由於下部重佈線結構210的構成方向與上部重佈線結構220的構成方向彼此不同,因此下部重佈線圖案212的形成方向與上部重佈線圖案222的形成方向可彼此相反。舉例而言,下部重佈線圖案212的突出方向與上部重佈線圖案222的突出方向可基於下部絕緣層211與上部絕緣層221之間的邊界線bs而彼此相反。相似地,下部重佈線通孔213的錐化方向與上部重佈線通孔223的錐化方向可彼此相反。
可在中介基板200的上表面200S1上設置半導體晶片(或半導體結構)300,且半導體晶片(或半導體結構)300可包括電性連接至上部重佈線圖案222的連接墊302。半導體晶片300可為其中多個積體電路(integrated circuit,IC)形成於晶圓301上的IC晶片。半導體晶片300可包括:邏輯晶片,例如中央處理器(central processor,CPU)、圖形處理器(graphics processor,GPU)、現場可程式化閘陣列(field programmable gate array,FPGA)、數位訊號處理器、密碼處理器、微處理器、微控制器、類比-數位轉換器、特殊應用IC(application-specific IC,ASIC)、包括高速串聯-並聯轉換電路的串聯器及解串器IC(serializer and deserializer IC,SerDes IC);或者揮發性記憶體晶片,例如動態隨機存取記憶體(dynamic RAM,DRAM)、靜態隨機存取記憶體(static RAM,SRAM)及類似物;或者非揮發性記憶體晶片,例如相變隨機存取記憶體(phase change RAM,PRAM)、磁性隨機存取記憶體(magnetic RAM,MRAM)、電阻式隨機存取記憶體(resistive RAM,RRAM)、快閃記憶體及類似物。
可在基礎基板100的上表面100S1上設置散熱結構400,且散熱結構400可覆蓋中介基板200及半導體晶片300。可藉由黏合劑將散熱結構400貼合至基礎基板100。作為黏合劑,可使用導熱黏合帶、導熱油脂、導熱黏合劑或類似物。散熱結構400可藉由半導體晶片300的上表面上的黏合構件303(例如,黏合劑)與半導體晶片300緊密接觸。散熱結構400可包含具有極佳導熱性的導電材料。舉例而言,散熱結構400可包含導電材料,例如包含金(Au)、銀(Ag)、銅(Cu)、鐵(Fe)或類似物的金屬或金屬合金或者石墨、石墨烯或類似物。散熱結構400可具有不同於圖式中所示形狀的形狀,且在其他示例性實施例中可省略散熱結構400。相反,散熱結構400可更包括於稍後闡述的示例性實施例中。
圖5是示出根據本揭露示例性實施例的半導體封裝1000B的剖視圖。
參照圖5,半導體封裝1000B可更包括被動元件240,被動元件240設置於中介基板200的下表面200S2上且電性連接至下部重佈線圖案212。被動元件240可設置於中介基板200與基礎基板100之間的空間中。舉例而言,被動元件240可包括例如多層陶瓷電容器(multi-layer ceramic capacitor,MLCC)或低電感晶片電容器(low inductance chip capacitor,LICC)等電容器、電感器、珠粒(bead)及類似物。在示例性實施例中,被動元件240可包括設置於多個下部連接凸塊21之間的搭接側電容器(Land-Side Capacitor,LSC)。被動元件240鄰近於半導體晶片300貼合至中介基板200的下表面,以使得可改善訊號完整性(Signal Integrity,SI)及電源完整性(Power Integrity,PI)特性。
圖6A及圖6B是示出根據本揭露示例性實施例的半導體封裝1000C的剖視圖及平面圖。圖6A是沿圖6B所示的線II-II’截取的剖視圖。
參照圖6A及圖6B,半導體封裝1000C可更包括多個被動元件500,所述多個被動元件500被設置成在基礎基板100的上表面100S1上鄰近於中介基板200,且電性連接至配線圖案或上部配線圖案122。被動元件500可包括例如電容器、電感器、珠粒及類似物。被動元件500可以倒裝晶片方式安裝於基礎基板100上。在示例性實施例中,當應用圖1A所示散熱結構400時,被動元件500可設置於散熱結構400內部。被動元件500可改善SI及PI特性。
圖7A及圖7B是示出根據本揭露示例性實施例的半導體封裝1000D的剖視圖及平面圖。圖7A是沿圖7B所示的線III-III’截取的剖視圖。
參照圖7A及圖7B,在半導體封裝1000D中,半導體晶片300可包括在與中介基板200的上表面200S1水平的方向(X軸方向)上彼此間隔開的第一半導體結構310與第二半導體結構320。第一半導體結構310及第二半導體結構320可藉由中介基板200的上部重佈線圖案222及上部重佈線通孔223彼此電性連接。第一半導體結構310與第二半導體結構320可包括不同類型的半導體晶片。
舉例而言,第一半導體結構310可包括例如CPU、GPU、數位訊號處理器、加密處理器、微處理器、微控制器及類似物等應用處理器晶片以及例如類比至數位轉換器、ASIC及類似物等邏輯晶片,且第二半導體結構320可包括例如DRAM、SRAM、快閃、PRAM、ReRAM、FeRAM、MRAM或高頻寬記憶體(high bandwidth memory,HBM)或混合記憶體立方(hybrid memory cubic,HMC)等記憶體半導體。
圖8A至圖8E是示意性地示出圖1所示半導體封裝1000A的製造製程的剖視圖。
參照圖8A,可在基礎基板100上安裝中介基板200。基礎基板100可具有為40毫米或大於40毫米的水平/垂直寬度,且中介基板200可分別具有為20毫米或大於20毫米的水平/垂直寬度。可藉由下部連接凸塊21將中介基板200貼合至基礎基板100,且可將中介基板200電性連接至配線圖案或上部配線圖案122。下部連接凸塊21可包括焊球。可藉由迴焊製程(reflow process)將中介基板200貼合至基礎基板100。
參照圖8B,接下來,可在中介基板200與基礎基板100之間形成下部底部填充樹脂22,以保護下部連接凸塊21。可藉由在中介基板200與基礎基板100之間塗佈底部填充樹脂材料(例如,環氧樹脂)且然後固化來形成下部底部填充樹脂22。在一些情形中,可省略下部底部填充樹脂22。
參照圖8C,可在中介基板200上設置半導體晶片300。半導體晶片300可為例如ASIC等邏輯晶片。可藉由上部連接凸塊31將半導體晶片300物理連接至且電性連接至中介基板200。可在半導體晶片300上設置黏合構件303。黏合構件303可包含包括環氧樹脂的黏合材料。黏合構件303亦可包含具有極佳導熱性的材料。
參照圖8D,可在半導體晶片300與中介基板200之間形成上部底部填充樹脂32,以保護上部連接凸塊31。上部底部填充樹脂32可由與下部底部填充樹脂22相似的材料及方法形成。在一些情形中,可省略上部底部填充樹脂32。
參照圖8E,可將覆蓋中介基板200及半導體晶片300的散熱結構400貼合至基礎基板100。可藉由例如環氧樹脂等黏合劑將散熱結構400貼合至基礎基板100的上表面100S1。另外,可藉由黏合構件303使散熱結構400與半導體晶片300緊密接觸。散熱結構400可包含用於散熱及屏蔽電磁波的導電材料。
如上所述,根據本揭露的示例性實施例,可藉由逐漸調整重佈線圖案的大小來提供具有極佳良率及降低的製造成本的半導體封裝。
在本文中,關於圖式的橫截面使用下側、下部部分、下表面及類似用語來指代朝向扇出型半導體封裝的安裝表面的方向,而使用上側、上部部分、上表面及類似用語指代與所述方向相反的方向。然而,該些方向是為便於闡述而界定,且申請專利範圍不受如上文所述界定的方向的特別限制。
在說明中組件「連接」至另一組件的含義包括兩個組件之間經由黏合層的間接連接以及兩個組件之間的直接連接。另外,「電性連接」在概念上包括實體連接及實體斷開連接。可理解,當使用例如「第一」及「第二」等用語提及元件時,所述元件不會因此而受限制。所述用語可僅用於將元件與其他元件作出區分的目的,且可不限制元件的順序或重要性。在一些情形中,第一元件可被稱為第二元件,而此並不背離本文中所陳述的申請專利範圍的範疇。相似地,第二元件亦可被稱為第一元件。
本文中所使用的用語「示例性實施例」不指代同一示例性實施例,且是為強調與另一示例性實施例的特徵或特性不同的特定特徵或特性而提供。然而,本文中所提供的示例性實施例被視為能夠藉由將示例性實施例整體地或部分地彼此組合來實施。舉例而言,特定示例性實施例中所述的一個元件即使在另一示例性實施例中未加以闡述,仍可被理解為與另一示例性實施例相關的說明,除非本文中提供相對或對立的說明。
本文中所使用的用語僅是為了闡述示例性實施例而使用,而非限制本揭露。在此種情形中,單數形式包括複數形式,除非上下文中另有解釋。
儘管以上已示出及闡述示例性實施例,然而對於熟習此項技術者而言將顯而易見,可在不背離本發明的範圍的情況下作出修改及變化。
11:外部連接凸塊
21:下部連接凸塊
22:下部底部填充樹脂
31:上部連接凸塊
32:上部底部填充樹脂
100、100a、100b:基礎基板
100S1、200S1:上表面
100S2、200S2:下表面
110:核心基板部分
111:核心絕緣層
112:核心配線圖案
113:穿孔
120:上部基板部分
121:上部構成絕緣層
122:上部配線圖案
123:上部配線通孔
130:下部基板部分
131:下部構成絕緣層
132:下部配線圖案
132C:下部通孔
132P:下部基板接墊
133:下部配線通孔
140A:上部覆蓋層
140B:下部覆蓋層
150:連接導體
200:中介基板
210:下部重佈線結構
211:下部絕緣層
212:下部重佈線圖案
212P1:下部連接墊
213:下部重佈線通孔
220:上部重佈線結構
221:上部絕緣層
221P1、222P1:上部連接墊
222、222c:上部重佈線圖案
222a:第一上部重佈線圖案
222b:第二上部重佈線圖案
222P1a:本體層
222P1b:障壁層
222P2:著陸墊
223:上部重佈線通孔
230:保護絕緣層
230H:開口
240、500:被動元件
300:半導體晶片/半導體結構
301:晶圓
302:連接墊
303:黏合構件
310:第一半導體結構
320:第二半導體結構
400:散熱結構
1000A、1000B、1000C、1000D:半導體封裝
A:區域
bs:邊界線
C1:第一載體
C2:第二載體
d1、d2:最大寬度
I-I’、II-II’、III-III’:線
L:線/線寬
S:空間/距離/間隔距離
X、Y、Z:軸
藉由結合附圖閱讀以下詳細說明,將更清楚地理解本揭露的實施例的以上及其他態樣、特徵及優點,在附圖中:
圖1A是示出根據本揭露示例性實施例的半導體封裝的剖視圖。
圖1B是示出根據本揭露示例性實施例的半導體封裝的平面圖。
圖1C是根據本揭露示例性實施例的半導體封裝的局部放大剖視圖。
圖2A是示出圖1A所示基礎基板的第一經修改實例的剖視圖。
圖2B是示出圖1A所示基礎基板的第二經修改實例的剖視圖。
圖3A是示出圖1A及圖1C所示中介基板的一些組件的第一局部放大平面圖。
圖3B是示出圖1A及圖1C所示中介基板的一些組件的第二局部放大平面圖。
圖4A是示意性地示出圖1A及圖1C所示中介基板的製造製程的第一剖視圖。
圖4B是示意性地示出圖1A及圖1C所示中介基板的製造製程的第二剖視圖。
圖4C是示意性地示出圖1A及圖1C所示中介基板的製造製程的第三剖視圖。
圖4D是示意性地示出圖1A及圖1C所示中介基板的製造製程的第四剖視圖。
圖5是示出根據本揭露示例性實施例的半導體封裝的剖視圖。
圖6A是示出根據本揭露示例性實施例的半導體封裝的剖視圖。
圖6B是示出根據本揭露示例性實施例的半導體封裝的平面圖。
圖7A是示出根據本揭露示例性實施例的半導體封裝的剖視圖。
圖7B是示出根據本揭露示例性實施例的半導體封裝的平面圖。
圖8A是示意性地示出圖1A所示半導體封裝的製造製程的第一剖視圖。
圖8B是示意性地示出圖1A所示半導體封裝的製造製程的第二剖視圖。
圖8C是示意性地示出圖1A所示半導體封裝的製造製程的第三剖視圖。
圖8D是示意性地示出圖1A所示半導體封裝的製造製程的第四剖視圖。
圖8E是示意性地示出圖1A所示半導體封裝的製造製程的第五剖視圖。
11:外部連接凸塊
21:下部連接凸塊
22:下部底部填充樹脂
31:上部連接凸塊
32:上部底部填充樹脂
100:基礎基板
100S1、200S1:上表面
100S2、200S2:下表面
110:核心基板部分
111:核心絕緣層
112:核心配線圖案
113:穿孔
120:上部基板部分
121:上部構成絕緣層
122:上部配線圖案
123:上部配線通孔
130:下部基板部分
131:下部構成絕緣層
132:下部配線圖案
133:下部配線通孔
140A:上部覆蓋層
140B:下部覆蓋層
200:中介基板
210:下部重佈線結構
220:上部重佈線結構
230:保護絕緣層
300:半導體晶片/半導體結構
301:晶圓
302:連接墊
303:黏合構件
400:散熱結構
1000A:半導體封裝
A:區域
X、Y、Z:軸
Claims (20)
- 一種半導體封裝,包括: 基礎基板,具有彼此相對的上表面與下表面,且包括配線圖案; 中介基板,設置於所述基礎基板的所述上表面上,且具有彼此相對的上表面與下表面,且包括電性連接至所述配線圖案的至少一個下部重佈線圖案及設置於所述至少一個下部重佈線圖案上且電性連接至所述至少一個下部重佈線圖案的至少一個上部重佈線圖案; 半導體結構,設置於所述中介基板的所述上表面上,且電性連接至所述至少一個上部重佈線圖案; 散熱結構,設置於所述基礎基板的所述上表面上,且覆蓋所述中介基板及所述半導體結構; 多個外部連接凸塊,設置於所述基礎基板的所述下表面上,且連接至所述配線圖案; 多個下部連接凸塊,設置於所述基礎基板與所述中介基板之間,且連接所述配線圖案與所述至少一個下部重佈線圖案;以及 多個上部連接凸塊,設置於所述中介基板與所述半導體結構之間,且連接所述至少一個上部重佈線圖案與所述半導體結構, 其中所述多個外部連接凸塊中彼此鄰近的一對外部連接凸塊之間的距離在0.8毫米至1.5毫米的範圍中, 所述多個下部連接凸塊中彼此鄰近的一對下部連接凸塊之間的距離在0.1毫米至0.7毫米的範圍中,且 所述多個上部連接凸塊中彼此鄰近的一對上部連接凸塊之間的距離在50微米至150微米的範圍中。
- 如請求項1所述的半導體封裝,其中所述配線圖案、所述至少一個下部重佈線圖案及所述至少一個上部重佈線圖案在第一方向上延伸, 其中所述配線圖案在垂直於所述第一方向的第二方向上的線寬在40微米至70微米的範圍中, 所述至少一個下部重佈線圖案在所述第二方向上的線寬在7微米至20微米的範圍中,且 所述至少一個上部重佈線圖案在所述第二方向上的線寬在5微米至10微米的範圍中。
- 如請求項1所述的半導體封裝,其中所述基礎基板的最小寬度在40毫米至80毫米的範圍內,且 所述中介基板的最小寬度在10毫米至20毫米的範圍內。
- 如請求項1所述的半導體封裝,更包括設置於所述中介基板的所述下表面上且電性連接至所述至少一個下部重佈線圖案的被動元件。
- 如請求項1所述的半導體封裝,其中所述至少一個下部重佈線圖案及所述至少一個上部重佈線圖案分別是位於不同水平(level)上的多個下部重佈線圖案及多個上部重佈線圖案, 其中所述中介基板更包括: 至少一個下部絕緣層,其上設置有所述多個下部重佈線圖案; 下部重佈線通孔,穿過所述至少一個下部絕緣層以對所述多個下部重佈線圖案進行互連(interconnect); 至少一個上部絕緣層,其上設置有所述多個上部重佈線圖案,且堆疊於所述至少一個下部絕緣層的一個表面上; 上部重佈線通孔,穿過所述至少一個上部絕緣層以對所述多個上部重佈線圖案進行互連或對所述多個上部重佈線圖案與所述多個下部重佈線圖案進行連接;以及 保護絕緣層,設置於所述至少一個下部絕緣層的與所述至少一個下部絕緣層的所述一個表面相對的另一表面上,且覆蓋所述多個下部重佈線圖案的至少部分, 其中所述多個下部重佈線圖案及所述多個上部重佈線圖案基於所述至少一個下部絕緣層與所述至少一個上部絕緣層之間的接觸邊界線在相反的方向上突出。
- 如請求項5所述的半導體封裝,其中所述至少一個上部絕緣層包含感光性樹脂, 其中所述至少一個下部絕緣層及所述保護絕緣層包含非感光性樹脂。
- 如請求項5所述的半導體封裝,其中所述下部重佈線通孔與所述上部重佈線通孔具有在彼此相反的方向上成錐形的形狀。
- 如請求項5所述的半導體封裝,其中所述下部重佈線通孔的最大直徑在60微米至80微米的範圍中,且所述上部重佈線通孔的最大直徑在10微米至30微米的範圍中。
- 如請求項5所述的半導體封裝,其中所述多個上部重佈線圖案中的最上上部重佈線圖案包括設置於較所述中介基板的所述上表面高的水平上的上部連接墊,且 所述多個下部重佈線圖案中的最下下部重佈線圖案包括設置於較所述中介基板的所述下表面高的水平上的下部連接墊, 其中所述保護絕緣層具有暴露出所述下部連接墊的至少部分且容置所述多個下部連接凸塊中的一者的開口。
- 如請求項1所述的半導體封裝,更包括: 下部底部填充樹脂,設置於所述基礎基板與所述中介基板之間,且環繞所述多個下部連接凸塊;以及 上部底部填充樹脂,設置於所述中介基板與所述半導體結構之間,且環繞所述多個上部連接凸塊。
- 如請求項1所述的半導體封裝,更包括: 多個被動元件,鄰近於所述中介基板設置於所述基礎基板的所述上表面上,且電性連接至所述配線圖案。
- 如請求項1所述的半導體封裝,其中所述半導體結構包括在與所述中介基板的所述上表面水平的方向上彼此間隔開的第一半導體結構與第二半導體結構。
- 如請求項12所述的半導體封裝,其中所述第一半導體結構包括邏輯晶片,且所述第二半導體結構包括記憶體晶片。
- 如請求項1所述的半導體封裝,其中所述基礎基板更包括核心絕緣層,且更包括分別堆疊於所述核心絕緣層的上表面及下表面上的上部構成絕緣層及下部構成絕緣層, 其中所述配線圖案包括分別設置於所述核心絕緣層的所述上表面及所述下表面上的核心配線圖案,且更包括分別設置於所述上部構成絕緣層及所述下部構成絕緣層上的上部配線圖案及下部配線圖案。
- 如請求項14所述的半導體封裝,其中所述基礎基板更包括上部配線通孔及下部配線通孔,所述上部配線通孔穿過所述上部構成絕緣層且將所述上部配線圖案連接至設置於所述核心絕緣層的所述上表面上的所述核心配線圖案,所述下部配線通孔穿過所述下部構成絕緣層且將所述下部配線圖案連接至設置於所述核心絕緣層的所述下表面上的所述核心配線圖案, 其中所述下部配線通孔與所述上部配線通孔具有在彼此相反的方向上成錐形的形狀。
- 一種半導體封裝,包括: 基礎基板,包括配線圖案; 中介基板,設置於所述基礎基板上,且包括設置於不同水平上且電性連接至所述配線圖案的多個下部重佈線圖案及電性連接至所述多個下部重佈線圖案的多個上部重佈線圖案;以及 半導體結構,設置於所述中介基板上且電性連接至所述多個上部重佈線圖案, 其中所述多個上部重佈線圖案中的最上上部重佈線圖案包括自所述中介基板的上表面突出的上部連接墊, 所述多個上部重佈線圖案中設置於所述上部連接墊下方的至少一者包括與所述上部連接墊交疊的著陸墊,且 所述上部連接墊的最大寬度小於所述著陸墊的最大寬度。
- 如請求項16所述的半導體封裝,其中所述上部連接墊的所述最大寬度在40微米至50微米的範圍中,且所述著陸墊的所述最大寬度在50微米至60微米的範圍中。
- 如請求項16所述的半導體封裝,其中所述上部連接墊包括本體層及設置於所述本體層上的障壁層, 其中所述障壁層的厚度小於所述本體層的厚度。
- 一種半導體封裝,包括: 基礎基板,包括配線圖案; 中介基板,設置於所述基礎基板上,且包括電性連接至所述配線圖案的多個下部重佈線圖案及電性連接至所述多個下部重佈線圖案的多個上部重佈線圖案;以及 半導體結構,設置於所述中介基板上且電性連接至所述多個上部重佈線圖案, 其中所述多個下部重佈線圖案及所述多個上部重佈線圖案在第一方向上延伸, 所述多個下部重佈線圖案在垂直於所述第一方向的第二方向上的線寬在7微米至20微米的範圍中, 所述多個上部重佈線圖案在所述第二方向上的線寬在5微米至10微米的範圍中, 所述多個下部重佈線圖案中設置於同一水平上且在所述第二方向上彼此鄰近的一對下部重佈線圖案之間的距離在10微米至20微米的範圍中,且 所述多個上部重佈線圖案中設置於同一水平上且在所述第二方向上彼此鄰近的一對上部重佈線圖案之間的距離在5微米至10微米的範圍中。
- 如請求項19所述的半導體封裝,其中所述配線圖案包括阻抗匹配電路,所述阻抗匹配電路被配置成補償由所述多個下部重佈線圖案及所述多個上部重佈線圖案引起的阻抗失配(impedance mismatch)。
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Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3967108B2 (ja) | 2001-10-26 | 2007-08-29 | 富士通株式会社 | 半導体装置およびその製造方法 |
JP3961537B2 (ja) | 2004-07-07 | 2007-08-22 | 日本電気株式会社 | 半導体搭載用配線基板の製造方法、及び半導体パッケージの製造方法 |
JP2010157690A (ja) | 2008-12-29 | 2010-07-15 | Ibiden Co Ltd | 電子部品実装用基板及び電子部品実装用基板の製造方法 |
US9385095B2 (en) | 2010-02-26 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
KR101767108B1 (ko) * | 2010-12-15 | 2017-08-11 | 삼성전자주식회사 | 하이브리드 기판을 구비하는 반도체 패키지 및 그 제조방법 |
JP2014154800A (ja) | 2013-02-13 | 2014-08-25 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法 |
US9349703B2 (en) | 2013-09-25 | 2016-05-24 | Intel Corporation | Method for making high density substrate interconnect using inkjet printing |
US9622350B2 (en) | 2013-09-28 | 2017-04-11 | Intel Corporation | Method of forming a circuit board |
US9659853B2 (en) | 2015-04-24 | 2017-05-23 | Advanced Semiconductor Engineering, Inc. | Double side via last method for double embedded patterned substrate |
US10283492B2 (en) | 2015-06-23 | 2019-05-07 | Invensas Corporation | Laminated interposers and packages with embedded trace interconnects |
WO2017039628A1 (en) | 2015-08-31 | 2017-03-09 | Daniel Sobieski | Inorganic interposer for multi-chip packaging |
US9673148B2 (en) | 2015-11-03 | 2017-06-06 | Dyi-chung Hu | System in package |
TWI609468B (zh) | 2017-01-16 | 2017-12-21 | 欣興電子股份有限公司 | 封裝體裝置及其製造方法 |
US20190287872A1 (en) | 2018-03-19 | 2019-09-19 | Intel Corporation | Multi-use package architecture |
US10535608B1 (en) | 2018-07-24 | 2020-01-14 | International Business Machines Corporation | Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate |
JP2020088069A (ja) | 2018-11-20 | 2020-06-04 | 凸版印刷株式会社 | 半導体パッケージ基板およびその製造方法 |
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2020
- 2020-10-07 KR KR1020200129209A patent/KR20220046134A/ko unknown
-
2021
- 2021-06-22 US US17/354,291 patent/US11798862B2/en active Active
- 2021-07-22 TW TW110126887A patent/TW202230651A/zh unknown
- 2021-09-27 CN CN202111134034.6A patent/CN114300440A/zh active Pending
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2023
- 2023-09-27 US US18/475,926 patent/US20240030089A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
US11798862B2 (en) | 2023-10-24 |
CN114300440A (zh) | 2022-04-08 |
US20240030089A1 (en) | 2024-01-25 |
KR20220046134A (ko) | 2022-04-14 |
US20220108935A1 (en) | 2022-04-07 |
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