TW202220160A - 連接至處理單元之半導體記憶體堆疊以及相關系統及方法 - Google Patents

連接至處理單元之半導體記憶體堆疊以及相關系統及方法 Download PDF

Info

Publication number
TW202220160A
TW202220160A TW110124911A TW110124911A TW202220160A TW 202220160 A TW202220160 A TW 202220160A TW 110124911 A TW110124911 A TW 110124911A TW 110124911 A TW110124911 A TW 110124911A TW 202220160 A TW202220160 A TW 202220160A
Authority
TW
Taiwan
Prior art keywords
die
conductive elements
conductive
memory controller
group
Prior art date
Application number
TW110124911A
Other languages
English (en)
Other versions
TWI785666B (zh
Inventor
凱爾 K 克比
Original Assignee
美商美光科技公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商美光科技公司 filed Critical 美商美光科技公司
Publication of TW202220160A publication Critical patent/TW202220160A/zh
Application granted granted Critical
Publication of TWI785666B publication Critical patent/TWI785666B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385Assembly of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0239Material of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081Disposition
    • H01L2224/0812Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13025Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701Structure
    • H01L2224/1703Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705Shape
    • H01L2224/17051Bump connectors having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808Bonding techniques
    • H01L2224/80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808Bonding techniques
    • H01L2224/80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80905Combinations of bonding methods provided for in at least two different groups from H01L2224/808 - H01L2224/80904
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06527Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)

Abstract

本發明揭示一種連接至一處理單元之半導體記憶體堆疊以及相關方法及系統。在一些實施例中,該半導體記憶體堆疊可包括附接至一記憶體控制器晶粒(例如,高頻寬記憶體)且由該記憶體控制器晶粒承載的一或多個記憶體晶粒。此外,一處理單元(例如,一處理器)可在無一內插件的情況下附接至該記憶體控制器晶粒,以為在該半導體記憶體堆疊與該處理單元之間行進的信號提供最短可能路線。另外,該半導體記憶體堆疊及該處理單元可在無一內插件的情況下附接至一封裝基板。

Description

連接至處理單元之半導體記憶體堆疊以及相關系統及方法
本發明大體上係關於半導體裝置總成,且更特定言之,係關於連接至處理單元之半導體記憶體堆疊以及相關系統及方法。
半導體封裝通常包括安裝在基板上且圍封於保護蓋中的一或多個半導體晶粒(例如,記憶體晶片、微處理器晶片、成像器晶片)。半導體晶粒可包括功能特徵,諸如記憶體胞元、處理器電路或成像器裝置,以及電連接至功能特徵之接合襯墊。接合襯墊可電連接至基板之對應導電結構,該等導電結構可耦接至保護蓋外部之端子,使得半導體晶粒可連接至較高層級電路系統。
下文描述連接至處理單元的一或多個半導體記憶體堆疊以及相關系統及方法的若干實施例的特定細節。術語「半導體裝置或晶粒」一般係指包括一或多種半導體材料之固態裝置。半導體裝置的實例包括邏輯裝置或晶粒、記憶體裝置或晶粒、控制器或微處理器(例如,中央處理單元(CPU)、圖形處理單元(GPU))等。此類半導體裝置可包括積體電路或組件、資料儲存元件、處理組件及/或製造於半導體基板上之其他特徵。此外,術語「半導體裝置或晶粒」可指成品裝置或在變為成品功能裝置之前的各種處理階段處的總成或其他結構。取決於使用其之上下文,術語「基板」可包括半導體晶圓、封裝支撐基板、半導體裝置或晶粒,等。一般熟習相關技術者將認識到,本文中所描述之方法的適當步驟可藉由與製造半導體裝置(晶圓級及/或晶粒級)及/或製造半導體封裝相關的處理步驟來執行。
某些計算系統,例如高效能計算(HPC)系統,包括與包括堆疊於控制器上方之一或多個記憶體晶粒(例如,DRAM晶粒)的高頻寬記憶體(HBM)耦接之處理器。在一些實施例中,處理器及HBM可並排附著至包括導電跡線之內插件,該內插件為處理器與HBM之間的信號提供通信路徑。在一些情況下,內插件可成為用於設計計算系統以在HPC環境中操作的瓶頸,此係因為維持經由內插件傳輸及/或接收的信號的保真度變得愈來愈具有挑戰性,例如,歸因於信號在HBM與處理器之間行進的距離。此外,鑒於利用應用於矽基板(例如,Si內插件)之各種半導體製程技術所製造的內插件,內插件增加計算系統之總成本。
本發明技術消除對內插件(例如,Si內插件)之需要,且提供用於連接半導體記憶體堆疊與處理單元之最短可能路線。該半導體記憶體堆疊可包括附接至控制器晶粒(例如,HBM)且由該控制器晶粒承載的一或多個記憶體晶粒(或記憶體晶粒堆疊)。如本文中更詳細地描述,半導體記憶體堆疊的控制器晶粒可附接至封裝基板,其中其前表面或前側背對封裝基板(即,控制器晶粒的背側面向封裝基板)而無內插件。另外,處理單元可配置於控制器晶粒(及封裝基板)上方,其前表面或前側面向控制器晶粒(及封裝基板)。此外,處理單元之第一區可直接附接至控制器晶粒之未覆蓋部分(即,不受記憶體晶粒阻礙),使得控制器晶粒與處理單元可在其間建立電連接,例如,直接晶片至晶片連接而無內插件。
另外,處理單元可在不使用內插件的情況下與封裝基板建立電連接。即,並不直接附接至控制器晶粒的處理單元之第二區可經由導電柱及/或焊球與封裝基板之導電組件(例如,接合襯墊)耦接。以此方式,本發明技術提供半導體記憶體堆疊(即,承載記憶體晶粒的控制器晶粒)與導電跡線的處理單元之間的不存在內插件的最短可能路線,同時將半導體記憶體堆疊(即,承載記憶體晶粒的控制器晶粒)及處理單元兩者直接連接至封裝基板而無內插件。
如本文中所使用,術語「前」、「後(背)」、「垂直」、「橫向」、「向下」、「向上」、「上部」及「下部」可指鑒於圖中所展示之定向的半導體裝置總成中之特徵的相對方向或位置。舉例而言,「上部」或「最上部」可指與另一特徵相比更接近頁面之頂部定位的特徵。然而,此等術語應被廣泛地解釋為包括具有其他定向的半導體裝置。除非另外說明,否則諸如「第一」及「第二」等詞用以任意地區別此類詞所描述的元件。因此,此等詞未必意欲指示此等元件的時間或其他優先排序。
圖1A說明根據本發明技術之實施例的半導體記憶體堆疊之實例示意圖。半導體記憶體堆疊可為HBM的實例或包括HBM的態樣。圖1A包括半導體記憶體堆疊之三維(3D)圖100a及大體上對應於3D圖100a的示意性截面圖101a。
圖101a描述半導體記憶體堆疊,其包括控制器晶粒105 (其可不同地被稱為控制器、介面(IF)晶粒、邏輯晶粒、HBM控制器晶粒、記憶體控制器晶粒)及附接至控制器晶粒105的記憶體晶粒堆疊125。控制器晶粒105包括前側106及與前側106相對之背側107。記憶體晶粒堆疊125附接至控制器晶粒105之前側106。控制器晶粒105包括在前側106附近之主動組件(例如,各種控制電路系統,諸如介面電路、通道控制電路等)。控制器晶粒105亦可包括具有嵌入於介電層中之導電跡線(諸如多層金屬層及通孔(其亦可稱為互連件))之層108,使得控制器晶粒105之主動組件可與記憶體晶粒堆疊125及控制器晶粒105之導電組件115耦接。在一些實施例中,導電組件115可包括連接襯墊,該等連接襯墊包括銅(Cu)、經組態以用於導電柱及/或凸塊下金屬化物的薄膜金屬層堆疊,等。
如圖1A中所描繪,控制器晶粒105之邊緣延伸超出記憶體晶粒堆疊125之對應邊緣,使得控制器晶粒105之前側106之部分110未由記憶體晶粒堆疊125覆蓋。由此,部分110可稱為曝露部分110及/或未覆蓋部分110。就此而言,可認為控制器晶粒105具有增大之晶粒大小以包括供安置導電組件115之曝露部分110。曝露部分110 (曝露部分110的包括導電組件115之至少某一部分)可置放於處理器晶粒(例如,處理單元、微處理器(例如,GPU、CPU))下方,使得導電組件115與處理器晶粒之對應導電組件之間直接電連接(例如,直接晶片至晶片連接),而其間不存在內插件。此外,控制器晶粒105可包括穿基板通孔(TSV) 120。TSV 120經組態以在控制器晶粒105之前側106與背側107之間轉發電信號。舉例而言,TSV 120可耦接至控制器晶粒105的主動組件。
在一些實施例中,圖101a之半導體記憶體堆疊可藉由將記憶體晶粒堆疊附接至記憶體控制器晶粒之前側,使得前側之一部分曝露(即,未由記憶體晶粒堆疊覆蓋)而形成。記憶體控制器之曝露部分可包括複數個第一導電組件(例如,導電組件115)。就此而言,本發明技術包括增大記憶體控制器晶粒之大小,使得記憶體控制器晶粒可具有不受阻部分(例如,曝露部分、未覆蓋部分)以將導電組件置放於其中。置放於曝露部分中之導電組件(例如,導電組件115)可經識別以用於與處理器晶粒交換信號,如參考圖1C所描述。以此方式,記憶體控制器晶粒的曝露部分可定位於處理器晶粒的面向記憶體控制器晶粒的區之下方,使得記憶體控制器晶粒與處理器晶粒的前側可直接附接至彼此。
儘管在前述實例實施例中,已描述且說明包括四(4)個記憶體晶粒之半導體記憶體堆疊,但在其他實施例中,可提供半導體記憶體堆疊以具有不同數量之記憶體晶粒。舉例而言,半導體記憶體堆疊可包括比圖1A中所描繪的半導體記憶體堆疊更小(例如,一個、二個、三個)或更大(例如,六個、八個、十二個或甚至更大)數量的記憶體晶粒。
圖1B說明根據本發明技術之實施例的包括一或多個半導體記憶體堆疊及一基板的實例示意圖。圖1B包括安裝於基板130上的四(4)個半導體記憶體堆疊的3D圖100b以及大體上對應於3D圖100b的示意性截面圖101b。
圖101a描述附接至基板130的半導體記憶體堆疊中的一者。基板130可包括用於附接半導體記憶體堆疊的第一區段135以及用於直接附接處理器晶粒的第二區段145。此外,基板130可包括在第一區段135中之導電組件140之集合及在第二區段145中之導電組件150的另一集合。基板130亦包括用於在控制器晶粒105 (及/或處理器晶粒160,如圖3C中所描繪)與較高層級電路系統之間的外部通信的基板端子131。在一些實施例中,導電組件140之集合可與形成及/或附接至焊球陣列(例如,球狀柵格陣列(BGA))相容。此外,導電組件150之集合可與形成及/或附接至導電柱或焊球相容。
如圖1B中所描繪,控制器晶粒105的背側107可經由焊球155的陣列附接至基板130。就此而言,控制器晶粒105之TSV 120中之每一者可經由陣列中的焊球155連接至基板130之第一區段135中的對應導電組件140。因此,控制器晶粒105及基板130可經由TSV 120中之至少一者傳輸及/或接收信號,該等TSV中之該至少一者連接至導電組件140中之對應一者而不包括包括導電跡線之內插層。
如圖101b中所描繪,附接至基板的半導體記憶體堆疊可藉由將承載記憶體晶粒堆疊的記憶體控制器晶粒的背側附接至基板來形成,如本文中所描述。舉例而言,焊球(例如,焊球155)之陣列可形成於記憶體控制器晶粒之背側上,其中焊球中之每一者耦接至記憶體控制器晶粒之對應TSV (例如,TSV 120)。或者,焊球之陣列可形成於基板上,其中焊球中之每一者耦接至基板之對應導電組件(例如,導電組件140)。隨後,記憶體控制器晶粒可配置在基板上方,使得該等TSV中之每一者可與該等導電組件(例如,導電組件140)中之對應一者對準。此外,可將記憶體控制器晶粒引至基板(或可將基板引至記憶體控制器),使得TSV中之每一者經由陣列中之焊球連接至導電組件中之對應一者。
圖1C說明根據本發明技術之實施例的包括一或多個半導體記憶體堆疊、一處理單元及一基板之半導體晶粒總成的實例示意圖。圖1C包括包括四(4)個半導體記憶體堆疊及安裝於基板130上的處理器晶粒160的半導體晶粒總成的3D圖100c以及大體上對應於3D圖100c的示意性截面圖101c。
圖101c描述附接於基板130的第一區段135上的半導體記憶體堆疊及附接至控制器晶粒105及基板130的第二區段145的處理器晶粒160中的一者。處理器晶粒160包括第一側161以及與第一側161相對的第二側162。類似於控制器晶粒105,處理器晶粒160包括在第一側161附近的各種主動組件(例如,GPU的圖形及計算陣列以及周邊電路系統、快取記憶體及CPU的算術邏輯電路)。
此外,處理器晶粒160可包括安置於第一側161之第一區165中的導電組件170的第一群組及安置於第一側161之第二區175中的導電組件180的第二群組。導電組件170之第一群組及導電組件180之第二群組與處理器晶粒160之主動組件耦接。在一些實施例中,導電組件170及/或180中之每一者可由諸如氧化物、氮化物、氮氧化物等的介電材料包圍。在一些實施例中,導電組件170可包括連接襯墊,該等連接襯墊包括銅(Cu)、經組態以用於導電柱及/或凸塊下金屬化物的薄膜金屬層堆疊,等。此外,導電組件180可與形成及/或附接至導電柱或焊球相容。
如圖1C中所描繪,處理器晶粒160之前側161面向控制器晶粒105之前側106及基板130,例如,處理器晶粒160經翻轉以使其前側161向下面向控制器晶粒105及基板130。此外,處理器晶粒160可配置於控制器晶粒105上方,使得處理器晶粒160之第一區165面向且重疊控制器晶粒105之曝露部分110。另外,處理器晶粒160之第二區175面向基板130之第二區段145。以此方式,曝露部分110中之導電組件115中之每一者可與第一區165中之導電組件170中之對應一者對準且耦接。類似地,基板130之第二區段145中的導電組件150中之每一者可與處理器晶粒160之第二區175中的導電組件180中之對應一者對準且耦接。
在一些實施例中,導電組件115之每一者對準至且直接接合至第一區165中的導電組件170中之對應一者,且包圍導電組件115中之每一者的介電材料(例如,控制器晶粒105之層108之介電材料)直接接合至包圍導電組件170中之每一者的另一介電材料。就此而言,由於兩種或更多種相異材料(例如,介電材料及導電材料)分別直接接合在一起以形成互連件且包圍介電層,因此此類組態可稱為組合接合、混合接合、直接接合,等。在一些實施例中,導電組件115及170兩者皆包括銅作為共同主要成分,且導電組件115中之每一者與導電組件170中之對應一者直接接觸。在一些實施例中,導電組件115中之每一者或導電組件170中之每一者包括導電柱(未展示),使得導電組件115中之每一者可經由導電柱連接至導電組件170中之對應一者。
以此方式,處理器晶粒160及控制器晶粒105可經由導電組件115中之至少一者傳輸及/或接收信號,該等導電組件中之該至少一者與導電組件170中之對應一者耦接而不包括包括導電跡線之內插層。因此,本發明技術可提供用於連接半導體記憶體堆疊(即,由控制器晶粒105承載之記憶體晶粒堆疊125)與處理單元(例如,處理器晶粒、GPU、CPU)的最短可能路線。
此外,處理器晶粒160之導電組件180可耦接至基板130之對應的導電組件150。在一些實施例中,導電組件180中之每一者包括導電柱185,使得導電組件180可經由導電柱185連接至導電組件150中之對應一者。或者,導電組件150中之每一者可包括導電柱185,使得導電組件180可經由導電柱185連接至導電組件150中之對應一者。在一些實施例中,焊球之陣列(未展示)可安置於處理器晶粒160與基板130之間,使得導電組件180中之每一者可經由陣列中之焊球連接至導電組件150中之對應一者。在一些實施例中,安置於處理器晶粒160與基板130之間的導電柱及/或焊球可包括某些高度及/或分佈以防止處理器晶粒160傾斜及/或下垂,以例如為處理器晶粒160提供機械支撐。
以此方式,處理器晶粒160及基板130可經由導電組件180中之至少一者傳輸及/或接收信號,該等導電組件中之該至少一者與導電組件150中之對應一者耦接而不包括包括導電跡線之內插層。此外,如參考圖1B所描述,控制器晶粒105及基板130亦可經由TSV 120中之至少一者傳輸及/或接收信號,該等TSV中之該至少一者連接至導電組件140中之對應一者而不包括內插層。
在一些實施例中,處理器晶粒160的兩個末端區可如圖100c中所描繪直接附接至控制器晶粒。在此等實施例中,處理器晶粒的中心區可包括用於經由在處理器晶粒160與基板130之間建立的連接(例如,導電柱185及/或焊球)與較高層級電路系統(例如,主機裝置)通信(或以其他方式介接)的主動組件(例如,各種電路系統)之集合。由此,處理器晶粒之末端區可包括用於與半導體記憶體堆疊(例如,GPU之周邊電路系統)通信(或以其他方式介接)之主動組件的另一集合。
儘管在前述實例實施例中,已描述且說明與四(4)個半導體記憶體堆疊耦接之處理器晶粒,但在其他實施例中,可提供處理器晶粒以與不同數量之半導體記憶體堆疊耦接。舉例而言,處理器晶粒可與比圖1C中所描繪的處理器晶粒更小(例如,一個、二個、三個)或更大數量的半導體記憶體堆疊(例如,六個、八個或甚至更大)耦接。
如圖101c中所描繪的附接至半導體記憶體堆疊及基板之處理器晶粒可藉由將處理器晶粒160之前側161附接至記憶體控制器晶粒105之曝露部分及基板130之第二區段145而形成。舉例而言,處理器晶粒(例如,處理器晶粒160)可經翻轉以使其前側161面向記憶體控制器晶粒及基板130。此外,處理器晶粒可配置於記憶體控制器晶粒上方,使得處理器晶粒之第一區165可面向記憶體控制器晶粒之曝露部分110 (未覆蓋或不受阻部分)。由此,記憶體控制器晶粒之導電組件115中之每一者可與處理器晶粒之導電組件170中之對應一者對準。另外,處理器晶粒之第二區175可面向基板之第二區段145,使得導電組件180中之每一者可與基板之導電組件150中之對應一者對準。 將處理器晶粒附接至記憶體控制器晶粒
在一些實施例中,處理器晶粒160可接合至記憶體控制器晶粒105,以將記憶體控制器晶粒的導電組件115中之每一者直接接合至處理器晶粒的導電組件170中之對應一者。另外,包圍記憶體控制器晶粒105的導電組件115中之每一者的第一介電材料(例如,控制器晶粒105的層108的介電材料)可接合至包圍處理器晶粒的導電組件170中之每一者的第二介電材料。
在一些實施例中,可將處理器晶粒160引至記憶體控制器晶粒105,使得記憶體控制器晶粒的導電組件115中之每一者與處理器晶粒的導電組件170中之對應一者直接接觸。另外,導電組件115及導電組件170包括銅作為共同主要成分。
在一些實施例中,導電柱(未展示)可形成於記憶體控制器晶粒的導電組件115中之每一者或處理器晶粒的導電組件170中之每一者上。隨後,可將處理器晶粒引至記憶體控制器晶粒,使得記憶體控制器晶粒之導電組件115中之每一者經由導電柱連接至處理器晶粒之導電組件170中之對應一者。 將處理器晶粒附接至基板
在一些實施例中,導電柱(例如,導電柱185)可形成於處理器晶粒160的導電組件180中之每一者上(或替代地,基板的導電組件150中之每一者上)。隨後,處理器晶粒可配置於基板上方,使得導電組件180中之每一者與基板之導電組件150中之對應一者對準。此外,可將處理器晶粒引至基板,使得導電組件180中之每一者經由導電柱185連接至基板的導電組件150中之對應一者。
在一些實施例中,焊球(未展示)可形成於處理器晶粒160之導電組件180中之每一者上(或替代地,形成於基板之導電組件150中之每一者上)。隨後,處理器晶粒可配置於基板上方,使得導電組件180中之每一者與基板之導電組件150中之對應一者對準。此外,可將處理器晶粒引至基板(或反之亦然),使得導電組件180中之每一者經由焊球連接至基板的導電組件150中之對應一者。
圖2為示意性地說明包括根據本發明技術之實施例組態的半導體晶粒總成之系統200之方塊圖。系統200可包括半導體裝置總成270、電源272、驅動器274、處理器276及/或其他子系統或組件278。半導體裝置總成270可併入至多種較大及/或較複雜系統中之任一者中,其代表性實例為圖2中示意性展示之系統200。參考圖1C所描述之半導體晶粒總成可包括於系統200之半導體裝置總成270中。
半導體裝置總成270可具有大體上類似於半導體晶粒總成之特徵。舉例而言,半導體裝置總成270可包括各自具有承載一或多個記憶體晶粒(例如,記憶體晶粒堆疊)之控制器晶粒的一或多個半導體記憶體堆疊。此外,半導體裝置總成270可包括處理器晶粒,其附接至控制器晶粒以提供用於連接半導體記憶體堆疊與處理器晶粒的最短可能路線。另外,半導體裝置總成270可包括承載半導體記憶體堆疊及處理器晶粒兩者而無內插件之基板。所得系統270可執行廣泛多種功能中之任一者,諸如記憶體儲存、資料處理及/或其他合適功能。因此,代表性系統270可包括但不限於手持型裝置(例如,行動電話、平板電腦、數位閱讀器及數位音訊播放器)、電腦及器具。系統270之組件可容納於單一單元中或遍及多個互連單元(例如,經由通信網路)而分佈。系統270之組件亦可包括遠端裝置及廣泛多種電腦可讀媒體中之任一者。
圖3為根據本發明技術之實施例之製造半導體晶粒總成的方法之流程圖300。流程圖300可包括如參考圖1A至圖1C所描述之方法的態樣。
該方法包括將記憶體晶粒堆疊附接在記憶體控制器晶粒之前側上,使得該前側之一部分曝露,該曝露部分包括複數個第一導電組件(框310)。該方法進一步包括將承載記憶體晶粒堆疊之記憶體控制器晶粒附接至在基板之第一區段中的第三導電組件之第一集合,該基板亦包括在基板之第二區段中的第三導電組件之一第二集合(框315)。該方法進一步包括將處理器晶粒附接至記憶體控制器晶粒及基板,該處理器晶粒包括在處理器晶粒之前側的第一區中的第二導電組件之第一群組及在處理器晶粒之前側的第二區中的第二導電組件之第二群組,使得1)該第一區面向記憶體控制器晶粒之曝露部分,且第一導電組件中之每一者與第一群組中的第二導電組件中之對應一者耦接,且2)該第二區面向基板之第二區段,且第二群組中的第二導電組件中之每一者與第二集合中的第三導電組件中之對應一者耦接(框320)。
在一些實施例中,將處理器晶粒附接至記憶體控制器晶粒包括:將處理器晶粒配置在記憶體控制器晶粒上方,使得第一導電組件中之每一者與第一群組中的第二導電組件中之對應一者對準;以及將處理器晶粒接合至記憶體控制器晶粒,以將第一導電組件中之每一者直接接合至第一群組中的第二導電組件中之對應一者,其中包圍第一導電組件中之每一者的第一介電材料同時接合至包圍第一群組中的第二導電組件中之每一者的第二介電材料。
在一些實施例中,將處理器晶粒附接至記憶體控制器晶粒包括:將處理器晶粒配置在記憶體控制器晶粒上方,使得第一導電組件中之每一者與第一群組中的第二導電組件中之對應一者對準;以及將處理器晶粒引至記憶體控制器晶粒,使得第一導電組件中之每一者與第一群組中的第二導電組件中之對應一者直接接觸,其中第一導電組件及第一群組中的第二導電組件包含銅作為共同主要成分。
在一些實施例中,將處理器晶粒附接至記憶體控制器晶粒包括:在第一導電組件中之每一者或第一群組中的第二導電組件中之每一者上形成導電柱;以及將處理器晶粒配置在記憶體控制器晶粒上方,使得第一導電組件中之每一者與第一群組中的第二導電組件中之對應一者對準;以及將處理器晶粒引至記憶體控制器晶粒,使得第一導電組件中之每一者經由導電柱連接至第一群組中的第二導電組件中之對應一者。
在一些實施例中,將處理器晶粒附接至基板包括:在第二群組中的第二導電組件中之每一者上形成焊球;將處理器晶粒配置在基板上方,使得第二群組中的第二導電組件中之每一者與第二集合中的第三導電組件中之對應一者對準;以及將處理器晶粒引至基板,使得第二群組中的第二導電組件中之每一者經由焊球連接至第二集合中的第三導電組件中之對應一者。
在一些實施例中,將處理器晶粒附接至基板包括:在第二群組中的第二導電組件中之每一者上形成導電柱;將處理器晶粒配置在基板上方,使得第二群組中的第二導電組件中之每一者與第二集合中的第三導電組件中之對應一者對準;以及將處理器晶粒引至基板,使得第二群組中的第二導電組件中之每一者經由導電柱連接至第二集合中的第三導電組件中之對應一者。
在一些實施例中,該記憶體控制器晶粒包含經組態以在記憶體控制器晶粒之前側與記憶體控制器晶粒之背側之間轉發電信號的複數個穿矽通孔(TSV),且將記憶體控制器晶粒附接至基板包括:形成各自與對應TSV耦接的焊球之陣列;將記憶體控制器晶粒配置在基板上方,使得TSV中之每一者與第一集合中的第三導電組件中之對應一者對準;以及將記憶體控制器晶粒引至基板,使得TSV中之每一者經由陣列中之焊球連接至第一集合中的第三導電組件中之對應一者。
應注意,上文所描述之方法描述可能的實施方案,且操作及步驟可經重新配置或以其他方式修改,且其他實施方案係可能的。此外,可組合該等方法中之兩者或多於兩者之實施例。自前文,應瞭解,儘管出於說明之目的已在本文描述技術之特定實施例,但可在不偏離本發明之情況下進行各種修改。另外,儘管在所說明之實施例中,已將某些特徵或組件展示為具有某些配置或組態,但其他配置及組態係可能的。此外,在其他實施例中,亦可組合或消除在特定實施例之上下文中描述的本發明技術之某些態樣。
可在諸如矽、鍺、矽-鍺合金、砷化鎵、氮化鎵等之半導體基板或晶粒上形成本文中所論述的裝置,包括半導體裝置。在一些情況下,基板為半導體晶圓。在其他情況下,基板可為絕緣層上矽(SOI)基板,諸如玻璃上矽(SOG)或藍寶石上矽(SOP),或另一基板上之半導體材料的磊晶層。可通過使用包括但不限於磷、硼或砷之各種化學物種摻雜而控制基板或基板之子區的導電性。可藉由離子植入或藉由任何其他摻雜方式在基板之初始形成或生長期間執行摻雜。
如本文中所使用(包括在申請專利範圍中),「或」在用於項目清單(例如,以諸如「中之至少一者」或「中之一或多者」之片語作為結尾之項目清單)中時指示包括性清單,使得例如A、B或C中之至少一者之清單意謂A或B或C或AB或AC或BC或ABC (即,A及B及C)。此外,如本文所用,片語「基於」不應被認作對封閉條件集合之參考。舉例而言,在不脫離本發明之範疇的情況下,被描述為「基於條件A」之例示性步驟可基於條件A及條件B兩者。換言之,如本文中所使用,應以與片語「至少部分地基於」相同之方式來解釋片語「基於」。
自前文,應瞭解,儘管已出於說明的目的在本文描述的本發明之特定實施例,但可在不偏離本發明的範疇的情況下進行各種修改。確切而言,在前文描述中,論述眾多具體細節以提供對本發明技術之實施例的透徹及啟發性的描述。然而,熟習相關技術者將認識到,本發明可在無此等具體細節中之一或多者之情況下實踐。在其他情況下,未展示或未詳細描述通常與記憶體系統及裝置相關的熟知結構或操作,以免混淆技術之其他態樣。一般而言,應理解,除了本文中所揭示之彼等具體實施例之外,各種其他裝置、系統及方法亦可在本發明技術之範疇內。
100a:三維(3D)圖 100b:3D圖 100c:3D圖 101a:示意性截面圖 101b:示意性截面圖 101c:示意性截面圖 105:控制器晶粒 106:前側 107:背側 108:層 110:曝露部分/未覆蓋部分 115:導電組件 120:穿基板通孔 125:記憶體晶粒堆疊 130:基板 131:基板端子 135:第一區段 140:導電組件 145:第二區段 150:導電組件 155:焊球 160:處理器晶粒 161:第一側 162:第二側 165:第一區 170:導電組件 175:第二區 180:導電組件 185:導電柱 200:系統 270:半導體裝置總成 272:電源 274:驅動器 276:處理器 278:其他子系統或組件 300:流程圖 310:框 315:框 320:框
參考以下圖式可更佳地理解本發明技術之許多態樣。圖式中之組件未必按比例。替代地,著重強調清楚地說明本發明技術之總體特徵及原理。
圖1A說明根據本發明技術之實施例的半導體記憶體堆疊之實例示意圖。
圖1B說明根據本發明技術之實施例的包括一或多個半導體記憶體堆疊及一基板的實例示意圖。
圖1C說明根據本發明技術之實施例的包括一或多個半導體記憶體堆疊、一處理單元及一基板之半導體晶粒總成的實例示意圖。
圖2為示意性地說明包括根據本發明技術之實施例組態的半導體晶粒總成之系統之方塊圖。
圖3為根據本發明技術之實施例之製造半導體晶粒總成的方法之流程圖。
100c:3D圖
101c:示意性截面圖
105:控制器晶粒
110:曝露部分/未覆蓋部分
115:導電組件
120:穿基板通孔
125:記憶體晶粒堆疊
130:基板
131:基板端子
135:第一區段
140:導電組件
145:第二區段
150:導電組件
155:焊球
160:處理器晶粒
161:第一側
162:第二側
165:第一區
170:導電組件
175:第二區
180:導電組件
185:導電柱

Claims (20)

  1. 一種半導體晶粒總成,其包含: 一記憶體控制器晶粒,其在其一前側上承載一記憶體晶粒堆疊,其中該記憶體控制器晶粒之一邊緣延伸超出該記憶體晶粒堆疊之一對應邊緣,使得該記憶體控制器晶粒的該前側之一部分未由該記憶體晶粒堆疊覆蓋,該部分包括複數個第一導電組件; 一處理器晶粒,其包括在該處理器晶粒之一前側的一第一區中的第二導電組件之一第一群組及在該處理器晶粒之該前側的一第二區中的第二導電組件之一第二群組,其中該處理器晶粒配置於該記憶體控制器晶粒上方,使得該處理器晶粒之該第一區面向該記憶體控制器晶粒之該部分,且該等第一導電組件中之每一者與該第一群組中的該等第二導電組件中之對應一者耦接;以及 一基板,其承載該記憶體控制器晶粒及該處理器晶粒兩者,該基板包括在該基板之一第二區段中的第三導電組件之一第二集合,其中該處理器晶粒配置於該基板上方,使得該處理器晶粒之該第二區面向該第二區段,且該第二群組中的該等第二導電組件中之每一者與該第二集合中的該等第三導電組件中之對應一者耦接。
  2. 如請求項1之半導體晶粒總成,其中該等第一導電組件中之每一者對準至且直接接合至該第一群組中的該等第二導電組件中之該對應一者,且包圍該等第一導電組件中之每一者的一第一介電材料直接接合至包圍該第一群組中的該等第二導電組件中之每一者的一第二介電材料。
  3. 如請求項1之半導體晶粒總成,其中該等第一導電組件及該第一群組中的該等第二導電組件兩者皆包含銅作為一共同主要成分,且該等第一導電組件中之每一者與該第一群組中的該等第二導電組件中之該對應一者直接接觸。
  4. 如請求項1之半導體晶粒總成,其中該等第一導電組件中之每一者或該第一群組中的該等第二導電組件中之每一者包含一導電柱,且該等第一導電組件中之每一者經由該導電柱連接至該第一群組中的該等第二導電組件中之該對應一者。
  5. 如請求項1之半導體晶粒總成,其中該處理器晶粒及該記憶體控制器晶粒經由該等第一導電組件中之至少一者傳輸及/或接收信號,該等第一導電組件中之該至少一者與該等第二導電組件中之該對應一者耦接而不包括包含導電跡線之一內插層。
  6. 如請求項1之半導體晶粒總成,其中該第二群組中的該等第二導電組件中之每一者經由一焊球連接至該第二集合中的該等第三導電組件中之該對應一者。
  7. 如請求項1之半導體晶粒總成,其中該第二群組中的該等第二導電組件中之每一者包含一導電柱,且該第二群組中的該等第二導電組件中之每一者經由該導電柱連接至該第二集合中的該等第三導電組件中之該對應一者。
  8. 如請求項1之半導體晶粒總成,其中該處理器晶粒及該基板經由該等第二導電組件中之至少一者傳輸及/或接收信號,該等第二導電組件中之該至少一者與該等第三導電組件中之該對應一者耦接而不包括包含導電跡線之一內插層。
  9. 如請求項1之半導體晶粒總成,其中: 該記憶體控制器晶粒包含經組態以在該記憶體控制器晶粒之該前側與該記憶體控制器晶粒之一背側之間轉發電信號的複數個穿矽通孔(TSV); 該記憶體控制器晶粒之該背側經由焊球之一陣列附接至該基板;且 該等TSV中之每一者經由該陣列中之一焊球連接至在該基板之一第一區段中的第三導電組件之一第一集合中的一對應第三導電組件。
  10. 如請求項9之半導體晶粒總成,其中該記憶體控制器晶粒及該基板經由該等TSV中之至少一者傳輸及/或接收信號,該等TSV中之該至少一者與該等第三導電組件中之該對應一者耦接而不包括包含導電跡線之一內插層。
  11. 一種方法,其包含: 將一記憶體晶粒堆疊附接在一記憶體控制器晶粒之一前側上,使得該前側之一部分曝露,該曝露部分包括複數個第一導電組件; 將承載該記憶體晶粒堆疊之該記憶體控制器晶粒附接至在一基板之一第一區段中的第三導電組件之一第一集合,該基板亦包括在該基板之一第二區段中的第三導電組件之一第二集合;以及 將一處理器晶粒附接至該記憶體控制器晶粒及該基板,該處理器晶粒包括在該處理器晶粒之一前側的一第一區中的第二導電組件之一第一群組及在該處理器晶粒之該前側的一第二區中的第二導電組件之一第二群組,使得1)該第一區面向該記憶體控制器晶粒之該曝露部分,且該等第一導電組件中之每一者與該第一群組中的該等第二導電組件中之對應一者耦接,且2)該第二區面向該基板之該第二區段,且該第二群組中的該等第二導電組件中之每一者與該第二集合中的該等第三導電組件中之對應一者耦接。
  12. 如請求項11之方法,其中將該處理器晶粒附接至該記憶體控制器晶粒包括: 將該處理器晶粒配置在該記憶體控制器晶粒上方,使得該等第一導電組件中之每一者與該第一群組中的該等第二導電組件中之該對應一者對準;以及 將該處理器晶粒接合至該記憶體控制器晶粒,以將該等第一導電組件中之每一者直接接合至該第一群組中的該等第二導電組件中之該對應一者,其中包圍該等第一導電組件中之每一者的一第一介電材料同時接合至包圍該第一群組中的該等第二導電組件中之每一者的一第二介電材料。
  13. 如請求項11之方法,其中將該處理器晶粒附接至該記憶體控制器晶粒包括: 將該處理器晶粒配置在該記憶體控制器晶粒上方,使得該等第一導電組件中之每一者與該第一群組中的該等第二導電組件中之該對應一者對準;以及 將該處理器晶粒引至該記憶體控制器晶粒,使得該等第一導電組件中之每一者與該第一群組中的該等第二導電組件中之該對應一者直接接觸,其中該等第一導電組件及該第一群組中的該等第二導電組件包含銅作為一共同主要成分。
  14. 如請求項11之方法,其中將該處理器晶粒附接至該記憶體控制器晶粒包括: 在該等第一導電組件中之每一者或該第一群組中的該等第二導電組件中之每一者上形成一導電柱; 將該處理器晶粒配置在該記憶體控制器晶粒上方,使得該等第一導電組件中之每一者與該第一群組中的該等第二導電組件中之該對應一者對準;以及 將該處理器晶粒引至該記憶體控制器晶粒,使得該等第一導電組件中之每一者經由該導電柱連接至該第一群組中的該等第二導電組件中之該對應一者。
  15. 如請求項11之方法,其中將該處理器晶粒附接至該基板包括: 在該第二群組中的該等第二導電組件中之每一者上形成一焊球; 將該處理器晶粒配置在該基板上方,使得該第二群組中的該等第二導電組件中之每一者與該第二集合中的該等第三導電組件中之該對應一者對準;以及 將該處理器晶粒引至該基板,使得該第二群組中的該等第二導電組件中之每一者經由該焊球連接至該第二集合中的該等第三導電組件中之該對應一者。
  16. 如請求項11之方法,其中將該處理器晶粒附接至該基板包括: 在該第二群組中的該等第二導電組件中之每一者上形成一導電柱; 將該處理器晶粒配置在該基板上方,使得該第二群組中的該等第二導電組件中之每一者與該第二集合中的該等第三導電組件中之該對應一者對準;以及 將該處理器晶粒引至該基板,使得該第二群組中的該等第二導電組件中之每一者經由該導電柱連接至該第二集合中的該等第三導電組件中之該對應一者。
  17. 如請求項11之方法,其中該記憶體控制器晶粒包含經組態以在該記憶體控制器晶粒之該前側與該記憶體控制器晶粒之一背側之間轉發電信號的複數個穿矽通孔(TSV),且其中將該記憶體控制器晶粒附接至該基板包括: 形成各自與對應TSV耦接的焊球之一陣列; 將該記憶體控制器晶粒配置在該基板上方,使得該等TSV中之每一者與該第一集合中的該等第三導電組件中之該對應一者對準;以及 將該記憶體控制器晶粒引至該基板,使得該等TSV中之每一者經由該陣列中之一焊球連接至該第一集合中的該等第三導電組件中之該對應一者。
  18. 一種半導體晶粒總成,其包含: 一第一記憶體控制器,其在其一前側上承載一第一記憶體晶粒堆疊,其中該第一記憶體控制器之一邊緣延伸超出該第一記憶體晶粒堆疊之一對應邊緣,使得該第一記憶體控制器的該前側之一部分曝露,該曝露部分包括第一複數個導電組件; 一第二記憶體控制器,其在其一前側上承載一第二記憶體晶粒堆疊,其中該第二記憶體控制器之一邊緣延伸超出該第二記憶體晶粒堆疊之一對應邊緣,使得該第二記憶體控制器的該前側之一部分曝露,該曝露部分包括第二複數個導電組件; 一處理器,其包括在其一前側上的導電組件之第一群組、第二群組及第三群組,其中該處理器配置於該第一記憶體控制器及該第二記憶體控制器兩者上方,使得該第一複數個導電組件中之每一者與該第一群組中的該等導電組件中之對應一者耦接,且該第二複數個導電組件中之每一者與該第三群組中的該等導電組件中之對應一者耦接;以及 一基板,其承載該第一記憶體控制器及該第二記憶體控制器以及該處理器,該基板包括導電組件之一第二集合,其中該處理器配置於該基板上方,使得該第二群組中的該等導電組件中之每一者與該第二集合中的該等導電組件中之對應一者耦接。
  19. 如請求項18之半導體晶粒總成,其中: 該第一記憶體控制器包含經組態以在該第一記憶體控制器之該前側與一背側之間轉發電信號的第一複數個穿矽通孔(TSV); 該第一記憶體控制器之該背側經由焊球之一第一陣列附接至該基板,其中該第一複數個TSV中之每一者經由該第一陣列中之一焊球連接至該基板之導電組件的一第一集合中的一對應導電組件; 該第二記憶體控制器包含經組態以在該第二記憶體控制器的該前側與一背側之間轉發電信號的第二複數個TSV;且 該第二記憶體控制器之該背側經由焊球之一第二陣列附接至該基板,其中該第二複數個TSV中之每一者經由該第二陣列中之一焊球連接至該基板之導電組件的一第三集合中的一對應導電組件。
  20. 如請求項18之半導體晶粒總成,其中: 該處理器及該第一記憶體控制器經由該第一複數個導電組件中之至少一者傳輸及/或接收信號,該第一複數個導電組件中之該至少一者與該第一群組中的該等導電組件中之該對應一者耦接而不包括包含導電跡線之一內插層;且 該處理器及該第二記憶體控制器經由該第二複數個導電組件中之至少一者傳輸及/或接收信號,該第二複數個導電組件中之該至少一者與該第三群組中的該等導電組件中之該對應一者耦接而不包括該內插層。
TW110124911A 2020-07-24 2021-07-07 連接至處理單元之半導體記憶體堆疊以及相關系統及方法 TWI785666B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/938,844 US11239169B1 (en) 2020-07-24 2020-07-24 Semiconductor memory stacks connected to processing units and associated systems and methods
US16/938,844 2020-07-24

Publications (2)

Publication Number Publication Date
TW202220160A true TW202220160A (zh) 2022-05-16
TWI785666B TWI785666B (zh) 2022-12-01

Family

ID=77358363

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110124911A TWI785666B (zh) 2020-07-24 2021-07-07 連接至處理單元之半導體記憶體堆疊以及相關系統及方法

Country Status (4)

Country Link
US (3) US11239169B1 (zh)
CN (1) CN116134516A (zh)
TW (1) TWI785666B (zh)
WO (1) WO2022020118A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240021571A1 (en) * 2022-07-18 2024-01-18 Applied Materials, Inc. Hybrid bonding of semiconductor structures to advanced substrate panels

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5070342B2 (ja) * 2007-10-23 2012-11-14 ヒューレット−パッカード デベロップメント カンパニー エル.ピー. コンピュータシステム装置における全光高速分散アービトレーション
US9679615B2 (en) * 2013-03-15 2017-06-13 Micron Technology, Inc. Flexible memory system with a controller and a stack of memory
US9263157B2 (en) 2013-12-23 2016-02-16 International Business Machines Corporation Detecting defective connections in stacked memory devices
US9666559B2 (en) 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
US10425260B2 (en) * 2017-08-07 2019-09-24 Micron Technology, Inc. Multi-level signaling in memory with wide system interface
JP7033332B2 (ja) 2017-11-21 2022-03-10 ウルトラメモリ株式会社 半導体モジュール
US10522489B1 (en) * 2018-06-28 2019-12-31 Western Digital Technologies, Inc. Manufacturing process for separating logic and memory array
KR102615197B1 (ko) 2018-11-23 2023-12-18 삼성전자주식회사 반도체 패키지
US20200168527A1 (en) * 2018-11-28 2020-05-28 Taiwan Semiconductor Manfacturing Co., Ltd. Soic chip architecture
KR20200066774A (ko) * 2018-12-03 2020-06-11 삼성전자주식회사 반도체 장치

Also Published As

Publication number Publication date
WO2022020118A1 (en) 2022-01-27
US20230395516A1 (en) 2023-12-07
US20220157728A1 (en) 2022-05-19
US11735528B2 (en) 2023-08-22
US11239169B1 (en) 2022-02-01
CN116134516A (zh) 2023-05-16
TWI785666B (zh) 2022-12-01
US20220028789A1 (en) 2022-01-27

Similar Documents

Publication Publication Date Title
US9972605B2 (en) Method for fabricating fan-out wafer level package and fan-out wafer level package fabricated thereby
US11239207B1 (en) Semiconductor die stacks and associated systems and methods
US10181457B2 (en) Microelectronic package for wafer-level chip scale packaging with fan-out
US20170263536A1 (en) Chip package having tilted through silicon via
US20220285315A1 (en) Stacked semiconductor dies for semiconductor device assemblies
US11152333B2 (en) Semiconductor device packages with enhanced heat management and related systems
TWI778489B (zh) 製作雙側半導體裝置之方法及相關裝置、總成、封裝及系統
US20230395516A1 (en) Semiconductor memory stacks connected to processing units and associated systems and methods
US11942455B2 (en) Stacked semiconductor dies for semiconductor device assemblies
US20240186295A1 (en) Microelectronic device assemblies, stacked semiconductor die assemblies, and memory device packages
KR20230096013A (ko) 반도체 소자의 제조 방법 및 반도체 소자
US20230282627A1 (en) Semiconductor memory dies bonded to logic dies and associated systems and methods
US20230284465A1 (en) Semiconductor die stacks and associated systems and methods
US20240071891A1 (en) Semiconductor device assemblies having face-to-face subassemblies, and methods for making the same
US20240113076A1 (en) Intra-bonding semiconductor integrated circuit chips
US20240047396A1 (en) Bonded semiconductor device
CN116387275A (zh) 作为用于封装结构的小芯片的带tsv的混合接合堆叠存储器
CN117637729A (zh) 具有共面互连结构的半导体装置组合件及其制造方法
CN116504747A (zh) 信号路由结构及包含其的半导体装置组合件