TW202219599A - Retractable substrate - Google Patents

Abstract

A retractable substrate includes a patterned substrate, a plurality of device parts, and a plurality of circuit parts. The device parts are located on the patterned substrate. Each device parts includes an active area and a peripheral area surrounding the active area. Each device parts includes a first active element and a second active element arranged in the active area. The circuit parts are located on the patterned substrate and is connected to corresponding device parts.

Description

retractable base plate

The present invention relates to a retractable substrate, and more particularly, to a retractable substrate suitable for a display device.

With the high development of electronic technology, electronic products are constantly innovating. In order to enable electronic products to be applied in various fields, the characteristics of stretchability, thinness and unrestricted appearance have gradually been paid more and more attention. That is to say, electronic products are gradually required to have different shapes according to different application methods and application environments, so electronic products need to be stretchable.

However, when the electronic product is stretched, it may cause structural fracture due to stress, and even further cause the internal circuit to be disconnected. Therefore, how to make stretchable electronic products have good manufacturing yield and product reliability is an urgent problem to be solved at present.

The invention provides a retractable base plate, which can improve the problem that the active element is damaged after the retractable base plate is stretched.

At least one embodiment of the present invention provides a retractable substrate. The retractable substrate includes a patterned substrate, a plurality of device parts, and a plurality of circuit parts. The device portion is located on the patterned substrate. Each device portion includes an active area and a peripheral area surrounding the active area. Each device portion includes a first active element and a second active element disposed in the active region. The circuit part is located on the patterned substrate and is connected to the corresponding device part.

FIG. 1A is a schematic top view of a retractable substrate 10 according to an embodiment of the present invention.

Referring to FIG. 1A , the retractable substrate 10 includes a patterned substrate 100 , a plurality of device parts 200 and a plurality of circuit parts 300 . In this embodiment, the retractable base plate 10 further includes a connecting portion 400 .

The patterned substrate 100 is a soft material. For example, the material of the patterned substrate 100 may include polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate Ester (polyethylene terephthalate; PET), polycarbonate (polycarbonates; PC), polyether sulfone (PES) or polyarylate (polyarylate), other suitable materials or a combination of at least two of the foregoing materials, but The present invention is not limited to this.

In this embodiment, the patterned substrate 100 has a plurality of through holes TH. In this embodiment, each through hole TH is in the shape of a dumbbell. In this embodiment, some of the through holes TH extend along the first direction E1, and another part of the through holes TH extend along the second direction E2. Part of the through holes TH extending along the first direction E1 and another part of the through holes TH extending along the second direction E2 are alternately arranged, thereby improving the stretchability of the retractable substrate 10 .

The device part 200 , the circuit part 300 and the connection part 400 are located on the patterned substrate 100 . The device part 200 , the circuit part 300 and the connection part 400 are connected together, and at least one of the through holes TH is substantially surrounded by the four device parts 200 . In this embodiment, one through hole TH is substantially surrounded by four device parts 200 , two circuit parts 300 and two connecting parts 400 . For example, in FIG. 1A , the central through hole TH is surrounded by two left and right circuit parts 300 , two upper and lower connecting parts 400 , and four corner device parts 200 .

Each device portion 200 includes an active area AR and a peripheral area PR surrounding the active area AR. Each device portion 200 includes a first active element T1 and a second active element T2 disposed in the active area AR. In this embodiment, each device part 200 further includes a third active element T3. In some embodiments, each device portion 200 is a rectangle with a length L and a width W, and in the direction of the width W of each device portion 200 , the width W1 of the peripheral region PR is 16%W to 40%W, and The width W2 of the peripheral region PR in the direction of the length L of each device portion 200 is 16%L to 40%L. The width W1 and the width W2 of the peripheral region PR are 10 to 250 micrometers.

In this embodiment, each device part 200 includes a first sub-pixel SP1, a second sub-pixel SP2 and a third sub-pixel SP3, wherein the second sub-pixel SP2 is located in the first sub-pixel SP1 and the third sub-pixel Between pixels SP3. The first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 respectively include a first active element T1, a second active element T2 and a third active element T3, and the first sub-pixel SP1, the second active element The sub-pixel SP2 and the third sub-pixel SP3 respectively include a first light-emitting diode (not shown in FIG. 1A ), a second light-emitting diode (not shown in FIG. 1A ), and a third light-emitting diode (not shown in FIG. 1A ) not shown). The first active element T1 , the second active element T2 and the third active element T3 are respectively suitable for driving the aforementioned first light emitting diode, second light emitting diode and third light emitting diode.

In this embodiment, the retractable substrate 10 is suitable for a display device, but the present invention is not limited thereto. In other embodiments, the retractable substrate 10 is not a display device, and the device portion 200 does not include sub-pixels.

The line unit 300 is connected to the corresponding device unit 200 . In this embodiment, each line part 300 is connected to two corresponding device parts 200 . Each line portion 300 includes at least one signal line 310 . The signal line 310 is electrically connected to the corresponding first sub-pixel SP1, the corresponding second sub-pixel SP2 and/or the corresponding third sub-pixel SP3. Although only the signal line 310 is shown to extend to the edge of the device portion 200 in FIG. 1A , in fact, the device portion 200 also includes many other wires (not shown in FIG. 1A ), so that the signal line 310 is connected to the corresponding first sub-connector. The pixel SP1, the corresponding second sub-pixel SP2 and/or the corresponding third sub-pixel SP3 are electrically connected.

The connection part 400 is adjacent to the corresponding line part 300 . In the present embodiment, each connection part 400 is connected to the corresponding two device parts 200 and is located on one side of the corresponding one of the circuit parts 300 . Each connecting portion 400 includes a plurality of reinforcing structures 410 arranged in sequence. The reinforcement structure 410 is separated from the signal line 310 . In some embodiments, the reinforcing structure 410 can adjust the neutral axis positions of the connecting portion 400 and the wiring portion 300 , and reduce the risk of the signal line 310 being disconnected due to stretching. In addition, since the reinforcing structure 410 is separated from the signal line 310 , even if a crack occurs in the reinforcing structure 410 , the crack is not easily extended to the signal line 310 , causing the signal line 310 to be disconnected. In some embodiments, the reinforcement structure 410 is a spare wire. In some embodiments, the reinforcement structure 410 is an insulating pattern.

FIG. 1B is a schematic top view of the retractable substrate 10 of FIG. 1A after stretching. FIG. 2 is a schematic diagram of the strain amount simulation of the retractable base plate of FIG. 1B , wherein in FIG. 2 , the numerical value on the left represents the strain amount.

Referring to FIG. 1B and FIG. 2 , the retractable substrate 10 is stretched and deformed. In this embodiment, the retractable base plate 10 is subjected to pulling forces F in different directions, and the pulling force F changes the shape of the retractable base plate 10 . It can be seen from the simulation diagram in FIG. 2 that in the device part 200, the peripheral region PR near the periphery is prone to have a larger strain than the active region AR in the center. Therefore, the first active element T1, the second active element T2 and the The third active element T3 is disposed in the active area AR instead of the peripheral area PR, so as to avoid the failure of the first active element T1 , the second active element T2 and the third active element T3 after the retractable substrate 10 is stretched question.

In some embodiments, the first active element T1 , the second active element T2 and the third active element T3 are directly electrically connected to the driving elements of the light emitting diodes, namely the first active element T1 , the second active element T2 and There is no other thin-film transistor between the third active element T3 and the corresponding light-emitting diode. Therefore, the quality of the first active element T1, the second active element T2 and the third active element T3 has a greater impact on the display screen than the first sub-picture. Other thin film transistors (eg, switching elements) in the pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are large. Therefore, disposing the first active element T1 , the second active element T2 and the third active element T3 in the active region AR is better than disposing other thin film transistors that are not directly electrically connected to the light emitting diodes in the active region AR The improvement of the retractable substrate 10 has the problem of screen Mura after stretching.

FIG. 3A is a schematic top view of a retractable base plate 20 according to an embodiment of the present invention. In order to explain the retractable base plate 20 of FIG. 3A more clearly, some components of the retractable base plate 20 are omitted and shown in In FIGS. 3B and 3C , in FIGS. 3A to 3D , the conductive layers of the same layer (that is, the conductive layers formed by the same patterning process) are shown with the same oblique lines or dots, and the conductive layers of different layers It is electrically connected through the via V passing through the insulating layer (eg, the insulating layer GI and/or the insulating layer ILD). Fig. 3D is a schematic cross-sectional view taken along line A-A' of Fig. 3A. 3E is an equivalent circuit diagram of a sub-pixel according to an embodiment of the present invention. In this embodiment, the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 have similar The equivalent circuit of the first sub-pixel SP1 is taken as an example in FIG. 3E .

It must be noted here that the embodiments of FIGS. 3A to 3E use the element numbers and part of the content of the embodiment of FIGS. 1A and 1B , wherein the same or similar numbers are used to represent the same or similar elements, and the same elements are omitted. Description of technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

Referring to FIGS. 3A to 3E , the device portion 200 and the circuit portion 300 are located on the patterned substrate 100 . In some embodiments, a buffer layer BL is disposed on the surface of the patterned substrate 100 , and the device portion 200 and the circuit portion 300 are located on the buffer layer BL.

Each line part 300 includes a plurality of signal lines SGL. The signal line SGL is the scan line SL, the first data line DL1, the second data line DL2, the third data line DL3, the first power line PL1 and/or the second power line PL2.

Each device unit 200 includes a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3.

The first sub-pixel SP1 includes a first switching element SE1, a first active element T1 and a first light emitting diode L1. The first switching element SE1 includes a semiconductor layer CHa, a gate electrode Ga, a source electrode Sa and a drain electrode Da. The gate electrode Ga is electrically connected to the scan line SL. The gate electrode Ga overlaps with the channel layer CHa, and the insulating layer GI is sandwiched between the gate electrode Ga and the channel layer CHa. The insulating layer ILD covers the gate electrode Ga. The source electrode Sa and the drain electrode Da are located on the insulating layer ILD and are electrically connected to the channel layer CHa. The source electrode Sa is electrically connected to the first data line DL1.

The first active element T1 includes a semiconductor layer CHb, a gate Gb, a source Sb and a drain Db. The gate Gb is electrically connected to the drain Da of the first switching element SE1. The gate electrode Gb overlaps the channel layer CHb, and an insulating layer GI is sandwiched between the gate electrode Gb and the channel layer CHb. The insulating layer ILD covers the gate Gb. The source electrode Sb and the drain electrode Db are located on the insulating layer ILD and are electrically connected to the channel layer CHb. The source electrode Sb is electrically connected to the first power line PL1.

The flat layer PL is located on the source electrode Sa, the drain electrode Da, the source electrode Sb and the drain electrode Db, and the first light emitting diode L1 is located on the flat layer PL. In some embodiments, the first light emitting diode L1 is electrically connected to the source electrode Sb and the second power line PL2 through the pad PD1 and the pad PD2, respectively.

The second sub-pixel SP2 includes a second switching element SE2, a second active element T2 and a second light emitting diode L2. The second switching element SE2 includes a semiconductor layer CHc, a gate electrode Gc, a source electrode Sc and a drain electrode Dc. The gate electrode Gc is electrically connected to the scan line SL. The gate electrode Gc overlaps the channel layer CHc, and an insulating layer GI is sandwiched between the gate electrode Gc and the channel layer CHc. The insulating layer ILD covers the gate electrode Gc. The source electrode Sc and the drain electrode Dc are located on the insulating layer ILD and are electrically connected to the channel layer CHc. The source electrode Sc is electrically connected to the second data line DL2.

The second active element T2 includes a semiconductor layer CHd, a gate electrode Gd, a source electrode Sd and a drain electrode Dd. The gate electrode Gd is electrically connected to the drain electrode Dc of the second switching element SE2. The gate electrode Gd overlaps the channel layer CHd, and an insulating layer GI is sandwiched between the gate electrode Gd and the channel layer CHd. The insulating layer ILD covers the gate electrode Gd. The source electrode Sd and the drain electrode Dd are located on the insulating layer ILD and are electrically connected to the channel layer CHd. The source electrode Sd is electrically connected to the first power line PL1.

The second light emitting diode L2 is located on the flat layer PL. In some embodiments, the second light emitting diode L2 is electrically connected to the source electrode Sd and the second power line PL2 through the pad PD3 and the pad PD4, respectively.

The third sub-pixel SP3 includes a third switching element SE3, a third active element T3 and a third light emitting diode L3. The third switching element SE3 includes a semiconductor layer CHe, a gate electrode Ge, a source electrode Se and a drain electrode De. The gate electrode Ge is electrically connected to the scan line SL. The gate electrode Ge overlaps the channel layer CHe, and the insulating layer GI is sandwiched between the gate electrode Ge and the channel layer CHe. The insulating layer ILD covers the gate electrode Ge. The source electrode Se and the drain electrode De are located on the insulating layer ILD and are electrically connected to the channel layer CHe. The source electrode Se is electrically connected to the second data line DL3.

The third active element T3 includes a semiconductor layer CHf, a gate electrode Gf, a source electrode S and a drain electrode Df. The gate electrode Gf is electrically connected to the drain electrode De of the third switching element SE3. The gate electrode Gf overlaps the channel layer CHf, and an insulating layer GI is sandwiched between the gate electrode Gf and the channel layer CHf. The insulating layer ILD covers the gate electrode Gf. The source electrode Sf and the drain electrode Df are located on the insulating layer ILD and are electrically connected to the channel layer CHf. The source electrode Sf is electrically connected to the first power line PL1.

The third light emitting diode L3 is located on the flat layer PL. In some embodiments, the third light emitting diode L3 is electrically connected to the source electrode Sf and the second power line PL2 through the pad PD5 and the pad PD6, respectively. In this embodiment, the position of the first active element T1 relative to the first light emitting diode L1, the position of the second active element T2 relative to the second light emitting diode L2, and the position of the third active element T3 relative to the third light emitting diode The positions of the diodes L3 are different from each other, so that the first light emitting diode L1 , the second active element T2 and the third active element T3 can be more easily disposed in the active region AR.

In some embodiments, the pads PD1 ˜ PD6 are multi-layered structures. For example, the pads PD1 ˜ PD6 each include a first pad layer CL1 , a second conductive layer CL2 and a third conductive layer CL3 . In some embodiments, the first conductive layer CL1 is a metal oxide (eg, indium tin oxide), the second conductive layer CL2 is a metal (eg, indium), and the third conductive layer CL3 is a metal (eg, gold), but the present invention Not limited to this. In this embodiment, the first light-emitting diode L1, the second light-emitting diode L2, and the third light-emitting diode L3 are inorganic light-emitting diodes (eg, micro-LEDs), but The present invention is not limited to this. In other embodiments, the first light emitting diode L1 , the second light emitting diode L2 and the third light emitting diode L3 are organic light emitting diodes, electroluminescent elements or other self-luminous elements.

In this embodiment, in order to prevent the signal lines transmitting different signals from short-circuiting each other, each signal line selectively includes conductive layers of different layers, and the conductive layers of different layers are electrically connected to each other through the via holes V .

In this embodiment, the semiconductor layer CHb of the first active element T1, the semiconductor layer CHd of the second active element T2 and the semiconductor layer CHf of the third active element T3 are disposed in the active region AR instead of the peripheral region PR around the active region AR , thereby avoiding the problem that the retractable substrate 20 fails after being stretched and causes the screen Mura.

In this embodiment, the first active element T1, the second active element T2 and the third active element T3 are directly electrically connected to the first light emitting diode L1, the second light emitting diode L2 and the third light emitting diode, respectively Therefore, the quality of the first active element T1, the second active element T2 and the third active element T3 has a greater impact on the display screen than the first switching element SE1, the second switching element SE2 and the third switching element SE3. In some embodiments, based on the limitation of wiring space, the first active element T1, the second active element T2 and the third active element T3, the first switching element SE1, the second switching element SE2 and the third switching element SE3 cannot be all All are arranged in the active area AR, and the first active element T1, the second active element T2 and the third active element T3 are preferably arranged in the active area AR, which can better improve the screen Mura of the retractable substrate 20 after stretching. problem, but the present invention is not limited to this. In other embodiments, if the wiring space is sufficient, the first active element T1, the second active element T2 and the third active element T3, the first switching element SE1, the second switching element SE2 and the third switching element SE3 are all arranged in the active District AR.

4 is a schematic top view of a retractable substrate according to an embodiment of the present invention, wherein FIG. 4 illustrates the semiconductor layer of the first active element T1 and the second sub-pixel SP2 in the first sub-pixel SP1 The semiconductor layer of the second active element T2 and the semiconductor layer of the third active element T3 in the third sub-pixel SP3 are omitted, and the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel are omitted. Other components in Pixel SP3.

It must be noted here that the embodiment of FIG. 4 uses the element numbers and part of the content of the embodiment of FIG. 3A to FIG. 3E , wherein the same or similar numbers are used to represent the same or similar elements, and the same technical content is omitted. illustrate. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

Referring to FIG. 4 , in this embodiment, the shape of the second active element T2 of the retractable substrate 30 is different from the shape of the first active element T1 and the shape of the third active element T3 . For example, the shape of the semiconductor layer of the second active element T2 is different from the shape of the semiconductor layer of the first active element T1 and the shape of the semiconductor layer of the third active element T3. In this embodiment, the semiconductor layer of the second active element T2 is substantially straight, and the semiconductor layer of the first active element T1 and the semiconductor layer of the third active element T3 are substantially L-shaped. The L-shaped or curved shape of the semiconductor layer can disperse the stress and reduce the bad influence on the electrical properties of the semiconductor layer due to strain or stress.

In some embodiments, each device portion 200 is a rectangle with a length L and a width W, and in the direction of the width W of each device portion 200 , the width W1 of the peripheral region PR is 16%W to 40%W, and The width W2 of the peripheral region PR in the direction of the length L of each device portion 200 is 16%L to 40%L.

Based on the above, the semiconductor layer of the first active element T1, the semiconductor layer of the second active element T2, and the semiconductor layer of the third active element T3 are disposed in the active region AR instead of the peripheral region PR around the active region AR, thereby avoiding the possibility of The retractable substrate 30 failed after stretching and caused a problem with the picture Mura.

5 is a schematic top view of a retractable substrate according to an embodiment of the present invention, wherein FIG. 5 illustrates the semiconductor layer of the first active element T1 and the second sub-pixel SP2 in the first sub-pixel SP1 The semiconductor layer of the second active element T2 and the semiconductor layer of the third active element T3 in the third sub-pixel SP3 are omitted, and the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel are omitted. Other components in Pixel SP3.

It must be noted here that the embodiment in FIG. 5 uses the element numbers and part of the content of the embodiment in FIGS. 3A to 3E , wherein the same or similar numbers are used to represent the same or similar elements, and the same technical content is omitted. illustrate. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

Referring to FIG. 5 , in this embodiment, the shape of the second active element T2 of the retractable substrate 40 is different from the shape of the first active element T1 and the shape of the third active element T3 . For example, the shape of the semiconductor layer of the second active element T2 is different from the shape of the semiconductor layer of the first active element T1 and the shape of the semiconductor layer of the third active element T3. In this embodiment, the semiconductor layer of the first active element T1 and the semiconductor layer of the third active element T3 are substantially straight-striped, and the semiconductor layer of the second active element T2 is substantially S-shaped.

The S-shaped or curved shape of the semiconductor layer can disperse the stress and reduce the bad influence on the electrical properties of the semiconductor layer due to strain or stress.

In the case of the same voltage difference, the current of the semiconductor layer with a longer length is smaller. In this embodiment, the length of the semiconductor layer of the second active element T2 is relatively long, and can be arranged corresponding to the blue sub-pixels. The length of the semiconductor layer of the first active element T1 and the semiconductor layer of the third active element T3 is relatively short, and can be arranged corresponding to the red sub-pixel and the green sub-pixel respectively.

In some embodiments, each device portion 200 is a rectangle with a length L and a width W, and in the direction of the width W of each device portion 200 , the width W1 of the peripheral region PR is 16%W to 40%W, and The width W2 of the peripheral region PR in the direction of the length L of each device portion 200 is 16%L to 40%L.

Based on the above, the semiconductor layer of the first active element T1, the semiconductor layer of the second active element T2, and the semiconductor layer of the third active element T3 are disposed in the active region AR instead of the peripheral region PR around the active region AR, thereby avoiding the possibility of The retractable base plate 40 fails after stretching and causes problems with the picture Mura.

10, 20, 30, 40: retractable base plate 100: Patterned substrate 200: Device Department 300: Line Department 310: Signal line 400: Connection part 410: Strengthen the structure AR: Active area BL: buffer layer CHa, CHb, CHc, CHd, CHe, CHf: semiconductor layer CL1: first conductive layer CL2: second conductive layer CL3: the third conductive layer Da, Db, Dc, Dd, De, Df: drain DL1: The first data line DL2: Second data line DL3: The third data line Ga, Gb, Gc, Gd, Ge, Gf: Gate GI, ILD: insulating layer L: length L1: The first light-emitting diode L2: The second light-emitting diode L3: the third light-emitting diode PD1, PD2, PD3, PD4, PD5, PD6: pads PL: flat layer PL1: first power line PL2: Second power cord PR: Surrounding area Sa, Sb, Sc, Sd, Se, Sf: source SE1: first switching element SE2: Second switching element SE3: The third switching element SP1: First Subpixel SP2: Second Subpixel SP3: Third Subpixel SGL: signal line SL: scan line TH: through hole T1: The first active element T2: The second active element T3: The third active element V: via hole W, W1, W2: width

FIG. 1A is a schematic top view of a retractable substrate according to an embodiment of the present invention. FIG. 1B is a schematic top view of the retractable substrate of FIG. 1A after being stretched. FIG. 2 is a schematic diagram of strain amount simulation of the retractable substrate of FIG. 1B . 3A is a schematic top view of a retractable substrate according to an embodiment of the present invention. FIG. 3B is a schematic top view of the retractable base plate of FIG. 3A with some components omitted. FIG. 3C is a schematic top view of the retractable base plate of FIG. 3A with some components omitted. FIG. 3D is a schematic cross-sectional view of the retractable substrate of FIG. 3A . 3E is an equivalent circuit diagram of a sub-pixel according to an embodiment of the present invention. FIG. 4 is a schematic top view of a retractable base plate according to an embodiment of the present invention. FIG. 5 is a schematic top view of a retractable base plate according to an embodiment of the present invention.

10: Retractable base plate

100: Patterned substrate

200: Device Department

300: Line Department

310: Signal line

400: Connection part

410: Strengthen the structure

AR: Active area

L: length

PR: Surrounding area

SP1: First Subpixel

SP2: Second Subpixel

SP3: Third Subpixel

TH: through hole

T1: The first active element

T2: The second active element

T3: The third active element

W, W1, W2: width

Claims (10)

A retractable base plate, comprising: a patterned substrate; A plurality of device parts are located on the patterned substrate, wherein each of the device parts includes an active area and a peripheral area surrounding the active area, and each of the device parts includes a first active element disposed in the active area and a a second active element; and A plurality of circuit parts are located on the patterned substrate and are connected to the corresponding device parts. The retractable substrate of claim 1, wherein the peripheral region has a width of about 10 microns to 250 microns. The retractable base plate of claim 1, wherein each of the device sections comprises: a first sub-pixel including the first active element and a first light emitting diode directly electrically connected to the first active element; a second sub-pixel including a second active element and a second light emitting diode directly electrically connected to the second active element; and A third sub-pixel includes a third active element and a third light emitting diode directly electrically connected to the third active element, wherein the second sub-pixel is located between the first sub-pixel and the first sub-pixel between three sub-pixels; and Each of the circuit portions includes at least one signal line electrically connected to the corresponding first sub-pixel, the corresponding second sub-pixel and/or the corresponding third sub-pixel. The retractable substrate of claim 3, wherein the shape of the semiconductor layer of the second active element is different from the shape of the semiconductor layer of the first active element and the shape of the semiconductor layer of the third active element. The retractable substrate of claim 3, wherein the position of the first active element relative to the first light emitting diode, the position of the second active element relative to the second light emitting diode, and the third The positions of the active elements relative to the third light emitting diode are different from each other. The retractable base plate of claim 1, wherein each of the device portions is a rectangle of length L and width W, wherein: In the direction of the width of each of the device portions, the width of the peripheral region is 16%W to 40%W, and The width of the peripheral region is 16%L to 40%L in the direction of the length of each of the device portions. The retractable substrate of claim 1, wherein the patterned substrate has a plurality of through holes. The retractable substrate of claim 6, wherein one of the through holes is substantially surrounded by at least four device parts. The retractable base plate according to claim 6, further comprising: A plurality of connecting portions are disposed on the patterned substrate and adjacent to the corresponding circuit portions, and each of the connecting portions includes a plurality of reinforcing structures arranged in sequence. The retractable base plate according to claim 6, wherein each of the through holes is in the shape of a dumbbell.

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