TWI703540B - Display panel - Google Patents

Abstract

A display panel incudes a substrate, a pixel array, a chip, first multiplexers, signal source lines, a repair line, a second multiplexer, and a first transmission line. The first multiplexers are adjacent to the first side of the pixel array and electrically connected to data lines. Signal source lines are electrically connected to the chip and the first multiplexers. The repair line has first pads. The first multiplexers are located between the first pads and the pixel array. Each of the first pads overlaps a corresponding one of the signal source lines. The second multiplexer is electrically connected to the repair line. The first transmission line overlaps the second multiplexer. The first transmission line has second pads on a second side of the pixel array. Each of the second pads is overlapped with a corresponding one of the data lines.

Description

Display panel

The present invention relates to a display panel, and particularly relates to a display panel with repair lines.

The existing display panel usually uses multiple scan lines and multiple data lines to control the sub-pixels arranged in an array to achieve the purpose of displaying images. Each scan line is sequentially turned on to turn on or off the corresponding switch element, so that the signal transmitted by each data line can be transmitted into the sub-pixels, thereby changing the state of the corresponding sub-pixels, and achieving the purpose of displaying images.

Although the related technology of the display panel has matured, the component elements of the display panel, such as the pixel array, will inevitably have some defects in the manufacturing process. For example, the scan lines and data lines in the pixel array are prone to disconnection due to their long lengths. When the scan line or the data line is broken, it will cause a part of the sub-pixels to fail (line defect), so we must try to repair the broken line. In addition, it is very difficult to achieve zero defect rate only by relying on improving process technology. Therefore, defect repair technology for display panels becomes very important.

In the prior art, the defect repair of the display panel is usually performed by means of laser welding and/or laser cutting. For example, by welding the repair line and the damaged data line, the signal of the repair line can be transmitted to the damaged data line. However, the signal transmitted by the repair line is easily affected by parasitic capacitance, which leads to problems such as signal attenuation and lower repair success rate.

The present invention provides a display panel, which can improve the problems of repair line signal attenuation and reduction of repair success rate.

An embodiment of the present invention provides a display panel including a substrate, a pixel array, a chip, a plurality of first multiplexers, a plurality of signal source lines, a repair line, a second multiplexer, and a first transmission line. The pixel array is located on the substrate. The pixel array includes multiple data lines, multiple scan lines, and multiple sub-pixels. The first end of each data line is close to the first side of the pixel array, and the second end of each data line is close to the second side of the pixel array. The multiple sub-pixels are electrically connected to the data line and the scan line. The wafer is located on the substrate. The plurality of first multiplexers are close to the first side of the pixel array and are electrically connected to the data line. The multiple signal source lines are electrically connected to the chip and the first multiplexer. The repair line overlaps the signal source line. The repair line has a plurality of first pads, the first multiplexer is located between the first pads and the pixel array, and each first pad overlaps a corresponding one of the signal source lines. The second multiplexer is electrically connected to the repair line. The first transmission line overlaps the second multiplexer. The first transmission line has a plurality of second pads located on the second side of the pixel array. Each second pad overlaps a corresponding one of the data lines.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout the specification, the same or similar reference signs indicate the same or similar elements. It should be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected" to another element, the aforementioned element may be directly on or connected to another element, Or an intermediate element between the aforementioned element and another element may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements between the aforementioned element and the other element. As used herein, "connection" can refer to physical and/or electrical connection. Furthermore, "electrical connection" or "coupling" can mean that there are other elements between two elements.

As used herein, "approximately", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the The specific amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the "about", "approximately" or "substantially" used herein can select an acceptable deviation range or standard deviation based on optical properties, etching properties or other properties.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the related technology and the present invention, and will not be interpreted as idealized or excessively formal meanings unless this text Clearly defined in this way.

FIG. 1 is a schematic top view of a display panel according to an embodiment of the invention. FIG. 2A is a partial enlarged view of area A of the display panel of FIG. 1. FIG. 2B is a partial circuit diagram of area A of the display panel of FIG. 1. Fig. 3A is a schematic cross-sectional view taken along line aa' in Fig. 2A. Fig. 3B is a schematic cross-sectional view taken along line bb' of Fig. 2A. FIG. 4A is a partial enlarged view of area B of the display panel of FIG. 1. 4B is a partial circuit diagram of area B of the display panel of FIG. 1. Fig. 5 is a schematic cross-sectional view taken along line cc' of Fig. 4A. FIG. 6 is a partial enlarged view of area C of the display panel in FIG. 1. Fig. 7 is a schematic cross-sectional view taken along the line dd' of Fig. 6.

Please refer to FIG. 1, the display panel 10 includes a substrate 100, a pixel array 200, a chip 300, a plurality of first multiplexers 410, a second multiplexer 420, a plurality of signal source lines 510, a repair line 520, and a first transmission line 530. In this embodiment, the display panel 10 further includes a wire 540, a signal amplifier 600, a flexible circuit board 700, a circuit board 800, and an opposite substrate 900.

The material of the substrate 100 can be glass, quartz, organic polymer, or opaque/reflective material (for example, conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive materials or metals are used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems.

The substrate 100 includes a display area 110 and a peripheral area 120 located outside the display area 110.

The pixel array 200 is located on the substrate 100. The pixel array 200 includes a plurality of data lines 210, a plurality of scan lines 220, and a plurality of sub-pixels 230. The first end 212 of each data line 210 is close to the first side S1 of the pixel array 200, and the second end 214 of each data line 210 is close to the second side S2 of the pixel array 200. A plurality of sub-pixels 230 are located on the display area 110. The multiple data lines 210 and the multiple scan lines 220 are partially located on the display area 110, and the multiple data lines 210 and the multiple scan lines 220 are partially located on the peripheral area 120.

The plurality of sub-pixels 230 are electrically connected to the plurality of data lines 210 and the plurality of scan lines 220. In this embodiment, each sub-pixel 230 includes a switching element 232 and a pixel electrode 234. The switching element 232 is electrically connected to a corresponding scan line 220, a corresponding data line 210, and a corresponding pixel electrode 234. In this embodiment, the switching element 232 is a bottom gate type switching element, but the invention is not limited to this. In other embodiments, the switching element 232 is a top gate type switching element or other types of switching elements.

The wafer 300 is located on the substrate 100. In this embodiment, the wafer 300 is located on the peripheral area 120 of the substrate 100. The chip 300 includes, for example, a source driving circuit and other circuits, and the chip 300 is electrically connected to the data line 210. In some embodiments, the display panel 10 includes a gate driving circuit (not shown). The gate driving circuit may be located in the chip 300 or in other positions on the substrate 100. The gate driving circuit is electrically connected to the scan line 220. The number of chips 300 can be adjusted according to actual needs.

Please refer to FIG. 1, FIG. 2A and FIG. 2B at the same time, a plurality of first multiplexers 410 are located on the substrate 100. In this embodiment, the first multiplexer 410 is located on the peripheral area 120 of the substrate 100.

The plurality of first multiplexers 410 are close to the first side S1 of the pixel array 200 and are electrically connected to the data line 210. The multiple signal source lines 510 are electrically connected to the chip 300 and the first multiplexer 410.

In this embodiment, each first multiplexer 410 includes a first switching element 412 and a second switching element 414. The drain 412D of the first switching element 412 and the drain 414D of the second switching element 414 are electrically connected to a corresponding one of the signal source lines 510. The source 412S of the first switching element 412 and the source 414S of the second switching element 414 are electrically connected to two different data lines 210 respectively.

Please refer to FIG. 1, FIG. 2A, FIG. 2B, and FIG. 3A. In this embodiment, the plurality of data lines 210 includes a data line 2101, a data line 2102, a data line 2103, and a data line 2104 arranged in sequence. The number of data lines 210 can be adjusted according to actual needs.

The plurality of first multiplexers 410 includes a first multiplexer 4101 and a first multiplexer 4102 arranged in sequence. The first multiplexer 4101 is electrically connected to the data line 2101 and the data line 2103. The first multiplexer 4102 is electrically connected to the data line 2102 and the data line 2104. In this way, the problem of the image texture of the display panel 10 can be improved, and the display panel 10 can be more power-saving.

2A and 3A, in this embodiment, the display panel 10 further includes a first insulating layer I1 and a second insulating layer I2. The first insulating layer I1 is located on the substrate 100. The second insulating layer I2 is located on the first insulating layer I1.

The first multiplexer 4101 is electrically connected to the data line 2103 through the connection line CS and the bridge structure BS. The connection line CS is connected to the first multiplexer 4101 and is electrically connected to the bridge structure BS through the first opening H1. The bridge structure BS spans the data line 2102. The data line 2103 is electrically connected to the bridge structure BS through the second opening H2. The first opening H1 and the second opening H2 penetrate the second insulating layer I2. In other embodiments, the positions of the data line 2102 and the data line 2103 are interchanged, and the first multiplexer 4101 does not need to be electrically connected to the data line 2103 through the connection line CS and the bridge structure BS. In other words, the present invention does not limit the display panel 10 to include the connecting line CS and the bridge structure BS.

2A and FIG. 2B, in this embodiment, the display panel 10 further includes a first control line 416 and a second control line 418. The first control line 416 is electrically connected to the gate 412G of the first switching element 412. The second control line 418 is electrically connected to the gate 414G of the second switching element 414.

Although in this embodiment, the first multiplexer 410 includes two switching elements as an example, the invention is not limited to this. In other embodiments, the first multiplexer 410 includes more than three switching elements, and each first multiplexer 410 is electrically connected to three data lines 210.

Please refer to FIG. 1, FIG. 2A, FIG. 2B, and FIG. 3B, the repair line 520 overlaps the signal source line 510. The repair line 520 has a plurality of first pads 522. The first multiplexer 410 is located between the first pad 522 and the pixel array 200.

Each first pad 522 overlaps a corresponding one of the signal source lines 510 in the direction D perpendicular to the substrate 100. The second insulating layer I2 is located between the first pad 522 of the repair line 520 and the signal source line 510. Since the first pad 522 overlaps the signal source line 510 instead of the data line 210, and the number of the signal source line 510 is less than the number of the data line 210, the parasitic capacitance on the repair line 520 can be reduced, and the signal It will not be transmitted to the repair line 520 after being weakened by the first multiplexer 410. Therefore, the signal attenuation of the repair line 520 and the reduction of the repair success rate of the display panel 10 can be improved.

In this embodiment, the repair line 520 includes a first line segment 524 and a second line segment 526. A part of the first pad 522 is located on the first line segment 524 and overlaps a part of the signal source line 510. Another part of the first pad 522 is located on the second line segment 526 and overlaps another part of the signal source line 510, thereby further reducing the parasitic capacitance on the repair line 520, and improving the signal attenuation of the repair line 520 and the display panel 10 is successfully repaired Rate reduction and other issues.

In this embodiment, the width of the first pad 522 is smaller than the widths of the first line segment 524 and the second line segment 526, but the invention is not limited thereto. It should be noted that the size of the first pad 522 in FIGS. 1 and 3 is only for illustration. For the convenience of description, the size of the first pad 522 in FIGS. 1 and 3 is additionally enlarged.

Please refer to FIGS. 1, 4A, 4B and 5 at the same time, the second multiplexer 420 is electrically connected to the repair line 520. In this embodiment, the signal amplifier 600 is electrically connected to the repair line 520. The wire 540 is electrically connected to the signal amplifier 600 and the second multiplexer 420. In other words, after the signal on the repair line 520 is enhanced by the signal amplifier 600, it is transmitted to the second multiplexer 420 via the wire 540. In this embodiment, the signal amplifier 600 is located on the chip 300.

The second multiplexer 420 includes a third switching element 422 and a fourth switching element 424. The drain 422D of the third switching element 422 and the drain 424D of the fourth switching element 424 are electrically connected to the repair line 520. In this embodiment, the drain 422D of the third switching element 422 and the drain 424D of the fourth switching element 424 are electrically connected to the repair line 520 through the wire 540 and the signal amplifier 600.

In this embodiment, the display panel 10 further includes a third control line 426 and a fourth control line 428. The third control line 426 is electrically connected to the gate 422G of the third switching element 422. The fourth control line 428 is electrically connected to the gate 424G of the fourth switching element 424. In this embodiment, the signal timings respectively controlled by the third control line 426 and the fourth control line 428 are the same as the first control line 416 and the second control line 418. In other words, the third control line 426 is electrically connected to the first control line 416, and both transmit the same signal; the fourth control line 428 is electrically connected to the second control line 418, and both transmit the same signal.

The first transmission line 530 overlaps the second multiplexer 420 in the direction D perpendicular to the substrate 100. In this embodiment, the first transmission line 530 overlaps the source 422S of the third switching element 422 and the source 424S of the fourth switching element 424. In this embodiment, the second insulating layer I2 is sandwiched between the first transmission line 530 and the source electrode 422S and between the first transmission line 530 and the source electrode 424S. The first transmission line 530 bypasses the pixel array 200 from the third side S3 of the pixel array 200, wherein the third side S3 of the pixel array 200 is located between the first side S1 and the second side S2 of the pixel array 200.

Please refer to FIGS. 1, 6 and 7, the first transmission line 530 has a plurality of second pads 532 located on the second side S2 of the pixel array 200. Each second pad 532 overlaps a corresponding one of the data lines 210 (including the data lines 2101 to 2104 in FIG. 6). In this embodiment, each data line 210 (including the data lines 2101 to 2104 in FIG. 6) includes a first conductive layer 210a and a second conductive layer 210b, respectively. In this embodiment, the first conductive layer 210a is located between the first insulating layer I1 and the second insulating layer I2, and the second conductive layer 210b is located on the second insulating layer I2. The second conductive layer 210b is electrically connected to the first conductive layer 210a through the opening H3, and the opening H3 is located in the second insulating layer I2, for example. Each second pad 532 overlaps the first conductive layer 210a of the data line 210 in a direction D perpendicular to the substrate 100, and a second insulating layer I2 is sandwiched between the second pad 532 and the first conductive layer 210a.

In this embodiment, multiple marks LB are located beside the data line 210, and the marks LB may be numbers. Setting the mark LB can make the position of the damaged data line 210 easier to be identified.

Please refer to FIG. 1, the flexible circuit board 700 and the circuit board 800 are located on the substrate 100. The opposite substrate 900 is located on the substrate 100 and covers the pixel array 200. In some embodiments, the display panel 10 is a liquid crystal display panel, and a liquid crystal material is sandwiched between the counter substrate 900 and the substrate 100. In some embodiments, the counter substrate 900 includes a filter element.

FIG. 8 is a schematic top view of a display panel according to an embodiment of the invention. FIG. 9 is a partial enlarged view of area A of the display panel of FIG. 8. Fig. 10 is a schematic cross-sectional view taken along line bb' of Fig. 9. FIG. 11 is a partial enlarged view of area B of the display panel of FIG. 8. Fig. 12 is a schematic cross-sectional view taken along the line cc' in Fig. 11. FIG. 13 is a partial enlarged view of area C of the display panel of FIG. 8. Fig. 14 is a schematic cross-sectional view taken along the line dd' of Fig. 13.

The main difference between the display panel 10a of FIG. 8 and the display panel 10 of FIG. 1 is that one of the data lines 210 of the display panel 10a has a defect DF.

In this embodiment, the data line 210 with the defective DF is repaired by a welding process. In this embodiment, the data line 2103 has a defect DF as an example.

Please refer to FIG. 8, FIG. 9, and FIG. 10, one of the first pads 522 is welded to a corresponding one of the signal source lines 510. In this embodiment, the signal source line 510 welded to the first pad 522 corresponds to the data line 2103 with a defect DF, so that the signal provided to the data line 2103 can be transmitted to the repair line 520.

In this embodiment, by laser welding the first pad 522 and the signal source line 510, the first welding hole WH1 is formed in the second insulating layer I2.

Referring to FIGS. 8, 11 and 12, in the second multiplexer 420, the source 422S of the third switching element 422 is welded to the first transmission line 530, so that a second welding hole WH2 is formed in the second insulating layer I2. And the source 424S of the fourth switching element 424 is open. In other words, the signal on the repair line 520 is amplified by the signal amplifier 600 and then transmitted to the wire 540, and the signal on the wire 540 is controlled by the third switch element 422 to control whether it is transmitted to the first transmission line 530. It can also be said that the third switching element 422 controls the timing of the signal on the first transmission line 530.

In other embodiments, the source 424S of the fourth switching element 424 is welded to the first transmission line 530, and the source 422S of the third switching element 422 is disconnected.

In this embodiment, since the second multiplexer 420 outputs a signal through a first transmission line 530, compared to the source of the third switching element and the source of the fourth switching element, outputting signals through different transmission lines, This embodiment can reduce the area of the peripheral area 120 of the display panel 10a occupied by the transmission line. Therefore, the display panel 10a of this embodiment may have a larger space for other circuits (for example, a gate driving circuit).

Referring to FIGS. 8, 13 and 14, one of the second pads 532 is welded to a corresponding one of the data lines 210, so that a third welding hole WH3 is formed in the second insulating layer I2. In this embodiment, the data line 210 welded to the second pad 532 is the data line 2103 with defect DF, so that the signal of the signal source line 510 can be provided to the data line 2103.

Based on the above, even if the data line 2103 is broken at the defect DF, the data line 2103 located behind the defect DF can still transmit signals, so that the sub-pixel 230 located behind the defect DF can operate. In addition, since the first pad 522 overlaps the signal source line 510 instead of the data line 210, the parasitic capacitance on the repair line 520 can be reduced, and the signal will not be transmitted to after being weakened by the first multiplexer 410 The repair line 520, therefore, can improve the problem of weak signal of the repaired data line 2103 and the problem of low repair success rate.

In other embodiments, the data line 2103 is short-circuited, the part of the data line 2103 short-circuited by the laser cutting process, and then the data line 2103 is repaired.

FIG. 15 is a schematic top view of a display panel according to an embodiment of the invention. FIG. 16A is a partial enlarged view of area C of the display panel of FIG. 15. FIG. 16B is a partial circuit diagram of area C of the display panel of FIG. 15.

The display panel 10b of FIG. 15 is similar to the display panel 10a of FIG. 9, so the same parts of the display panel 10b and the display panel 10a are not described here. The main difference between the display panel 10b and the display panel 10a is that the display panel 10b further includes a second transmission line 530a.

In this embodiment, the second multiplexer 420 is disposed on the second side S2 of the pixel array 200. The wire 540 bypasses the pixel array 200 from the third side S3 of the pixel array 200.

The first transmission line 530 and the second transmission line 530a overlap the second multiplexer 420. The source 422S of the third switching element 422 is electrically connected to the first transmission line 530. The source 424S of the fourth switching element 424 is electrically connected to the second transmission line 530a.

The first transmission line 530 has a plurality of second pads 532 located on the second side S2 of the pixel array 200, and each of the second pads 532 overlaps a corresponding one of the data lines 210. The second transmission line 530a has a plurality of third pads 532a located on the second side S2 of the pixel array 200, and each third pad 532a overlaps a corresponding one of the data lines 210.

In this embodiment, the data line 2103 has a defect DF. The second pad 532 or the second pad 532a is welded to the data line 2103 with the defect DF so that the signal of the signal source line 510 can be provided to the data line 2103. In this embodiment, the second pad 532 and the data line 2103 are welded, so that a third welding hole WH3 is formed in the second insulating layer I2.

Although in this embodiment, the welding of the second pad 532 and the data line 2103 is taken as an example, the present invention is not limited to this. In other embodiments, other data lines have defects. For example, the data line 2102 has defects. Therefore, the third pad 532a and the data line 2102 are welded to repair the data line 2102.

Based on the above, even if the data line 2103 is broken at the defect DF, the data line 2103 located behind the defect DF can still transmit signals, so that the sub-pixel 230 located behind the defect DF can operate. In addition, since the first pad 522 overlaps the signal source line 510 instead of the data line 210, the parasitic capacitance on the repair line 520 can be reduced, and the signal will not be transmitted to after being weakened by the first multiplexer 410 The repair line 520, therefore, can improve the problem of the signal weakening of the repaired data line 2103 and the problem of the reduction of the repair success rate.

FIG. 17 is a schematic top view of a display panel according to an embodiment of the invention.

The display panel 10c of FIG. 17 is similar to the display panel 10b of FIG. 15, so the same parts of the display panel 10c and the display panel 10b will not be described here. The main difference between the display panel 10c and the display panel 10b is that part of the repair line 520 and part of the wire 540 of the display panel 10c pass through the flexible circuit board 700 and the circuit board 800.

Please refer to FIG. 17, in this embodiment, part of the repair line 520 and part of the wire 540 are located in the flexible circuit board 700 and the circuit board 800. For example, part of the second line segment 526 and part of the wire 540 are located in the flexible circuit board 700 and the circuit board 800.

In this embodiment, by providing the flexible circuit board 700 and the circuit board 800, the capacitance generated when the repair line 520 and the wire 540 cross other circuits can be reduced.

FIG. 18 is a schematic top view of a display panel according to an embodiment of the invention.

The display panel 10d of FIG. 18 is similar to the display panel 10c of FIG. 17, so the same parts of the display panel 10d and the display panel 10c are not described here. The main difference between the display panel 10d and the display panel 10c is that the signal amplifier 600 of the display panel 10d is located on the flexible circuit board 700.

In summary, since the first pad of the repair line overlaps the signal source line instead of the data line, the parasitic capacitance on the repair line can be reduced, and the signal will not be transmitted to after being weakened by the first multiplexer. The repair line, therefore, can improve the problem of the signal weakening of the repaired data line and the problem of low repair success rate.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10, 10a, 10b, 10c, 10d: electronic device 100: substrate 110: display area 120: Surrounding area 200: pixel array 210, 2101~2104: data line 210a: first conductive layer 210b: second conductive layer 220: scan line 230: sub-pixel 232: switching element 234: pixel electrode 300: chip 410, 4101, 4102: the first multiplexer 412: first switching element 412D, 414D, 422D, 424D: drain 412G, 414G, 422G, 424G: gate 412S, 414S, 422S, 424S: source 414: second switching element 416: First Control Line 418: second control line 420: second multiplexer 422: third switching element 424: fourth switching element 426: Third Control Line 428: Fourth Control Line 510: signal source line 520: repair line 522: first pad 524: first line segment 526: second line segment 530: The first transmission line 530a: second transmission line 532: second pad 532a: third pad 540: Wire 600: signal amplifier 700: Flexible circuit board 800: circuit board 900: Opposite substrate A, B, C: area BS: Bridge structure CS: connection line D: direction DF: defect H1: First opening H2: second opening H3: opening I1: first insulating layer I2: second insulating layer LB: Mark S1: First side S2: second side S3: Third side WH1: The first welding hole WH2: second welding hole WH3: third welding hole

FIG. 1 is a schematic top view of a display panel according to an embodiment of the invention. FIG. 2A is a partial enlarged view of area A of the display panel of FIG. 1. FIG. 2B is a partial circuit diagram of area A of the display panel of FIG. 1. Fig. 3A is a schematic cross-sectional view taken along line aa' in Fig. 2A. Fig. 3B is a schematic cross-sectional view taken along line bb' of Fig. 2A. FIG. 4A is a partial enlarged view of area B of the display panel of FIG. 1. 4B is a partial circuit diagram of area B of the display panel of FIG. 1. Fig. 5 is a schematic cross-sectional view taken along line cc' of Fig. 4A. FIG. 6 is a partial enlarged view of area C of the display panel in FIG. 1. Fig. 7 is a schematic cross-sectional view taken along the line dd' of Fig. 6. FIG. 8 is a schematic top view of a display panel according to an embodiment of the invention. FIG. 9 is a partial enlarged view of area A of the display panel of FIG. 8. Fig. 10 is a schematic cross-sectional view taken along line bb' of Fig. 9. FIG. 11 is a partial enlarged view of area B of the display panel of FIG. 8. Fig. 12 is a schematic cross-sectional view taken along the line cc' in Fig. 11. FIG. 13 is a partial enlarged view of area C of the display panel of FIG. 8. Fig. 14 is a schematic cross-sectional view taken along the line dd' of Fig. 13. FIG. 15 is a schematic top view of a display panel according to an embodiment of the invention. FIG. 16A is a partial enlarged view of area C of the display panel of FIG. 15. FIG. 16B is a partial circuit diagram of area C of the display panel of FIG. 15. FIG. 17 is a schematic top view of a display panel according to an embodiment of the invention. FIG. 18 is a schematic top view of a display panel according to an embodiment of the invention.

10a: Electronic device

100: substrate

110: display area

120: Surrounding area

200: pixel array

210: data line

220: scan line

230: sub-pixel

232: switching element

234: pixel electrode

300: chip

410: first multiplexer

420: second multiplexer

510: signal source line

520: repair line

522: first pad

524: first line segment

526: second line segment

530: The first transmission line

532: second pad

540: Wire

600: signal amplifier

700: Flexible circuit board

800: circuit board

900: Opposite substrate

A, B, C: area

D: direction

DF: defect

S1: First side

S2: second side

S3: Third side

WH1: The first welding hole

WH2: second welding hole

WH3: third welding hole

Claims (13)

A display panel including: A substrate; A pixel array is located on the substrate, and the pixel array includes: A plurality of data lines and a plurality of scan lines, wherein the first end of each data line is close to the first side of the pixel array, and the second end of each data line is close to the second side of the pixel array; and A plurality of sub-pixels are electrically connected to the data lines and the scan lines; A chip on the substrate; A plurality of first multiplexers are close to the first side of the pixel array and are electrically connected to the data lines; Multiple signal source lines are electrically connected to the chip and the first multiplexers; A repair line overlaps the signal source lines, wherein the repair line has a plurality of first pads, the first multiplexers are located between the first pads and the pixel array, and each of the first pads A pad overlaps the corresponding one of the signal source lines; and A second multiplexer, electrically connected to the repair line; and A first transmission line overlaps the second multiplexer, and the first transmission line has a plurality of second pads located on the second side of the pixel array, and each of the second pads overlaps the data lines The corresponding one in. According to the display panel described in item 1 of the scope of patent application, each of the first multiplexers includes: A first switching element; and A second switching element, wherein the drain of the first switching element and the drain of the second switching element are electrically connected to a corresponding one of the signal source lines, and the source of the first switching element and the first The sources of the two switching elements are respectively electrically connected to two different ones of the data lines. The display panel described in item 2 of the scope of patent application further includes: A first control line electrically connected to the gates of the first switching elements; and A second control line is electrically connected to the gates of the second switching elements. The display panel described in item 1 of the scope of patent application, wherein the second multiplexer includes: A third switching element; and A fourth switch element, wherein the drain of the third switch element and the drain of the fourth switch element are electrically connected to the repair line. The display panel described in item 4 of the scope of patent application further includes: A third control line electrically connected to the gate of the third switching element; and A fourth control line is electrically connected to the gate of the fourth switching element. According to the display panel described in claim 5, the source of the third switching element is welded to the first transmission line, and the source of the fourth switching element is disconnected. The display panel described in item 5 of the scope of patent application further includes: A second transmission line electrically connected to the source of the fourth switching element, wherein the second transmission line has a plurality of third pads on the second side, and each of the third pads overlaps the data lines The corresponding one. The display panel described in item 4 of the scope of patent application further includes: A signal amplifier electrically connected to the repair line; and A wire is electrically connected to the signal amplifier and the second multiplexer. In the display panel described in item 8 of the scope of patent application, the signal amplifier is located on the chip. The display panel described in item 8 of the scope of patent application further includes: A flexible circuit board is located on the substrate, and the signal amplifier is located on the flexible circuit board. The display panel described in item 1 of the scope of patent application, wherein the repair line includes: A first line segment, part of the first pads are located on the first line segment and overlap a part of the signal source lines; and A second line segment, and another part of the first pads are located on the first line segment and overlap with the other part of the signal source lines. In the display panel described in item 1 of the scope of patent application, one of the first pads is welded to the corresponding one of the signal source lines. In the display panel described in item 1 of the scope of patent application, one of the second pads is welded to the corresponding one of the data lines.

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