TW202215664A - Semiconductor element and semiconductor device - Google Patents

Abstract

The present invention provides: a semiconductor element which has improved forward characteristics, and is particularly useful for power devices; and a semiconductor device. A semiconductor element which is a multilayer structure that is provided with a semiconductor layer which contains, as a main component, a crystalline oxide semiconductor (for example, [alpha]-Ga2O3), an electrode layer which is superposed on the semiconductor layer, and a conductive substrate which is superposed on the electrode layer directly or with another layer being interposed therebetween, wherein the conductive substrate contains a group 6 metal of the periodic table; and a semiconductor device which is provided with this semiconductor element.

Description

Semiconductor elements and semiconductor devices

The present invention relates to a semiconductor element useful as a power element or the like.

Semiconductor devices using gallium oxide (Ga ₂ O ₃ ) with a large energy gap are attracting attention as next-generation switching elements that can achieve high withstand voltage, low loss, and high heat resistance, and are expected to be used in power applications such as inverters. semiconductor device. Moreover, because of the wide energy gap, it is also expected to be used as light-emitting devices such as LEDs and sensors. According to Patent Document 1, the energy gap of the gallium oxide can be controlled by indium or aluminum, respectively, or by combining them to form a mixed crystal, which constitutes a very attractive material system as an InAlGaO-based semiconductor. Here, InAlGaO-based semiconductor means In _X Al _Y Ga _Z O ₃ (0≤X≤2, 0≤Y≤2, 0≤Z≤2, X+Y+Z=1.5 to 2.5), which can be classified into It is the same material system that contains gallium oxide.

A beta gallium oxide substrate and a sapphire substrate as underlying substrates have been studied to realize a semiconductor device using these InAlGaO-based semiconductors. According to Patent Document 2, when a β gallium oxide substrate is used, the homogeneous epitaxial growth of gallium oxide can be performed, and the quality of the aluminum oxide gallium thin film can be improved. However, the size of the available substrate is limited, and it is difficult to increase the diameter compared to materials such as silicon or sapphire that have been mass-produced. According to Patent Document 3 and Patent Document 4, when a sapphire substrate is used, an Al _X Ga _Y O ₃ (0≤X≤2, 0≤Y≤2, X+Y=2) thin film having a corundum structure can be improved in quality , but the β-gallia structure membrane is difficult to achieve high quality. And because sapphire is an insulator, there is also a problem that current cannot flow to the underlying material. In this case, electrodes cannot be formed on the underlying material, resulting in a limitation in the output current per unit area of the semiconductor device. In the case of large-diameter sapphire to 6 inches and 8 inches, the industrial application of such large-diameter sapphire has not yet matured, so it may not be stably obtained, and there is also a problem that the acquisition cost increases.

In addition, the low thermal conductivity of gallium oxide and sapphire is also a problem for the heat generated by the large current of the semiconductor device and the operation at high temperature. Furthermore, the properties of the underlying material also pose a problem for realizing the electrical properties of a low-loss semiconductor device. For example, in order to realize a semiconductor with high withstand voltage and low loss, in addition to reducing the loss of the channel layer, it is necessary to reduce the loss other than the channel layer. For example, loss reduction in a contact region constituting a semiconductor device is required, and in a vertical semiconductor device, a lower loss is further required for the underlying material and the layers between the underlying material and the channel layer.

Patent Document 5 describes a stacked semiconductor structure in which a support layer containing a conductive material having a thermal expansion coefficient different from that of the semiconductor layer as a main component is stacked on a semiconductor layer using an InAlGaO-based semiconductor via a conductive adhesive layer. However, the semiconductor structure described in Citation 5 is not practical in terms of forward properties and the like, and is not sufficiently satisfied with warpage, which is a problem peculiar to InAlGaO-based semiconductors. Therefore, a semiconductor structure that can fully exhibit the semiconductor properties of the InAlGaO-based semiconductor and is excellent in heat dissipation and electrical properties is expected.

In addition, Patent Document 1 and Patent Document 5 are patent applications filed by the applicant of the present application. [Prior Art Literature] [Patent Literature]

[Patent Document 1] International Publication No. 2014/050793 [Patent Document 2] International Publication No. 2013/035842 [Patent Document 3] International Publication No. 2013/035844 [Patent Document 4] Japanese Patent Laid-Open No. 2013-58637 [Patent Document 5] Japanese Patent Laid-Open No. 2016-81496

[The problem to be solved by the invention]

An object of the present invention is to provide a semiconductor element having excellent electrical characteristics such as forward characteristics. [Means of Solving Problems]

In order to achieve the above object, the inventors of the present invention have conducted detailed studies and found that, in the production (previous step) of a semiconductor element using a semiconductor layer containing a crystalline oxide semiconductor as a main component, if a conductive substrate containing molybdenum is used, it is not only the same as the result obtained The adhesion between the electrode and the adhesive layer in the semiconductor element is further improved, and warpage can be suppressed, and the electrical characteristics such as the forward characteristic of the obtained semiconductor element become better. A semiconductor layer containing a material semiconductor as a main component, an electrode layer laminated on the semiconductor layer, and a conductive substrate laminated directly or via other layers on the electrode layer, and a semiconductor element in which the conductive substrate contains molybdenum, the order Excellent electrical properties such as directional characteristics can solve the above-mentioned conventional problems at one stroke. In addition, the inventors of the present invention have completed the present invention after repeated studies after obtaining the above-mentioned findings.

That is, the present invention relates to the following inventions. [1] A semiconductor element comprising at least a semiconductor layer containing a crystalline oxide semiconductor as a main component, an electrode layer laminated on the semiconductor layer, and a conductive substrate laminated directly on the electrode layer or via other layers, The aforementioned conductive substrate contains at least a metal of Group 6 of the periodic table. [2] The semiconductor device according to the aforementioned [1], wherein the metal of Group 6 of the periodic table is molybdenum. [3] The semiconductor device according to the aforementioned [1] or [2], wherein the conductive substrate further comprises a metal of Group 11 of the periodic table. [4] The semiconductor device according to the aforementioned [3], wherein the metal of Group 11 of the periodic table is copper. [5] The semiconductor device according to the aforementioned [3] or [4], wherein the conductive substrate has a layer formed by laminating at least one layer each containing a metal from Group 6 of the periodic table and a layer containing a metal from Group 11 of the periodic table. Laminated structure. [6] The semiconductor element according to any one of the aforementioned [1] to [5], wherein the weight ratio of the metal of Group 6 of the periodic table in the aforementioned conductive substrate is 0.09 or more. [7] The semiconductor element according to any one of the aforementioned [1] to [6], wherein the aforementioned crystalline oxide semiconductor contains at least one metal selected from the group consisting of aluminum, indium, and gallium. [8] The semiconductor element according to any one of the aforementioned [1] to [7], wherein the aforementioned crystalline oxide semiconductor contains at least gallium. [9] The semiconductor element according to any one of the above [1] to [8], further comprising another electrode layer on the surface of the semiconductor layer facing the surface on which the electrode layer is stacked. [10] The semiconductor element according to any one of the aforementioned [1] to [9], which is a power element. [11] A semiconductor device comprising a semiconductor element bonded to a lead frame, a circuit board, or a heat dissipation substrate at least by a bonding member, wherein the semiconductor element is the semiconductor according to any one of the aforementioned [1] to [10] element. [12] A power conversion device in which the semiconductor device as described in the aforementioned [11] is used. [13] A control system in which the semiconductor device as described in the aforementioned [11] is used. [Effect of invention]

The semiconductor element of the present invention is excellent in electrical characteristics such as forward characteristics.

The semiconductor element of the present invention includes at least a semiconductor layer containing a crystalline oxide semiconductor as a main component, an electrode layer laminated on the semiconductor layer, and a conductive substrate laminated directly or via other layers on the electrode layer, wherein It is characterized in that the conductive substrate contains molybdenum.

In an embodiment of the present invention, for example, the aforementioned semiconductor element can be suitably manufactured by a manufacturing method including the following steps: (1) after the aforementioned semiconductor layer is directly laminated on an underlying substrate or via other layers, (2) After an electrode layer is formed on the semiconductor layer, (3) the conductive substrate is laminated on the electrode layer via a conductive adhesive as required, and the underlying substrate is removed by conventional means. Hereinafter, the main steps (1) to (3) of manufacturing the aforementioned semiconductor element will be described in detail with reference to the drawings.

In step (1), the aforementioned semiconductor layer is laminated directly or via other layers on the underlying substrate. By the step (1), for example, a layered body as shown in FIG. 1 can be obtained. In the laminate shown in FIG. 1 , a crystalline semiconductor 101 is laminated on a base substrate 108 . In the present invention, the crystalline semiconductor film 101 obtained in the step (1) can be used as the aforementioned semiconductor layer (hereinafter also referred to as "semiconductor film"). Step (1) will be described below.

(underlying substrate) The base substrate is in a plate shape, and is not particularly limited as long as it is a support for the semiconductor film. It can be an insulator substrate, a semiconductor substrate, a metal substrate or a conductive substrate, but the underlying substrate is preferably an insulator substrate, and a substrate with a metal film on the surface is also preferred. Examples of the underlying substrate include an underlying substrate containing as a main component a substrate material having a corundum structure, an underlying substrate containing a substrate material having a β-gallia structure as a main component, and a substrate material having a hexagonal crystal structure as a main component components of the underlying substrate, etc. Here, the "main component" refers to, in terms of atomic ratio, relative to the total composition of the substrate material, preferably including 50% or more of the aforementioned substrate material having a specific crystal structure, more preferably 70% or more, still more preferably 90% above, and may be 100%.

The substrate material is not particularly limited as long as it does not inhibit the purpose of the present invention, and may be a known material. Examples of the substrate material having the corundum structure include, for example, α-Al ₂ O ₃ (sapphire substrate) or α-Ga ₂ O ₃ . More preferred examples include a-plane sapphire substrates and m-plane sapphire substrates. , r-plane sapphire substrate, c-plane sapphire substrate or α-type gallium oxide substrate (a-plane, m-plane or r-plane), etc. The base substrate with the substrate material of β-gallia structure as the main component, for example: β-Ga ₂ O ₃ substrate, or a substrate containing Ga ₂ O ₃ and Al ₂ O ₃ , and Al ₂ O ₃ greater than 0wt% and in Mixed crystal substrates below 60wt%, etc. Moreover, as a base substrate whose main component is the substrate material which has a hexagonal crystal structure, a SiC substrate, a ZnO substrate, a GaN substrate, etc. are mentioned, for example.

The aforementioned semiconductor layer is not particularly limited as long as it contains a crystalline oxide semiconductor as a main component. The crystal structure of the crystalline oxide semiconductor is not particularly limited as long as it does not inhibit the object of the present invention. Examples of the crystal structure of the crystalline oxide semiconductor include a corundum structure, a β-gallia structure, a hexagonal structure (for example, an ε-type structure, etc.), a histogram structure (for example, a κ-type structure, etc.), a cubic structure, or the like. tetragonal structure, etc. In an embodiment of the present invention, the crystalline oxide semiconductor preferably has a corundum structure, a β-gallia structure or a hexagonal crystal structure (eg, an ε-type structure, etc.), more preferably a corundum structure. Examples of the crystalline oxide semiconductor include metal oxides containing one or more metals selected from the group consisting of aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. Wait. In an embodiment of the present invention, the oxide semiconductor preferably contains at least one metal selected from aluminum, indium, and gallium, more preferably at least gallium, and most preferably α-Ga ₂ O ₃ or a mixed crystal thereof. In addition, the "main component" means that the oxide semiconductor having a corundum structure is preferably 50% or more, more preferably 70% or more, more preferably 70% or more with respect to all the components of the semiconductor layer in terms of atomic ratio. 90% or more, and means 100% as well. In addition, the thickness of the said semiconductor layer is not specifically limited, It may be 1 μm or less, and may be 1 μm or more, but in the embodiment of the present invention, it is preferably 1 μm or more. The surface area of the semiconductor layer is not particularly limited, and may be 1 mm ² or more or 1 mm ² or less, but preferably 10 mm ² to 300 cm ² , more preferably 100 mm ² to 100 cm ² . In addition, although the said semiconductor layer is usually a single crystal, it may be a polycrystal. In addition, when the semiconductor layer is a multilayer film including at least a first semiconductor layer and a second semiconductor layer, and when a Schottky electrode is provided on the first semiconductor layer, the carrier density of the first semiconductor layer is lower than that of the second semiconductor layer. Density multilayer films are also preferred. In addition, in this case, the second semiconductor layer usually contains a dopant, and the carrier density of the semiconductor layer can be appropriately set by adjusting the amount of doping.

The aforementioned semiconductor layer preferably contains dopants. The aforementioned dopant is not particularly limited, and may be known in the art. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, and niobium, and p-type dopants such as magnesium, calcium, and zinc. In the embodiment of the present invention, the aforementioned n-type dopant is preferably Sn, Ge or Si. The content of the dopant in the composition of the semiconductor layer is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and most preferably 0.00001 atomic % to 10 atomic %. More specifically, the concentration of the dopant may be generally about 1×10 ¹⁶ /cm ³ to 1×10 ²² /cm ³ , and the concentration of the dopant may be, for example, about 1×10 ¹⁷ /cm ³ the following low concentrations. Furthermore, according to the present invention, the dopant may be contained in a high concentration of about 1×10 ²⁰ /cm ³ or more. In the embodiment of the present invention, the dopant is preferably contained at a carrier concentration of 1×10 ¹⁷ /cm ³ or more.

The aforementioned semiconductor layer can be formed by known means. Examples of means for forming the semiconductor layer include CVD, MOCVD, MOVPE, atomized CVD, atomization/epitaxy, MBE, HVPE, pulse growth, or ALD. In an embodiment of the present invention, the formation method of the aforementioned semiconductor layer is preferably an atomized CVD method or an atomized/epitaxy method. In the aforementioned atomization CVD method or atomization/epitaxy method, for example, using the atomization CVD apparatus shown in FIG. 12, the raw material solution is atomized (atomization step), the droplets are floated, and after the atomization is carried by a carrier gas The obtained atomized droplets are transferred to a substrate (transfer step), and then the atomized droplets are thermally reacted in a film forming chamber, and a semiconductor film containing a crystalline oxide semiconductor as a main component is laminated on the substrate (film-forming step), whereby the aforementioned semiconductor layer is formed.

(Atomization step) In the atomization step, the aforementioned raw material solution is atomized. The atomization means of the raw material solution is not particularly limited as long as the raw material solution can be atomized, and may be a conventional means, and in an embodiment of the present invention, an atomization means using ultrasonic waves is preferred. The atomized droplets obtained by using ultrasonic waves have zero initial velocity and can float in the air, so it is better. For example, instead of being blown by a spray, it is a mist that can be floated in space and transported as a gas, so it is not It is very suitable for damage caused by impact energy. The droplet size is not particularly limited, and may be about several millimeters, but is preferably 50 μm or less, and more preferably 100 nm to 10 μm.

(raw material solution) The raw material solution is not particularly limited as long as it can be atomized or dropletized and contains a raw material capable of forming a semiconductor film, and may be an inorganic material or an organic material. In an embodiment of the present invention, the aforementioned raw material is preferably a metal or a metal compound, more preferably one selected from the group consisting of aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt and iridium or 2 or more metals.

In an embodiment of the present invention, as the raw material solution, one obtained by dissolving or dispersing the metal in an organic solvent or water in the form of a complex or a salt can be suitably used. As a form of a complex, an acetylacetone complex, a carbonyl complex, an ammonia complex, a hydride complex, etc. are mentioned, for example. Examples of the salt form include organic metal salts (eg, metal acetates, metal oxalates, metal citrates, etc.), sulfide metal salts, nitrated metal salts, phosphated metal salts, and halogenated metal salts (eg, chlorine salts) metal bromide, metal bromide, metal iodide, etc.) and the like.

Moreover, it is preferable to mix additives, such as a hydrohalic acid or an oxidizing agent, in the said raw material solution. Examples of the above-mentioned hydrohalic acid include hydrobromic acid, hydrochloric acid, and hydroiodic acid, and among them, hydrobromic acid or hydroiodic acid is preferred because the generation of abnormal crystal grains can be suppressed more efficiently. Examples of the oxidizing agent include hydrogen peroxide (H ₂ O ₂ ), sodium peroxide (Na ₂ O ₂ ), barium peroxide (BaO ₂ ), and benzyl peroxide (C ₆ H ₅ CO) ₂ O _2nd class peroxides, organic peroxides such as hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, peracetic acid or nitrobenzene, etc.

The aforementioned raw material solution may also contain a dopant. Doping can be favorably performed by making the raw material solution contain the dopant. The aforementioned dopant is not particularly limited as long as it does not inhibit the purpose of the present invention. Examples of the above-mentioned dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or Mg, H, Li, Na, K, Rb, Cs, Fr, Be, p-type dopants such as Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, or P, etc. The content of the aforementioned dopant can be appropriately set by using a calibration curve, which represents the relationship between the concentration of the dopant in the raw material and the expected carrier density.

The solvent of the raw material solution is not particularly limited, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In an embodiment of the present invention, the aforementioned solvent is preferably water, more preferably water or a mixed solvent of water and alcohol.

(conveying procedure) In the conveying step, the atomized droplets are conveyed into the film forming chamber with a carrier gas. The carrier gas is not particularly limited as long as it does not inhibit the object of the present invention, and preferable examples include inert gases such as oxygen, ozone, nitrogen, and argon, and reducing gases such as hydrogen and synthesis gas. In addition, the type of carrier gas may be one type or two types, and a dilution gas (for example, a 10-fold dilution gas, etc.) whose flow rate is reduced may be further used as the second carrier gas. In addition, the supply location of the carrier gas may be not only one location, but also two or more locations. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L/min, more preferably 1 to 10 L/min. In the case of the dilution gas, the flow rate of the dilution gas is preferably 0.001 to 2 L/min, more preferably 0.1 to 1 L/min.

(film formation step) In the film-forming step, the semiconductor film is formed on the substrate by thermally reacting the atomized droplets in the film-forming chamber. The thermal reaction is not particularly limited as long as the atomized liquid droplets are reacted with heat, and the reaction conditions and the like are not particularly limited as long as the object of the present invention is not inhibited. In this step, the thermal reaction is usually carried out at a temperature higher than the evaporation temperature of the solvent, preferably not too high (for example, 1000°C) or lower, more preferably 650°C or lower, and most preferably 300°C to 650°C. In addition, the thermal reaction may be carried out in any environment of vacuum, non-oxygen environment (for example, inert gas environment, etc.), reducing gas environment, and oxygen environment, as long as the object of the present invention is not hindered. The best system is carried out in an inert gas environment or an oxygen environment. In addition, it may be carried out under any conditions of atmospheric pressure, pressurized and reduced pressure, but in the present invention, it is preferably carried out under atmospheric pressure. In addition, the film thickness of the aforementioned semiconductor film can be set by adjusting the film formation time.

In an embodiment of the present invention, an annealing treatment may also be performed after the aforementioned film forming step. The annealing treatment temperature is not particularly limited as long as the object of the present invention is not inhibited, but is usually 300°C to 650°C, preferably 350°C to 550°C. Moreover, the processing time of an annealing is 1 minute - 48 hours normally, Preferably it is 10 minutes - 24 hours, More preferably, it is 30 minutes - 12 hours. In addition, the annealing treatment can be performed in any environment as long as the object of the present invention is not inhibited. It can be in a non-oxygen environment or in an oxygen environment. As a non-oxygen environment, for example, an inert gas environment (such as a nitrogen environment) or a reducing gas environment can be mentioned, but in the embodiment of the present invention, it is preferably an inert gas environment, more preferably nitrogen in environment.

In addition, in an embodiment of the present invention, the semiconductor film may be directly provided on the underlying substrate, or the semiconductor film may be provided via other layers such as a stress relaxation layer (eg, a buffer layer, an ELO layer, etc.), a peeling sacrificial layer, etc. . The method for forming each layer is not particularly limited, and may be a conventional method, and in an embodiment of the present invention, the atomized CVD method is preferred.

In step (2), an electrode layer 105b is formed on the aforementioned semiconductor layer 101 . By the step (2), for example, a layered body as shown in FIG. 2 can be obtained. The build-up system of FIG. 2 is composed of a base substrate 108, a semiconductor layer 101, and an electrode layer 105b.

The aforementioned electrode layer is not particularly limited as long as it has conductivity and does not inhibit the purpose of the present invention. The constituent material of the electrode layer may be a conductive inorganic material or a conductive organic material. In the embodiment of the present invention, the material of the aforementioned electrode is preferably metal. Preferable examples of the aforementioned metal include at least one metal selected from Groups 4 to 10 of the periodic table, and the like. As a metal of group 4 of the periodic table, titanium (Ti), zirconium (Zr), hafnium (Hf), etc. are mentioned, for example. As a metal of Group 5 of the periodic table, vanadium (V), niobium (Nb), tantalum (Ta), etc. are mentioned, for example. Examples of metals in Group 6 of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W). As a metal of Group 7 of the periodic table, manganese (Mn), onium (Tc), rhenium (Re), etc. are mentioned, for example. As a metal of Group 8 of the periodic table, iron (Fe), ruthenium (Ru), osmium (Os), etc. are mentioned, for example. Examples of metals in Group 9 of the periodic table include cobalt (Co), rhodium (Rh), iridium (Ir), and the like. As a metal of group 10 of the periodic table, nickel (Ni), palladium (Pd), platinum (Pt), etc. are mentioned, for example. In an embodiment of the present invention, the electrode layer preferably contains at least one metal selected from Group 4 and Group 9 of the periodic table, and more preferably contains a metal of Group 9 of the periodic table. The thickness of the electrode layer is not particularly limited, but is preferably 0.1 nm to 10 μm, more preferably 5 nm to 500 nm, and most preferably 10 nm to 200 nm. Moreover, in the embodiment of the present invention, the electrode layer may be constituted by two or more layers having mutually different compositions.

The formation means of the said electrode layer is not specifically limited, It can be a conventional means. As a formation means of the said electrode layer or the said other electrode layer, a dry method, a wet method, etc. are mentioned specifically, for example. As a dry method, sputtering, vacuum vapor deposition, CVD, etc. are mentioned, for example. As a wet method, a screen printing, die coating, etc. are mentioned, for example.

In step (3), the conductive substrate may be laminated on the electrode layer via a conductive adhesive as required, and the underlying substrate may be removed by conventional means. By the step (3), for example, a layered body as shown in FIG. 3 can be obtained. In the laminate shown in FIG. 3, the electrode layer 105b is bonded to the conductive substrate 107 via the conductive adhesive layer 106, and the semiconductor layer 101 is laminated on the electrode layer 105b. As a method of removing the above-mentioned base substrate, for example, a method of removing it by applying a mechanical impact, a method of removing it by heating it by thermal stress, a method of removing it by applying vibrations such as ultrasonic waves, and etching it. A method of removing it, a method of removing it by grinding, a method of removing it by heat treatment after plasma implantation by a smart cut method, a method of removing it by a laser lift-off method, etc. method of combining, etc.

The conductive adhesive layer is not particularly limited as long as the electrode layer can be bonded to the conductive substrate. Examples of the constituent material of the conductive adhesive layer include those containing at least one metal selected from the group consisting of Al, Au, Pt, Ag, Ti, Ni, Bi, Cu, Ga, In, Pb, Sn, and Zn, and the like. Metal oxides, eutectic materials (eg, Au-Sn, etc.), etc. In an embodiment of the present invention, the conductive adhesive layer preferably has a porous structure. Further, when the conductive adhesive layer has a porous structure, the conductive adhesive layer preferably contains metal particles, and more preferably contains metal particles selected from the group consisting of Au, Pt, Ag, Ti, Ni, Bi, Cu, Ga, and In The metal particles of at least one metal among Pb, Sn, and Zn are preferably metal particles containing a noble metal. Examples of the noble metal include at least one metal selected from Au, Ag, Pt, Pd, Rh, Ir, Ru, and Os. In an embodiment of the present invention, the noble metal is preferably Ag. Moreover, in the embodiment of this invention, it is preferable that the said electroconductive adhesive layer contains a metal particle sintered body, and it is more preferable that it contains a silver particle sintered body. By using such a preferable conductive adhesive layer, the adhesiveness with the electrode layer and the conductive substrate can be further improved without impairing the electrical properties of the semiconductor element. Moreover, the said electroconductive adhesive layer may be a single layer, and may be a multilayer. Moreover, the thickness of the said electroconductive adhesive layer is not specifically limited unless the objective of this invention is impaired, Preferably it is 10 nm - 200 micrometers, More preferably, it is 30 nm - 50 micrometers. Moreover, the said electroconductive adhesive layer is amorphous normally, and may contain auxiliary components, such as a crystal. In addition, the formation means of the said electroconductive adhesive layer is not specifically limited, A conventional coating means may be sufficient.

The conductive substrate is not particularly limited as long as it has conductivity, can support the semiconductor layer, and contains a metal of Group 6 of the periodic table. As a periodic table Group 6 metal, chromium (Cr), molybdenum (Mo), tungsten (W), etc. are mentioned, for example. In an embodiment of the present invention, the metal of Group 6 of the periodic table is preferably molybdenum (Mo). The content of the periodic table Group 6 metal in the conductive substrate is not particularly limited as long as the object of the present invention is not impaired. In the embodiment of the present invention, it is preferable that the weight ratio of the metal of Group 6 of the periodic table in the conductive substrate is 0.09 or more, which can improve the forward characteristic and further reduce the warpage of the entire semiconductor element. Moreover, in the embodiment of the present invention, the conductive substrate preferably contains two or more kinds of metals, and as a combination of such two or more kinds of metals, for example, copper (Cu)-tungsten (W), copper (Cu)-molybdenum (Mo), molybdenum (Mo)-lanthanum (La), molybdenum (Mo)-yttrium (Y), molybdenum (Mo)-rhenium (Re), molybdenum (Mo)-tungsten (W), molybdenum (Mo)-niobium (Nb), molybdenum (Mo)-tantalum (Ta), etc. In an embodiment of the present invention, it is further preferable that the conductive substrate contains a metal of Group 11 of the periodic table in addition to molybdenum. As a periodic table group 11 metal, copper (Cu), silver (Ag), or gold (Au) etc. are mentioned, for example. In an embodiment of the present invention, the metal of Group 11 of the periodic table is preferably copper. In addition, in the embodiment of the present invention, when the conductive substrate contains molybdenum and copper, it is preferable to use, as the conductive substrate, a Cu-Mo composite substrate obtained by an impregnation method in which a compressed molybdenum powder is impregnated with copper. (Hereinafter, it is also simply referred to as "Cu-Mo composite substrate"). Moreover, in the embodiment of this invention, the said electroconductive board|substrate may have a metal film on the surface. Examples of the constituent metal of the metal film include 1 selected from the group consisting of gallium, iron, indium, aluminum, vanadium, titanium, chromium, rhodium, nickel, cobalt, zinc, magnesium, calcium, silicon, yttrium, strontium, and barium. one or more metals, etc.

Furthermore, in the embodiment of the present invention, the conductive substrate preferably has a layered structure in which a layer containing molybdenum and a layer containing a metal of Group 11 of the periodic table are laminated at least one each, more preferably a layer containing molybdenum The layer and the layer containing the metal of Group 11 of the periodic table are alternately laminated at least one layer each. In addition, in this case, the thickness of each layer is preferably 5 μm or more, and more preferably 10 μm or more. By making the conductive substrate to have such a preferable configuration, the forward characteristic of the semiconductor element can be improved and the thermal resistance of the semiconductor element can be reduced more favorably. In addition, in an embodiment of the present invention, when the conductive substrate has the above-mentioned laminate structure, the uppermost layer and/or the lowermost layer in the laminate structure includes a metal of Group 11 of the periodic table, which can further improve the heat dissipation of the semiconductor element. and mountability, it is preferable that the uppermost layer and the lowermost layer contain metals from Group 11 of the periodic table. In addition, in the case where the uppermost layer and/or the lowermost layer of the above-mentioned laminated structure contains a metal of Group 11 of the periodic table, the bonding of the electrode layer and the conductive substrate can be performed without using the conductive adhesive layer, which can be more effective. Therefore, the warpage and thermal resistance of the aforementioned semiconductor device can be improved. That is, for example, the copper-containing layer located on the outermost surface of the electrode layer on the side of the conductive substrate and the copper-containing layer located on the outermost surface of the electrode layer in the laminate structure of the conductive substrate are diffusion bonded, thereby preventing Using the above-mentioned conductive adhesive layer, the above-mentioned electrode layer and the above-mentioned conductive substrate can be joined in an industrially advantageous manner. In addition, the thickness of the conductive substrate is not particularly limited, but 200 μm or less is preferable, and 100 μm or less is more preferable because better heat dissipation can be imparted without impairing the electrical properties of the semiconductor element. In addition, the area of the conductive substrate is not particularly limited, and in the embodiment of the present invention, it is preferably substantially the same as the area of the aforementioned semiconductor layer. In addition, the term "substantially the same" also includes, for example, the case where the area of the conductive substrate is the same as the area of the semiconductor layer, and also includes that the ratio of the area of the conductive substrate to the area of the semiconductor layer is in the range of 0.9 to 1.4 By.

In an embodiment of the present invention, after step (3), the crystals of the crystalline semiconductor film may be re-grown, and different semiconductor layers, other electrode layers, etc. may be provided on the crystalline semiconductor film.

In the embodiment of the present invention, it is preferable to further include another electrode layer on the surface of the semiconductor layer facing the surface on which the electrode layer is stacked. In this way, by forming a laminated structure in which the conductive substrate, the conductive adhesive layer, the electrode layer, the semiconductor layer, and the other electrode layers are laminated in this order, a current can flow in the thickness direction of the semiconductor layer as a The vertical element makes the forward characteristic of the aforementioned semiconductor element more excellent. The other electrode layers described above are not particularly limited as long as they have conductivity and do not impair the purpose of the present invention. The constituent materials of the other electrode layers may be conductive inorganic materials or conductive organic materials. In the embodiment of the present invention, the materials of the other electrodes are preferably metals. As said metal, at least 1 sort(s) of metal etc. chosen from group 8 - group 13 of a periodic table are mentioned suitably, for example. Examples of the metals of Groups 8 to 10 of the periodic table include the metals exemplified as the metals of Groups 8 to 10 of the periodic table in the description of the aforementioned electrode layer. As a periodic table group 11 metal, copper (Cu), silver (Ag), gold (Au), etc. are mentioned, for example. As a metal of Group 12 of the periodic table, zinc (ZN), cadmium (Cd), etc. are mentioned, for example. Moreover, as a metal of Group 13 of the periodic table, aluminum (Al), gallium (Ga), indium (In), etc. are mentioned, for example. In an embodiment of the present invention, the aforementioned other electrode layer preferably comprises at least one metal selected from metals of Group 11 and Group 13 of the periodic table, more preferably comprises at least one selected from silver, copper, gold and aluminum a metal. The thickness of the other electrode layers is not particularly limited, but is preferably 1 nm to 500 μm, more preferably 10 nm to 100 μm, and most preferably 0.5 μm to 10 μm.

The formation means of the other electrode layers described above is not particularly limited, and may be conventional means. As a formation means of the said electrode layer or the said other electrode layer, a dry method, a wet method, etc. are mentioned specifically, for example. As a dry method, sputtering, vacuum vapor deposition, CVD, etc. are mentioned, for example. As a wet method, a screen printing, die coating, etc. are mentioned, for example.

The semiconductor element of the present invention can be used as various semiconductor elements, especially as a power element. In addition, semiconductor elements can be classified into: horizontal elements (horizontal devices) in which electrodes are formed on one side of the semiconductor layer, and current flows in the semiconductor layer in a direction perpendicular to the film thickness direction; and vertical elements (vertical devices). ), electrodes are provided on both sides of the front surface and the back surface of the semiconductor layer, respectively, and current flows in the thickness direction of the semiconductor layer. In the embodiment of the present invention, it is suitable to use the semiconductor element in both a horizontal device and a vertical device, but among them, it is preferably used in a vertical device. Examples of the aforementioned semiconductor elements include Schottky barrier diodes (SBDs), metal semiconductor field effect transistors (MESFETs), high electron mobility transistors (HEMTs), and metal oxide semiconductor field effect transistors (MOSFETs). ), Static Induction Transistor (SIT), Junction Field Effect Transistor (JFET), Insulated Gate Bipolar Transistor (IGBT) or Light Emitting Diode, etc. In an embodiment of the present invention, the aforementioned semiconductor element is preferably SBD, MOSFET, SIT, JFET or IGBT, more preferably SBD, MOSFET or SIT, and most preferably SBD.

Hereinafter, preferred examples of the aforementioned semiconductor elements will be described with reference to the drawings, but the present invention is not limited to these embodiments. In addition, the semiconductor elements exemplified below may further contain other layers (for example, an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers, etc.), as long as the object of the present invention is not impaired. A buffer layer and the like may also be appropriately omitted.

(SBD) FIG. 4 shows an example of a Schottky barrier diode (SBD) of the present invention. The SBD of FIG. 4 includes an n- type semiconductor layer 101a, an n+ type semiconductor layer 101b, a conductive adhesive layer 106, a conductive substrate 107, a Schottky electrode 105a, and an ohmic electrode 105b.

The materials of the Schottky electrode and the ohmic electrode can be known electrode materials. As the aforementioned electrode materials, for example, Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, Metals such as V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag or their alloys, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc indium oxide ( Metal oxide conductive films such as IZO), organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, or mixtures of these.

The formation of the Schottky electrode and the ohmic electrode can be performed by conventional means such as vacuum deposition method or sputtering method, for example. More specifically, for example, in the case of forming a Schottky electrode, it can be carried out as follows: a layer composed of Mo and a layer composed of Al are laminated, and then a layer composed of Mo is formed by photolithography. and patterning of layers composed of Al.

In an embodiment of the present invention, a conductive substrate containing a metal of Group 6 of the periodic table is used as the aforementioned conductive substrate 107 . In addition, in the embodiment of the present invention, it is preferable to use molybdenum and a conductive substrate containing metals of Group 11 of the periodic table, more preferably to use a conductive substrate containing molybdenum and copper, and still more preferably to use a molybdenum-containing layer and A conductive substrate composed of a laminated structure in which at least one copper-containing layer is laminated. By using the conductive substrate with such a preferred configuration, on the one hand, the forward characteristic of the semiconductor element can be improved, and on the other hand, the thermal resistance of the entire semiconductor element can be further reduced, which is preferable. A preferred aspect of the aforementioned conductive substrate is shown in FIG. 23 . FIG. 23 shows a conductive substrate (hereinafter also referred to as a “Cu—Mo laminate substrate”) having a laminate structure in which at least one molybdenum-containing layer and a copper-containing layer are laminated, a first metal layer 107a, a third metal layer 107c and the fifth metal layer 107e are made of copper, and the second metal layer 107b and the fourth metal layer 107d are made of molybdenum. Using a Si substrate, a Cu-Mo composite substrate (70% by mass of Mo, 30% by mass of Cu) substrate, and a Cu-Mo laminated substrate as conductive substrates, the structure based on the SBD shown in Fig. 4 was heated. resistance simulation. In addition, the thicknesses of the conductive substrates were all 100 μm. The results for the case where the conductive substrate is a Si substrate are shown in FIG. 20 , and the results for the case where the conductive substrate is a Cu-Mo composite substrate (the content of Mo is 70% by mass, and the content of Cu is 30% by mass) are shown in FIG. 21 . The case where the substrate is a Cu-Mo laminated substrate is shown in FIG. 22 . From the simulation results, it can be seen that the thermal resistance of the semiconductor element is lower when a Cu-Mo composite substrate or a Cu-Mo laminate substrate is used as the conductive substrate than when a Si substrate is used as the conductive substrate. In addition, it was found that the effect of reducing the thermal resistance was four times or more in the case of using the Cu-Mo laminated substrate compared to the case of using the Cu-Mo composite substrate. From the results, it was found that the use of oxide semiconductors (eg, gallium oxide, etc.) can be further improved by using, as a conductive substrate, a substrate in which at least one layer containing a metal of Group 11 of the periodic table and a molybdenum-containing layer are laminated. Thermal resistance of semiconductor components.

In addition, when the Cu-Mo laminated substrate shown in FIG. 23 was used as the conductive substrate, and the molybdenum content in the conductive substrate was 9%, 24%, and 30% by weight to produce the semiconductor element , the warpage amount of the semiconductor element is measured. The results are shown in Figure 23. As is clear from FIGS. 23 and 24 , the amount of warpage of the entire semiconductor element can be reduced by adjusting the molybdenum content in the conductive substrate. In addition, the content of molybdenum can be appropriately adjusted by the thickness of the semiconductor layer in the aforementioned semiconductor element, the thickness of the layer containing the metal of Group 11 of the periodic table, and the like. In this way, the warpage of the semiconductor element can be reduced more effectively by using the conductive substrate containing the metal of Group 6 of the periodic table and the metal of Group 11 of the periodic table. Moreover, the warpage of the semiconductor element can be reduced more favorably by using the laminated substrate as shown in FIG. 23 and adjusting the thickness and material of each layer.

FIG. 5 shows an example of the Schottky Barrier Diode (SBD) of the present invention. The SBD of FIG. 5 further includes an insulator layer 104 in addition to the configuration of the SBD of FIG. 4 . More specifically, an n- type semiconductor layer 101a, an n+ type semiconductor layer 101b, a conductive adhesive layer 106, a conductive substrate 107, a Schottky electrode 105a, an ohmic electrode 105b, and an insulator layer 104 are provided.

Examples of the material of the insulator layer 104 include GaO, AlGaO, InAlGaO, AlInZnGaO ₄ , AlN, Hf ₂ O ₃ , SiN, SiON, Al ₂ O ₃ , MgO, GdO, SiO ₂ , or Si ₃ N ₄ . In the embodiment of the present invention, it is preferable to have a corundum structure. By using an insulator having a corundum structure for the insulator layer, the function of semiconductor properties in the interface can be better exhibited. The insulator layer 104 is provided between the n-type semiconductor layer 101 and the Schottky electrode 105a. The insulator layer can be formed, for example, by conventional means such as sputtering, vacuum deposition, or CVD.

As for the formation and material of the Schottky electrode or the ohmic electrode, as in the case of the SBD shown in FIG. 4 described above, conventional methods such as sputtering, vacuum evaporation, pressure bonding, and CVD can be used. Metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag or Such alloys, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, or the like An electrode composed of a mixture of etc.

The SBD of FIG. 5 has better insulating properties than the SBD of FIG. 4, and has higher current controllability.

(MOSFET) An example of the case where the semiconductor element of the present invention is a MOSFET is shown in FIG. 6 . The MOSFET of FIG. 6 is a trench MOSFET, and includes an n- type semiconductor layer 131a, n+ type semiconductor layers 131b and 131c, a conductive adhesive layer 136, a conductive substrate 137, a gate insulating film 134, a gate electrode 135a, and a source electrode 135b and drain electrode 135c.

A conductive adhesive layer 136 having a thickness of, for example, 50 nm to 50 μm is formed on the conductive substrate 137 . In addition, a drain electrode 135c is formed on the conductive adhesive layer 136 . In addition, an n+ type semiconductor layer 131b having a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 135c, and an n- type semiconductor layer 131a of, for example, a thickness of 100 nm to 100 μm is formed on the n+ type semiconductor layer 131b. Then, an n+ type semiconductor layer 131c is further formed on the aforementioned n− type semiconductor layer 131a, and an active electrode 135b is formed on the aforementioned n+ type semiconductor layer 131c.

Further, a plurality of trenches are formed in the n-type semiconductor layer 131a and the n+-type semiconductor layer 131c penetrating the n+-type semiconductor layer 131c and reaching the depth in the middle of the n-type semiconductor layer 131a. In the trench, for example, an electrode 135a is formed with the gate insulating film 134 having a thickness of 10 nm to 1 μm interposed therebetween.

In the ON state of the MOSFET of FIG. 6, a voltage is applied between the source electrode 135b and the drain electrode 135c, and if a positive voltage is applied to the gate electrode 135a with respect to the source electrode 135b, the n-type semiconductor layer 131a has a A channel layer is formed on the side, and electrons are injected into the aforementioned n-type semiconductor layer, which is then turned on. In the OFF state, when the voltage of the gate electrode is set to 0 V, the channel layer disappears, and the n- type semiconductor layer 131a is in a state of being filled with the depletion layer, and thus is turned off.

FIG. 7 shows a portion of the manufacturing steps of the MOSFET of FIG. 6 . For example, using the laminate shown in FIG. 7(a), an etching mask is provided in a predetermined region of the n- type semiconductor layer 131a and the n+ type semiconductor layer 131c, and the above-mentioned etching mask is used as a mask, and then the reactive ion etching method is used. Then, anisotropic etching is performed, and as shown in FIG. 7( b ), a trench having a depth extending from the surface of the n+ type semiconductor layer 131c to the middle of the n− type semiconductor layer 131a is formed. Next, as shown in FIG. 7( c ), conventional means such as thermal oxidation, vacuum evaporation, sputtering, and CVD are used to form gate insulation with a thickness of 50 nm to 1 μm, for example, on the side and bottom surfaces of the trenches. After the film 134 is formed, a gate electrode material such as polysilicon is formed in the trench to a thickness equal to or less than the thickness of the n-type semiconductor layer by using a CVD method, a vacuum deposition method, a sputtering method, or the like.

Then, a source electrode 135b is formed on the n+ type semiconductor layer 131c, and a drain electrode 135c is formed on the n+ type semiconductor layer 131b by conventional means such as vacuum evaporation, sputtering, CVD, etc., thereby manufacturing a power MOSFET. In addition, the electrode materials of the source electrode and the drain electrode can be known electrode materials, respectively. As the aforementioned electrode materials, for example, Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Metals such as Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag or their alloys, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), oxide Metal oxide conductive films such as zinc indium (IZO), organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, or mixtures of these.

The MOSFET thus obtained has better withstand voltage than the conventional trench MOSFET. In addition, although FIG. 6 shows an example of a trench-type vertical MOSFET, the embodiment of the present invention is not limited to this, and can be applied to various types of MOSFETs. For example, the series resistance can also be reduced by excavating the trench in FIG. 6 to the bottom surface of the n-type semiconductor layer 131a.

(SIT) FIG. 8 shows an example of the case where the semiconductor element of the present invention is a SIT. The SIT of FIG. 8 includes an n- type semiconductor layer 141a, n+ type semiconductor layers 141b and 141c, a conductive adhesive layer 146, a conductive substrate 147, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.

A conductive support layer 147 having a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 145 c , and a conductive adhesive layer 146 of a thickness of, for example, 50 nm to 50 μm is formed on the conductive support layer 147 . Further, an n+ type semiconductor layer 141b having a thickness of, for example, 100 nm to 100 μm is formed on the conductive adhesive layer 146, and an n- type semiconductor layer 141a having a thickness of, for example, 100 nm to 100 μm is formed on the n+ type semiconductor layer 141b. Then, an n+ type semiconductor layer 141c is further formed on the aforementioned n- type semiconductor layer 141a, and an active electrode 145b is formed on the aforementioned n+ type semiconductor layer 141c.

In addition, a plurality of trenches are formed in the n- type semiconductor layer 141a penetrating the n+ type semiconductor layer 131c and the depth reaches the middle of the n- semiconductor layer 131a. A gate electrode 145a is formed on the n-type semiconductor layer in the aforementioned trench. In the ON state of the SIT shown in FIG. 8, a voltage is applied between the source electrode 145b and the drain electrode 145c, and if a positive voltage is applied to the gate electrode 145a with respect to the source electrode 145b, the n-type semiconductor layer 141a is formed in the n-type semiconductor layer 141a. A channel layer is formed, electrons are injected into the aforementioned n-type semiconductor layer, and thus turned on. In the OFF state, when the voltage of the gate electrode is set to 0 V, the channel layer disappears, and the n- type semiconductor layer is in a state of being filled with the depletion layer, and thus is turned off.

In an embodiment of the present invention, the SIT of FIG. 8 can be fabricated in the same manner as the MOSFET of FIG. 7 . More specifically, for example, an etching mask is provided on predetermined regions of the n- type semiconductor layer 141a and the n+ type semiconductor layer 141c, and the etching mask is used as a mask, for example, by reactive ion etching or the like. The tropic etching is used to form a trench whose depth reaches from the surface of the n+-type semiconductor layer 141c to the n-type semiconductor layer. Next, a gate electrode material such as polysilicon is formed in the trenches by a CVD method, a vacuum deposition method, a sputtering method, or the like to a thickness of the n- type semiconductor layer or less. Further, the SIT can be fabricated by forming the source electrode 145b on the n+ type semiconductor layer 141c and forming the drain electrode 145c on the n+ type semiconductor layer 141b by conventional means such as vacuum evaporation, sputtering, and CVD. In addition, the electrode materials of the source electrode and the drain electrode can be known electrode materials, respectively. Examples of the aforementioned electrode materials include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au , Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag and other metals or their alloys, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), Metal oxide conductive films such as indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, or mixtures thereof, and the like.

In the above-mentioned example, although the example in which the p-type semiconductor is not used is shown, the embodiment of the present invention is not limited to this, and a p-type semiconductor may also be used. Examples using p-type semiconductors are shown in FIGS. 9 to 11 . These semiconductor elements can be manufactured in the same manner as in the above-mentioned examples. In addition, the p-type semiconductor may be the same material as the n-type semiconductor and include a p-type dopant, or may be a different p-type semiconductor.

The aforementioned semiconductor elements are particularly useful as power elements. Examples of the aforementioned semiconductor elements include diodes (eg, PN diodes, Schottky barrier diodes, junction barrier Schottky diodes, etc.), transistors (eg, MESFETs, etc.), among which more Preferably it is a diode, more preferably a Schottky barrier diode (SBD).

In addition to the above-mentioned matters, the semiconductor element according to the embodiment of the present invention can be suitably used as a semiconductor device by bonding to a lead frame, a circuit board, a heat-dissipating board, etc. by a bonding member by a general method, and can be suitably used in particular as a semiconductor device. Further, a power module, an inverter, or a converter can be suitably used in, for example, a semiconductor system using a power supply device. A preferred example of the aforementioned semiconductor device is shown in FIG. 15 . In the semiconductor device of FIG. 15 , both sides of the semiconductor element 500 are bonded to a lead frame, a circuit board, or a heat dissipation board 502 by solder 501 , respectively. With this configuration, a semiconductor device having excellent heat dissipation properties can be used. In addition, in the embodiment of the present invention, it is preferable to seal the periphery of the bonding member such as solder with resin.

The above-described semiconductor element or semiconductor device of the present invention can be applied to a power conversion device such as an inverter or a converter in order to exhibit the above-described functions. More specifically, it can be used as a diode built in an inverter or a converter, or as a switching element as a thyristor, power transistor, IGBT (Insulated Gate Bipolar Transistor), MOSFET (Metal-Oxide) -Semiconductor Field Effect Transistor) etc. FIG. 16 is a block diagram showing an example of a control system of a semiconductor element or semiconductor device to which the embodiment of the present invention is applied. FIG. 17 is a circuit diagram of the same control system, which is particularly suitable for a control system mounted on an electric vehicle.

As shown in FIG. 16 , the control system 500 includes a battery (power source) 501, a boost converter 502, a step-down converter 503, an inverter 504, a motor (object to be driven) 505, and a drive control unit 506, which are mounted on an electric motor car. The battery 501 is composed of a storage battery such as a nickel-metal hydride battery or a lithium-ion battery, and stores electric power by charging at a charging station or regenerative energy during deceleration, etc., and can output the DC necessary for the operation of the electric vehicle and the operation of the electrical system. Voltage. The boost converter 502, such as a voltage conversion device equipped with a chopper circuit, boosts the DC voltage such as 200V supplied from the battery 501 to, for example, 650V by the switching operation of the chopper circuit, and can be output to the operation of the motor, etc. system. The step-down converter 503 is also a voltage conversion device equipped with a chopper circuit, but it steps down the DC voltage of, for example, 200V supplied from the battery 501 to, for example, about 12V. Electrical systems such as in-vehicle electrical equipment.

The inverter 504 converts the DC voltage supplied from the boost converter 502 into a three-phase AC voltage by switching, and outputs it to the motor 505 . The motor 505 constitutes a three-phase AC motor of the operating system of the electric vehicle, and is rotationally driven by the three-phase AC voltage output from the inverter 504, and then transmits its rotational driving force through a transmission (not shown in the figure) or the like. to the wheels of an electric vehicle.

On the other hand, various sensors not shown in the figure are used to measure the actual measurement values such as the number of revolutions of the wheels, the torque, and the pedaling amount (acceleration amount) of the accelerator from the running electric vehicle, and these measurement signals are input to the drive control unit 506 . At the same time, the output voltage value of the inverter 504 is also input to the drive control unit 506 . The drive control unit 506 has the function of a controller including an arithmetic unit such as a central processing unit (CPU, Central Processing Unit) and a data storage unit such as a memory, and uses the input measurement signal to generate a control signal, which is output to the feedback signal as a feedback signal. The switch 504 is used to control the switch operation with the switch element. In this way, the AC voltage given to the motor 505 by the inverter 504 is instantly corrected, so that the operation control of the electric vehicle can be executed correctly, and the safe and comfortable operation of the electric vehicle can be realized. In addition, by giving the feedback signal from the drive control unit 506 to the boost converter 502, the voltage output to the inverter 504 can also be controlled.

FIG. 17 shows the circuit configuration in which the step-down converter 503 in FIG. 16 is removed, that is, only the circuit configuration for driving the motor 505 is shown. As shown in the figure, the semiconductor device of the present invention is used in the boost converter 502 and the inverter 504 as a Schottky barrier diode, for example, and is applied to switching control. The boost converter 502 is incorporated in a chopper circuit for chop control, and the inverter 504 is incorporated in a switch circuit including IGBTs for switch control. In addition, by interposing an inductor (coil, etc.) in the output of the battery 501, current stabilization is achieved, and a capacitor (electrolyte) is provided between the battery 501, the boost converter 502, and the inverter 504, respectively. capacitor (electrolytic condenser, etc.), thereby achieving voltage stabilization.

17, the drive control unit 506 includes a calculation unit 507 composed of a central processing unit (CPU) and a storage unit 508 composed of a non-volatile memory. The signal input to the drive control unit 506 is sent to the calculation unit 507 to perform necessary calculation, thereby generating feedback signals for each semiconductor element. The storage unit 508 temporarily holds the calculation results of the calculation unit 507 , or stores physical constants and functions required for drive control in a table format and outputs them to the calculation unit 507 as appropriate. The calculation unit 507 and the storage unit 508 may have conventional structures, and the processing capability and the like may be arbitrarily selected.

As shown in FIGS. 16 and 17 , in the control system 500 , in the switching operation of the boost converter 502 , the buck converter 503 , and the inverter 504 , thyristors and power transistors are used as diodes or switching elements. , IGBT, MOSFET, etc. By using gallium oxide (Ga ₂ O ₃ ), especially corundum-type gallium oxide (α-Ga ₂ O ₃ ), as the material of these semiconductor elements, switching characteristics can be greatly improved. Furthermore, by applying the semiconductor device or the like of the present invention, excellent switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be achieved. That is, the boost converter 502 , the buck converter 503 , and the inverter 504 can all expect the effects of the present invention, and any one of them or a combination of any two or more, or the type that also includes the drive control unit 506 In either state, the effects of the present invention can be expected. In addition, the above-mentioned control system 500 can not only apply the semiconductor device of the present invention to a control system of an electric vehicle, but also can be applied to step-up/step-down power from a DC power supply, or convert power from DC to become a Control systems for all purposes such as AC. In addition, a power source such as a solar cell may be used as the battery.

FIG. 18 is a block diagram showing another example of a control system for a semiconductor element or semiconductor device to which an embodiment of the present invention can be applied, and FIG. 19 is a circuit diagram of the same control system, which is suitable to be installed in a control system that operates with power from an AC power source. control system of basic equipment or home appliances.

As shown in FIG. 18 , the control system 600 receives electric power supplied from, for example, an external three-phase AC power supply (power supply) 601, and includes an AC/DC converter 602, an inverter 604, a motor (driving object) 605, The drive control unit 606 can be mounted on various devices (described later). The three-phase AC power source 601 is, for example, a power generation facility (a thermal power plant, a hydroelectric power plant, a geothermal power plant, a nuclear power plant, etc.) of a power company, and its output is stepped down through a substation and supplied as an AC voltage. Moreover, for example, it is installed in a building or an adjacent facility in the form of a self-generated generator, etc., and it supplies with a cable. The AC/DC converter 602 is a voltage conversion device that converts an AC voltage into a DC voltage, and converts the AC voltage of 100V or 200V supplied from the three-phase AC power source 601 into a predetermined DC voltage. Specifically, through voltage conversion, it is converted into a generally used expected DC voltage such as 3.3V, 5V, or 12V. When the driving object is a motor, it is converted to 12V. In addition, a single-phase AC power supply can be used instead of a three-phase AC power supply. In this case, as long as the AC/DC converter is single-phase input, the same system can be constructed.

The inverter 604 converts the DC voltage supplied by the AC/DC converter 602 into a three-phase AC voltage by switching operation, and outputs it to the motor 605 . The type of the motor 605 varies depending on the control object. In the case of the control object, it is a three-phase AC motor for driving wheels, and in the case of factory equipment, it is a three-phase AC motor for driving pumps and various power sources. In the case of home appliances, a three-phase AC motor for driving a compressor or the like is rotationally driven by the three-phase AC voltage output from the inverter 604, and the rotational driving force is transmitted to a driving force not shown in the figure. object.

In addition, for example, in home appliances, there are many driving objects (such as computers, LED lighting equipment, video equipment, audio equipment, etc.) that can directly supply the DC voltage output from the AC/DC converter 302. At this time, the control system 600 does not An inverter 604 is required, and as shown in FIG. 18 , a DC voltage is supplied from the AC/DC converter 602 to the driving object. In this case, for example, a DC voltage of 3.3V is supplied to a computer or the like, and a DC voltage of 5V is supplied to an LED lighting device or the like.

On the other hand, various sensors not shown in the figure are used to measure the rotational speed of the driven object, torque, or actual measured values such as the temperature and flow rate of the surrounding environment of the driven object, and these measurement signals are input. Drive control unit 606 . At the same time, the output voltage value of the inverter 604 is also input to the drive control unit 606 . Based on these measurement signals, the drive control unit 606 gives a feedback signal to the inverter 604 to control the switching operation by the switching element. In this way, by instantly correcting the AC voltage applied to the motor 605 by the inverter 604, the operation control of the driven object can be correctly performed, and the stable operation of the driven object can be realized. Also, as described above, when the object to be driven can be driven by a DC voltage, the AC/DC converter 602 may also be controlled by feedback instead of the feedback of the inverter.

FIG. 19 shows the circuit configuration of FIG. 18 . As shown in this figure, the semiconductor device of the present invention is used in the AC/DC converter 602 and the inverter 604 as a Schottky barrier diode, for example, and is applied to switching control. The AC/DC converter 602 uses, for example, a bridge-connected Schottky barrier diode circuit configuration, and performs DC conversion by transforming and rectifying the negative voltage portion of the input voltage into a positive voltage. Also in the inverter 604, a switching circuit in the IGBT is assembled to perform switching control. In addition, an inductor (coil, etc.) is provided between the three-phase AC power supply 601 and the AC/DC converter 602 to stabilize the current, and between the AC/DC converter 602 and the inverter 604 is provided capacitors (electrolytic capacitors, etc.), thereby achieving voltage stabilization.

In addition, as shown by the dotted line in FIG. 19 , the driving control unit 606 is provided with an arithmetic unit 607 constituted by a CPU and a storage unit 608 constituted by a nonvolatile memory. The signal input to the drive control unit 606 is transmitted to the calculation unit 607 to perform necessary calculation, thereby generating a feedback signal for each semiconductor element. In addition, the storage unit 608 temporarily stores the calculation result of the calculation unit 607 , or stores physical constants and functions required for drive control in a table format and outputs them to the calculation unit 607 as appropriate. The calculation unit 607 and the storage unit 608 may have conventional structures, and the processing capability and the like may be arbitrarily selected.

In such a control system 600 , like the control system 500 shown in FIGS. 16 and 17 , a diode or switching element is also used in the rectification operation and switching operation of the AC/DC converter 602 and the inverter 604 . Thyristor, power transistor, IGBT, MOSFET, etc. By using gallium oxide (Ga ₂ O ₃ ), especially corundum-type gallium oxide (α-Ga ₂ O ₃ ), as the material of these semiconductor elements, the switching characteristics are improved. Furthermore, by applying the semiconductor film and semiconductor device of the present invention, excellent switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be achieved. That is, both the AC/DC converter 602 and the inverter 604 can expect the effect of the present invention, and any one of these or a combination thereof, or the type including the drive control unit 606 can expect the effect of the present invention.

18 and 19 exemplify the motor 605 as the object to be driven, but the object to be driven is not limited to a machine operator, and many devices that require an AC voltage may be targeted. As long as electric power is input from an AC power source to drive the object to be driven, the control system 600 can be applied, and the control system 600 can be applied to infrastructure equipment (for example, power equipment such as buildings and factories, communication equipment, traffic control equipment, water purification equipment, system equipment, and labor-saving equipment). , trains, etc.) or home appliances (eg, refrigerators, washing machines, computers, LED lighting equipment, video equipment, audio equipment, etc.) as objects, and the control system 600 is mounted to drive and control these objects. [Example]

Examples of the present invention will be described below, but the present invention is not limited to these.

(Example 1) 1. Formation of n-type semiconductor layer 1-1. Film forming device The atomized CVD apparatus 1 used in this example will be described with reference to FIG. 12 . The atomized CVD apparatus 1 includes: a carrier gas source 2a for supplying a carrier gas; a flow control valve 3a for adjusting the flow rate of the carrier gas sent from the carrier gas source 2a; and a carrier gas (dilution) source 2b for supplying the carrier gas gas (dilution); flow control valve 3b, used to adjust the flow rate of carrier gas (dilution) sent from carrier gas (dilution) source 2b; mist generation source 4, containing raw material solution 4a; container 5, put water 5a The ultrasonic vibrator 6 is installed on the bottom surface of the container 5; the film forming chamber 7; the supply pipe 9 is connected to the film forming chamber 7 from the mist generation source 4; 11. Discharge the mist, droplets and exhaust gas after thermal reaction. In addition, the substrate 10 is provided on the heating plate 8 .

1-2. Formation of crystalline oxide semiconductor film An n-type semiconductor layer was formed on a sapphire substrate (substrate 10 ) using the atomized CVD apparatus shown in FIG. 12 .

1-3. Evaluation Using an XRD diffraction apparatus, the phase of the film obtained in the above 1-2. was identified, and as a result, the obtained film was α-Ga ₂ O ₃ .

2. Formation of n+-type semiconductor layer An n+-type semiconductor layer was formed on the n-type semiconductor layer in the same manner as in 1-2. above, except that tin was used as a dopant. For the obtained film, the phase of the film was identified using an XRD diffraction apparatus, and the obtained film was α-Ga ₂ O ₃ .

3. Formation of Ohmic Electrodes A Ti layer and an Au layer were sputtered on the n + -type semiconductor layer of the laminate obtained in the above 2. to perform lamination. In addition, the thickness of the Ti layer was 70 nm, and the thickness of the Au layer was 30 nm.

4. Lamination of conductive substrates On the ohmic electrode of the laminate obtained in 3. above, a Cu-Mo composite substrate (70% by mass of Mo and 30% by mass of Cu) was laminated via a conductive adhesive layer composed of a sintered silver particle. In addition, the thickness of the conductive substrate was 200 μm.

5. Substrate removal In the laminated body obtained in the above 4., the above-mentioned sapphire substrate is removed.

6. Formation of Schottky Electrodes A Co film (thickness 100 nm), a Ti film (50 nm), and an Al film (thickness 5 μm) were respectively formed by EB evaporation on the second n-type semiconductor layer of the laminate obtained in the above 5. as a Schottky film. electrode.

(Comparative Example 1) An SBD was produced in accordance with Example 1, except that the Si substrate was used as the conductive substrate.

(Evaluation of electrical properties) For the semiconductor devices (SBD) obtained in Example 1 and Comparative Example 1, IV characteristics were evaluated. The results are shown in Figure 13 and Figure 14, respectively. As can be seen from FIGS. 13 and 14 , the Schottky barrier diode of Example 1 has excellent electrical characteristics. In addition, when the Cu—Mo laminated substrate shown in FIG. 23 was used as a conductive substrate, electrical characteristics equivalent to those of Example 1 were also obtained.

The semiconductor element of the present invention can be used in all fields such as semiconductors (eg, compound semiconductor electronic elements), electronic parts/electrical equipment parts, optical/electronic image-related devices, and industrial components, and is particularly useful as a power element.

1: Film formation device (atomized CVD device) 2a: carrier gas source 2b: Carrier gas (dilution) source 3a: Flow control valve 3b: Flow regulating valve 4: The source of atomization 4a: raw material solution 4b: raw material microparticles 5: Container 5a: water 6: Ultrasonic vibrator 7: Film forming chamber 8: Heating plate 9: Supply pipe 10: Substrate 101: Semiconductor layer 101a: n-type semiconductor layer 101b: n+ type semiconductor layer 102: p-type semiconductor layer 103: Metal layer 104: Insulator layer 105: Electrode layer 105a: Schottky electrode (other electrode layers) 105b: Ohmic electrode (electrode layer) 106: Conductive Adhesive Layer 107: Conductive substrate 107a: 1st metal layer 107b: 2nd metal layer 107c: Metal Layer 3 107d: 4th metal layer 107e: Metal Layer 5 108: Bottom substrate 131a: n-type semiconductor layer 131b: 1n+ type semiconductor layer 131c: 2n+ type semiconductor layer 132: p-type semiconductor layer 134: gate insulating film 135a: Gate electrode 135b: source electrode 135c: drain electrode 136: conductive adhesive layer 137: Conductive substrate 141a: n-type semiconductor layer 141b: 1n+ type semiconductor layer 141c: 2n+ type semiconductor layer 142: p-type semiconductor layer 145a: Gate electrode 145b: source electrode 145c: drain electrode 146: conductive adhesive layer 147: Conductive substrate 500: Control System 501: Battery (Power) 502: Boost Converter 503: Buck Converter 504: Inverter 505: Motor (drive object) 506: Drive Control Department 507: Calculation Department 508: Storage Department 600: Control System 601: Three-phase AC power supply (power supply) 602: AC/DC Converter 604: Inverter 605: Motor (drive object) 606: Drive Control Department 607: Calculation Department 608: Storage Department

FIG. 1 is a view showing an example of a laminate used in an embodiment of the present invention. FIG. 2 is a view showing an example of the bonded laminate used in the embodiment of the present invention. FIG. 3 is a diagram showing an example of a semiconductor structure used in an embodiment of the present invention. FIG. 4 is a diagram schematically showing a preferred aspect of the Schottky Barrier Diode (SBD) of the present invention. FIG. 5 is a diagram schematically showing a preferred aspect of the Schottky Barrier Diode (SBD) of the present invention. FIG. 6 is a diagram schematically showing a preferred example of the metal oxide semiconductor field effect transistor (MOSFET) of the present invention. FIG. 7 is a schematic diagram for explaining a part of the manufacturing steps of the metal oxide semiconductor field effect transistor (MOSFET) of FIG. 4 . FIG. 8 is a diagram schematically showing a preferred example of the electrostatic induction transistor (SIT) of the present invention. FIG. 9 is a diagram schematically showing a preferred example of the Schottky barrier diode (SBD) of the present invention. FIG. 10 is a diagram schematically showing a preferred example of the metal oxide semiconductor field effect transistor (MOSFET) of the present invention. FIG. 11 is a diagram schematically showing a preferred example of the junction field effect transistor (JFET) of the present invention. FIG. 12 is a block diagram of an atomized CVD apparatus used in the Example of the present invention. FIG. 13 is a graph showing the results of IV measurement in Examples, with current (A) on the vertical axis and voltage (V) on the horizontal axis. FIG. 14 is a graph showing the results of IV measurement in the comparative example, with the current (A) on the vertical axis and the voltage (V) on the horizontal axis. FIG. 15 is a diagram schematically showing a preferred example of a semiconductor device. FIG. 16 is a block diagram showing an example of a control system of a semiconductor device to which an embodiment of the present invention is applied. 17 is a circuit diagram showing an example of a control system of a semiconductor device to which the embodiment of the present invention is applied. 18 is a block diagram showing an example of a control system of a semiconductor device to which the embodiment of the present invention is applied. 19 is a circuit diagram showing an example of a control system of a semiconductor device to which the embodiment of the present invention is applied. FIG. 20 is a graph showing simulation results of thermal resistance in an embodiment of the present invention. FIG. 21 is a graph showing simulation results of thermal resistance in an embodiment of the present invention. FIG. 22 is a graph showing simulation results of thermal resistance in an embodiment of the present invention. FIG. 23 is a diagram showing a preferred aspect of the conductive substrate (Cu-Mo laminated substrate) in the embodiment of the present invention. FIG. 24 is a graph showing the warpage measurement results in the embodiment of the present invention.

101a: n-type semiconductor layer

101b: n+ type semiconductor layer

105a: Schottky electrode (other electrode layers)

105b: Ohmic electrode (electrode layer)

106: Conductive Adhesive Layer

107: Conductive substrate

Claims (13)

A semiconductor element comprising at least a semiconductor layer containing a crystalline oxide semiconductor as a main component, an electrode layer laminated on the semiconductor layer, and a conductive substrate laminated directly or via other layers on the electrode layer, wherein the conductive The flexible substrate contains at least a metal of Group 6 of the periodic table. The semiconductor device according to claim 1, wherein the metal of Group 6 of the periodic table is molybdenum. The semiconductor device according to claim 1 or 2, wherein the conductive substrate further comprises a metal of Group 11 of the periodic table. The semiconductor device according to claim 3, wherein the metal of Group 11 of the periodic table is copper. The semiconductor device according to claim 3 or 4, wherein the conductive substrate has a layered structure in which at least one layer each of a layer containing a metal from Group 6 of the periodic table and a layer containing a metal from group 11 of the periodic table are laminated. The semiconductor element according to any one of claims 1 to 5, wherein the weight ratio of the metal of Group 6 of the periodic table in the conductive substrate is 0.09 or more. The semiconductor device according to any one of claims 1 to 6, wherein the crystalline oxide semiconductor contains at least one metal selected from the group consisting of aluminum, indium, and gallium. The semiconductor device according to any one of claims 1 to 7, wherein the crystalline oxide semiconductor contains at least gallium. The semiconductor element according to any one of claims 1 to 8, further comprising another electrode layer on the surface of the semiconductor layer facing the surface on which the electrode layer is stacked. The semiconductor element according to any one of claims 1 to 9, which is a power element. A semiconductor device, which is a semiconductor device in which a semiconductor element is at least bonded to a lead frame, a circuit substrate or a heat dissipation substrate by a bonding member, wherein the semiconductor element is the semiconductor element according to any one of claims 1 to 10 . A power conversion device in which the semiconductor device as claimed in claim 11 is used. A control system in which the semiconductor device as claimed in claim 11 is used.

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