WO2022230834A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2022230834A1
WO2022230834A1 PCT/JP2022/018790 JP2022018790W WO2022230834A1 WO 2022230834 A1 WO2022230834 A1 WO 2022230834A1 JP 2022018790 W JP2022018790 W JP 2022018790W WO 2022230834 A1 WO2022230834 A1 WO 2022230834A1
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layer
semiconductor device
semiconductor layer
current blocking
present
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PCT/JP2022/018790
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French (fr)
Japanese (ja)
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雅裕 杉本
慎平 松田
安史 樋口
和良 則松
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株式会社Flosfia
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Priority to JP2023517527A priority Critical patent/JPWO2022230834A1/ja
Publication of WO2022230834A1 publication Critical patent/WO2022230834A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a semiconductor device useful as a power device or the like.
  • Gallium oxide (Ga 2 O 3 ) is a transparent semiconductor that has a wide bandgap of 4.8-5.3 eV at room temperature and hardly absorbs visible and ultraviolet light. It is therefore a particularly promising material for use in opto - electronic devices and transparent electronics operating in the deep UV region.
  • LEDs Light-emitting diodes
  • transistors have been developed (see Non-Patent Document 1). According to Patent Document 4, the gallium oxide can control the bandgap by forming a mixed crystal of indium and aluminum, respectively or in combination, and constitutes an extremely attractive material system as an InAlGaO-based semiconductor. .
  • Gallium oxide (Ga 2 O 3 ) has five crystal structures ⁇ , ⁇ , ⁇ , ⁇ , and ⁇ , and generally the most stable structure is ⁇ -Ga 2 O 3 .
  • ⁇ -Ga 2 O 3 has a ⁇ -Gallic structure, it is not necessarily suitable for use in semiconductor devices, unlike crystal systems generally used in electronic materials and the like.
  • the growth of the ⁇ -Ga 2 O 3 thin film requires a high substrate temperature and a high degree of vacuum, there is also the problem of increased manufacturing costs.
  • ⁇ -Ga 2 O 3 even a high concentration (for example, 1 ⁇ 10 19 /cm 3 or more) of dopant (Si) is 800% after ion implantation. C. to 1100.degree. C., it could not be used as a donor without annealing.
  • ⁇ -Ga 2 O 3 has the same crystal structure as the sapphire substrate that has already been widely used, so it is suitable for use in optoelectronic devices, and has a wider band than ⁇ -Ga 2 O 3 . Since it has a gap, it is particularly useful for power devices. Therefore, semiconductor devices using ⁇ -Ga 2 O 3 as a semiconductor are eagerly awaited.
  • Patent Document 1 discloses a Ga 2 O 3 -based crystal layer containing donors and an N-doped region formed in at least a part of the Ga 2 O 3 -based crystal layer, wherein the N-doped region is a channel region.
  • a vertical MOSFET is disclosed that is a current blocking region that includes or has an open region that provides a current path. However, it has not been confirmed that it actually operates as a vertical MOSFET, and its reliability such as withstand voltage is not sufficiently satisfactory.
  • An object of the present invention is to provide a semiconductor device with excellent withstand voltage.
  • a crystalline oxide semiconductor layer including a channel layer and a drift layer and a gate electrode disposed on the channel layer with a gate insulating film interposed therebetween. and a current blocking layer disposed between the channel layer and the drift layer, wherein the current blocking layer contains a dopant element, and the current blocking layer contains the dopant element concentration of 5.0 ⁇ 10 17 /cm 3 or more has improved withstand voltage compared to a structure without such a current blocking layer. It has been found that the semiconductor device thus obtained can solve the conventional problems described above. Moreover, after obtaining the above knowledge, the inventors of the present invention completed the present invention through further studies.
  • a crystalline oxide semiconductor layer including a channel layer and a drift layer, a gate electrode disposed on the channel layer with a gate insulating film interposed therebetween, and a gate electrode disposed between the channel layer and the drift layer wherein the current blocking layer contains a dopant element, and the concentration of the dopant element in the current blocking layer is 5.0 ⁇ 10 17 /cm 3 or more.
  • a semiconductor device comprising a region.
  • the dopant element is a p-type dopant element.
  • [3] The semiconductor device according to [1] or [2], wherein the concentration of the dopant element in the current blocking layer is 1.0 ⁇ 10 18 /cm 3 or more.
  • [4] The semiconductor according to any one of [1] to [3], wherein the thickness of the region in the current blocking layer where the concentration of the dopant element is 5.0 ⁇ 10 17 /cm 3 or more is 200 nm or more.
  • Device. [5] The semiconductor device according to any one of [1] to [4], wherein the dopant element is doped by ion implantation.
  • [6] The semiconductor device according to any one of [1] to [5], wherein the current blocking layer contains a crystalline oxide as a main component.
  • a semiconductor device with excellent pressure resistance can be provided.
  • FIG. 1 schematically illustrates a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the invention
  • FIG. 1 schematically illustrates a preferred manufacturing process for a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention
  • FIG. 1 schematically illustrates a preferred manufacturing process for a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention
  • FIG. 1 schematically illustrates a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the invention
  • FIG. 4 is a diagram showing the results of IV measurements in Examples and Comparative Examples.
  • FIG. 1 schematically illustrates a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the invention;
  • FIG. 1 schematically illustrates a preferred manufacturing process for a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention;
  • FIG. 1 schematically illustrates a preferred manufacturing process for a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention;
  • FIG. 1 is a configuration diagram of a mist CVD apparatus used in an embodiment of the present invention;
  • FIG. 1 is a configuration diagram of a mist CVD apparatus used in an embodiment of the present invention;
  • FIG. 1 is a block configuration diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention
  • FIG. 1 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention
  • FIG. 1 is a block configuration diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention
  • FIG. 1 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention
  • FIG. 1 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention
  • a semiconductor device includes a crystalline oxide semiconductor layer including a channel layer and a drift layer, a gate electrode disposed on the channel layer with a gate insulating film interposed therebetween, the channel layer and the A semiconductor device comprising at least a current blocking layer disposed between a drift layer and a drift layer, wherein the current blocking layer contains a dopant element, and the concentration of the dopant element in the current blocking layer is 5.0. It is characterized by including a region having a density of 10 17 /cm 3 or more.
  • the crystalline oxide semiconductor layer is not particularly limited as long as it does not hinder the object of the present invention.
  • the crystalline oxide semiconductor layer preferably contains a crystalline oxide semiconductor as a main component.
  • the crystalline oxide semiconductor include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt and iridium. can give.
  • the crystalline oxide semiconductor layer preferably contains at least one metal selected from aluminum, indium and gallium, more preferably at least gallium, and ⁇ -Ga 2 Most preferred is O3 or mixed crystals thereof.
  • the crystal structure of the crystalline oxide semiconductor layer is also not particularly limited as long as the object of the present invention is not hindered.
  • the crystal structure of the crystalline oxide semiconductor layer includes, for example, a corundum structure, a ⁇ -gallia structure, a hexagonal crystal structure (eg, ⁇ -type structure, etc.), an orthogonal crystal structure (eg, ⁇ -type structure, etc.), a cubic crystal structure, Alternatively, a tetragonal crystal structure or the like can be mentioned.
  • the crystalline oxide semiconductor layer preferably has a corundum structure, a ⁇ -gallia structure or a hexagonal crystal structure (e.g., ⁇ -type structure, etc.), and more preferably has a corundum structure.
  • the “main component” means that the crystalline oxide semiconductor accounts for preferably 50% or more, more preferably 70% or more, and even more preferably 70% or more, in atomic ratio, of all components of the crystalline oxide semiconductor layer. means that the content is 90% or more, and may be 100%.
  • the crystalline oxide semiconductor is gallium oxide
  • the crystalline oxide semiconductor has an atomic ratio of gallium in all metal elements contained in the crystalline oxide semiconductor layer of 0.5 or more.
  • the layer contains gallium oxide as a crystalline oxide semiconductor.
  • the atomic ratio of gallium in all metal elements contained in the crystalline oxide semiconductor layer is preferably 0.7 or more, more preferably 0.9 or more.
  • the thickness of the crystalline oxide semiconductor layer is not particularly limited, and may be 1 ⁇ m or less or 1 ⁇ m or more. is preferred, and 10 ⁇ m or more is more preferred.
  • the surface area (in plan view) of the semiconductor film is not particularly limited, but may be 1 mm 2 or more or 1 mm 2 or less, preferably 10 mm 2 to 300 mm 2 , and preferably 10 mm 2 to 300 mm 2 . More preferably 100 mm 2 .
  • the crystalline oxide semiconductor layer is usually single crystal, but may be polycrystal.
  • the crystalline oxide semiconductor layer usually includes two or more semiconductor layers.
  • the crystalline oxide semiconductor layer includes, for example, at least an n+ type semiconductor layer, a drift layer (n ⁇ type semiconductor layer), a channel layer, and a source region (n+ type semiconductor layer). Further, the carrier density of the crystalline oxide semiconductor layer can be appropriately set by adjusting the doping amount.
  • the crystalline oxide semiconductor layer preferably contains a dopant.
  • the dopant is not particularly limited and may be a known one.
  • suitable examples of the dopant include tin, germanium, silicon, titanium, zirconium and vanadium. or n-type dopants such as niobium, or Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au , Zn, Cd, Hg, Ti, Pb, N, or P, and the like.
  • the n-type dopant is preferably at least one selected from Sn, Ge and Si.
  • the content of the dopant is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and more preferably 0.00001 atomic % to 10 atomic % in the composition of the semiconductor layer. is most preferred. More specifically, the dopant concentration may typically be about 1 ⁇ 10 16 /cm 3 to 1 ⁇ 10 22 /cm 3 , and the dopant concentration may be, for example, about 1 ⁇ 10 17 /cm 3 . A low concentration of 3 or less may be used. Further, according to the present invention, the dopant may be contained at a high concentration of about 1 ⁇ 10 20 /cm 3 or higher.
  • the crystalline oxide semiconductor layer includes a channel layer, and a gate electrode is arranged on the channel layer with the gate insulating film interposed therebetween.
  • the constituent material of the channel layer may be the same as the constituent material of the crystalline oxide semiconductor layer described above.
  • the conductivity type of the channel layer is not particularly limited, and may be n-type or p-type. When the conductivity type of the channel layer is the n-type, preferable examples of the constituent material of the channel layer include ⁇ -Ga 2 O 3 and mixed crystals thereof.
  • the constituent material of the channel layer is preferably, for example, ⁇ -Ga 2 O 3 containing a p-type dopant or a mixed crystal thereof.
  • Metal oxides containing at least one metal selected from Group 6 eg, ⁇ -Cr 2 O 3 etc.
  • Metal oxides containing at least one metal selected from Group 9 of the periodic table eg, ⁇ -Ir 2 O 3 , ⁇ -Cr 2 O 3 , ⁇ -Rh 2 O 3
  • the metal oxide containing at least one metal selected from Group 6 of the periodic table or the metal oxide containing at least one metal selected from Group 9 of the periodic table may be other metal oxides (e.g. Ga 2 O 3 ) may be a mixed crystal.
  • a constituent material of the gate insulating film is not particularly limited, and may be a known material.
  • the material of the gate insulating film include SiO 2 film, phosphorus-added SiO 2 film (PSG film), boron-added SiO 2 film, phosphorus-boron-added SiO 2 film (BPSG film), and the like.
  • methods for forming the gate insulating film include CVD, atmospheric pressure CVD, plasma CVD, mist CVD, and the like. In an embodiment of the present invention, the method for forming the gate insulating film is preferably mist CVD or atmospheric pressure CVD.
  • the constituent material of the gate electrode is not particularly limited, and may be a known electrode material.
  • Examples of the constituent material of the gate electrode include the constituent materials of the source electrode described above.
  • a method for forming the gate electrode is not particularly limited. Specific examples of the method for forming the gate electrode include a dry method and a wet method. Dry methods include, for example, sputtering, vacuum deposition, and CVD. Wet methods include, for example, screen printing and die coating.
  • the constituent material of the drift layer examples include the constituent materials of the crystalline oxide semiconductor layer described above.
  • the drift layer preferably contains a crystalline oxide semiconductor as a main component.
  • the crystalline oxide semiconductor is: It preferably contains at least one metal selected from aluminum, indium and gallium, more preferably at least gallium, and most preferably ⁇ -Ga 2 O 3 or a mixed crystal thereof.
  • the conductivity type of the drift layer is preferably n-type.
  • the preferred current blocking layer described above is used as the current blocking layer. function can be suitably exhibited in a semiconductor device (such as a MOSFET).
  • the current blocking layer is provided between the channel layer and the drift layer in the semiconductor device, contains a dopant element, and the concentration of the dopant element in the current blocking layer is is not particularly limited as long as it includes a region in which is 5.0 ⁇ 10 17 /cm 3 or more.
  • the current blocking layer may be provided within the drift layer or may be provided on the drift layer.
  • the dopant element may be introduced into the current blocking layer by ion implantation, or may be introduced into the current blocking layer by epitaxial growth. Note that the ion implantation profile is not particularly limited. In embodiments of the present invention, the ion implantation is preferably performed with a box profile.
  • Elements to be implanted in ion implantation are not particularly limited.
  • the dopant elements include Sn, Ge, Si, Ti, Zr, V, Nb, Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, Al, N and the like.
  • the dopant element concentration contained in the current blocking layer is preferably 1.0 ⁇ 10 18 /cm 3 or more.
  • the thickness of the region where the concentration of the dopant element in the current blocking layer is 5.0 ⁇ 10 17 /cm 3 or more is 200 nm or more.
  • the dopant element is preferably Mg, H, Li, Na, K, Rb, Cs, Fr , Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, or P, and more Mg is preferred.
  • the source region is not particularly limited as long as it includes an n+ type semiconductor layer.
  • the source region includes at least an n + -type semiconductor layer and an n++ -type semiconductor layer disposed on the n + -type semiconductor layer and having a higher carrier density than the n + -type semiconductor layer.
  • the carrier density can be determined using a known method. Examples of methods for determining the carrier density include SIMS (secondary ion mass spectrometry), SCM (scanning capacitance microscopy), SMM (scanning microwave microscopy), and SRA (spreading resistance measurement). etc.
  • SIMS secondary ion mass spectrometry
  • SCM scanning capacitance microscopy
  • SMM scanning microwave microscopy
  • SRA scanning resistance measurement
  • the main component of the n + -type semiconductor layer and the main component of the n++ -type semiconductor layer are the same. Further, in the embodiment of the present invention, it is preferable that the n + type semiconductor layer and the n ++ type semiconductor layer have the same crystal structure, and the n + type semiconductor layer and the n ++ type semiconductor layer have a corundum structure. It is more preferable to have
  • the “main component” means, for example, when the main component of the n + type semiconductor layer is gallium oxide, the atomic ratio of gallium in all metal elements in the n + type semiconductor layer is 50% or more.
  • the atomic ratio of gallium in all metal elements in the n + -type semiconductor layer is preferably 70% or more, more preferably 90% or more, and may be 100%.
  • the n++ type semiconductor layer is preferably an epitaxial layer, and more preferably the n++ type semiconductor layer is epitaxially doped.
  • epitaxial doping means doping by epitaxial growth, not doping by ion implantation or the like.
  • the n-type dopant contained in the n + -type semiconductor layer and/or the n++-type semiconductor layer include at least one n-type dopant selected from tin, germanium, silicon, titanium, zirconium, vanadium and niobium. mentioned.
  • the n-type dopant is preferably at least one selected from Sn, Ge and Si.
  • the carrier density of the n++ type semiconductor layer is not particularly limited as long as it is higher than the carrier density of the n+ type semiconductor layer.
  • the n++ type semiconductor layer preferably has a carrier density of 1.0 ⁇ 10 19 /cm 3 or more, more preferably 6.0 ⁇ 10 19 /cm 3 or more. .
  • the carrier density of the n++ type semiconductor layer is not particularly limited. In an embodiment of the present invention, it is preferable that the carrier density of the n+ type semiconductor layer is in the range of 1.0 ⁇ 10 17 /cm 3 or more and less than 1.0 ⁇ 10 19 /cm 3 . By setting the carrier density of the n + -type semiconductor layer within the preferred range as described above, the source resistance can be reduced more satisfactorily.
  • the method of doping the n+ type semiconductor layer is not particularly limited, and may be diffusion, ion implantation, or epitaxial growth.
  • the mobility of the n+ type semiconductor layer is higher than the mobility of the n++ type semiconductor layer.
  • the thickness of the n++ type semiconductor layer is not particularly limited as long as the object of the present invention is not hindered.
  • the n++ type semiconductor layer preferably has a thickness in the range of 1 nm to 1 ⁇ m, more preferably in the range of 10 nm to 100 nm. In an embodiment of the present invention, the thickness of the n+ type semiconductor layer is preferably larger than the thickness of the n++ type semiconductor layer.
  • the source contact resistance and the source resistance in the semiconductor device can be satisfactorily reduced by using the above-described preferable combination of the n + -type semiconductor layer and the n++ -type semiconductor layer, the element resistance is further reduced.
  • a semiconductor device can be realized.
  • the crystalline oxide semiconductor layer (hereinafter also referred to as "oxide semiconductor layer”, “semiconductor film” or “semiconductor layer”) may be formed using known means.
  • means for forming the semiconductor layer include CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulse growth, and ALD.
  • the means for forming the semiconductor layer is preferably MOCVD, mist CVD, mist epitaxy or HVPE, preferably mist CVD or mist epitaxy.
  • the mist CVD method or mist epitaxy method for example, the mist CVD apparatus shown in FIG.
  • a semiconductor film containing a crystalline oxide semiconductor as a main component is formed on a substrate by transporting droplets onto a substrate with a carrier gas (transporting step) and then thermally reacting the atomized droplets in the vicinity of the substrate. (film formation step) to form the semiconductor layer.
  • the atomization step atomizes the raw material solution.
  • the means for atomizing the raw material solution is not particularly limited as long as it can atomize the raw material solution, and may be any known means.
  • atomizing means using ultrasonic waves is preferable.
  • Atomized droplets obtained using ultrasonic waves have an initial velocity of zero and are preferable because they float in the air. Since it is a possible mist, there is no damage due to collision energy, so it is very suitable.
  • the droplet size is not particularly limited, and may be droplets of several millimeters, preferably 50 ⁇ m or less, more preferably 100 nm to 10 ⁇ m.
  • the raw material solution is not particularly limited as long as it contains a raw material capable of being atomized or dropletized and capable of forming a semiconductor film, and may be an inorganic material or an organic material.
  • the raw material is preferably a metal or a metal compound, and one or two selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt and iridium. More preferably, it contains more than one species of metal.
  • a solution in which the metal is dissolved or dispersed in an organic solvent or water in the form of a complex or salt can be preferably used.
  • forms of the complex include acetylacetonate complexes, carbonyl complexes, ammine complexes, hydride complexes, and the like.
  • the salt form include organic metal salts (e.g., metal acetates, metal oxalates, metal citrates, etc.), metal sulfide salts, metal nitrate salts, metal phosphate salts, metal halide salts (e.g., metal chlorides, salts, metal bromides, metal iodides, etc.).
  • hydrohalic acid examples include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Among them, hydrobromic acid or Hydroiodic acid is preferred.
  • oxidizing agent examples include hydrogen peroxide (H 2 O 2 ), sodium peroxide (Na 2 O 2 ), barium peroxide (BaO 2 ), benzoyl peroxide (C 6 H 5 CO) 2 O 2 and the like. , hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, and organic peroxides such as peracetic acid and nitrobenzene.
  • the raw material solution may contain a dopant.
  • the dopant By including the dopant in the raw material solution, the doping can be performed well.
  • the dopant is not particularly limited as long as it does not interfere with the object of the present invention.
  • the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium or niobium, or Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba , Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N or P, and the like.
  • the content of the dopant is appropriately set by using a calibration curve showing the relationship between the concentration of the dopant in the raw material and the desired carrier density.
  • the solvent of the raw material solution is not particularly limited, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent.
  • the solvent preferably contains water, more preferably water or a mixed solvent of water and alcohol.
  • the atomized liquid droplets are transported into the film forming chamber using a carrier gas.
  • the carrier gas is not particularly limited as long as it does not interfere with the object of the present invention. Suitable examples include oxygen, ozone, inert gases such as nitrogen and argon, and reducing gases such as hydrogen gas and forming gas. mentioned.
  • one type of carrier gas may be used, two or more types may be used, and a diluted gas with a reduced flow rate (for example, a 10-fold diluted gas, etc.) may be further used as a second carrier gas. good too.
  • the carrier gas may be supplied at two or more locations instead of at one location.
  • the flow rate of the carrier gas is not particularly limited, it is preferably 0.01 to 20 L/min, more preferably 1 to 10 L/min.
  • the flow rate of diluent gas is preferably 0.001 to 2 L/min, more preferably 0.1 to 1 L/min.
  • the semiconductor film is formed on the substrate by thermally reacting the atomized droplets in the vicinity of the substrate.
  • the thermal reaction is not particularly limited as long as the atomized droplets react with heat, and the reaction conditions and the like are not particularly limited as long as they do not interfere with the object of the present invention.
  • the thermal reaction is usually carried out at a temperature equal to or higher than the evaporation temperature of the solvent, preferably at a temperature that is not too high (for example, 1000° C.), more preferably 650° C. or less, most preferably from 300° C. to 650° C. preferable.
  • the thermal reaction is carried out under vacuum, under a non-oxygen atmosphere (for example, under an inert gas atmosphere, etc.), under a reducing gas atmosphere, or under an oxygen atmosphere, as long as the object of the present invention is not hindered.
  • a non-oxygen atmosphere for example, under an inert gas atmosphere, etc.
  • a reducing gas atmosphere for example, under an inert gas atmosphere, etc.
  • an oxygen atmosphere for example, under an inert gas atmosphere, etc.
  • the reaction may be carried out under atmospheric pressure, increased pressure or reduced pressure, but is preferably carried out under atmospheric pressure in the embodiment of the present invention.
  • the film thickness can be set by adjusting the film formation time.
  • the substrate is not particularly limited as long as it can support the semiconductor film.
  • the material of the substrate is also not particularly limited as long as it does not interfere with the object of the present invention, and may be a known substrate, an organic compound, or an inorganic compound.
  • the shape of the substrate may be any shape, and is effective for all shapes. Cylindrical, helical, spherical, ring-shaped, etc. are mentioned, but in the embodiment of the present invention, the substrate is preferable.
  • the thickness of the substrate is not particularly limited in embodiments of the present invention.
  • the substrate is not particularly limited as long as it has a plate shape and serves as a support for the semiconductor film.
  • the substrate may be an insulator substrate, a semiconductor substrate, a metal substrate, or a conductive substrate.
  • a substrate with a membrane is also preferred.
  • the substrate for example, a base substrate containing a substrate material having a corundum structure as a main component, or a base substrate containing a substrate material having a ⁇ -gallia structure as a main component, a substrate material having a hexagonal crystal structure as a main component.
  • a base substrate etc. are mentioned.
  • the “main component” means that the substrate material having the specific crystal structure accounts for preferably 50% or more, more preferably 70% or more, and even more preferably 90%, in atomic ratio, of all components of the substrate material. % or more, and may be 100%.
  • the substrate material is not particularly limited as long as it does not interfere with the object of the present invention, and may be any known material.
  • the substrate material having the corundum structure for example, ⁇ -Al 2 O 3 (sapphire substrate) or ⁇ -Ga 2 O 3 are preferably mentioned, a-plane sapphire substrate, m-plane sapphire substrate, r-plane sapphire substrate , a c-plane sapphire substrate, an ⁇ -type gallium oxide substrate (a-plane, m-plane, or r-plane) and the like are more preferable examples.
  • the base substrate mainly composed of a substrate material having a ⁇ -Gallia structure is, for example, a ⁇ -Ga 2 O 3 substrate, or a substrate containing Ga 2 O 3 and Al 2 O 3 with more than 0 wt % of Al 2 O 3 and A mixed crystal substrate having a content of 60 wt % or less may be used.
  • Examples of base substrates mainly composed of a substrate material having a hexagonal crystal structure include SiC substrates, ZnO substrates, and GaN substrates.
  • annealing may be performed after the film formation process.
  • Annealing treatment temperature is not particularly limited as long as the object of the present invention is not impaired, and is usually 300°C to 650°C, preferably 350°C to 550°C.
  • the annealing treatment time is usually 1 minute to 48 hours, preferably 10 minutes to 24 hours, more preferably 30 minutes to 12 hours.
  • the annealing treatment may be performed under any atmosphere as long as the object of the present invention is not hindered.
  • a non-oxygen atmosphere or an oxygen atmosphere may be used.
  • the non-oxygen atmosphere includes, for example, an inert gas atmosphere (e.g., nitrogen atmosphere), a reducing gas atmosphere, etc. In the embodiment of the present invention, an inert gas atmosphere is preferable, and a nitrogen atmosphere Lower is more preferred.
  • the semiconductor film may be directly provided on the substrate, or other layers such as a stress relaxation layer (for example, a buffer layer, an ELO layer, etc.), a peeling sacrificial layer, etc. may be formed on the substrate.
  • the semiconductor film may be provided via the semiconductor film.
  • the means for forming each layer is not particularly limited, and known means may be used. In the embodiment of the present invention, the mist CVD method is preferred.
  • the semiconductor film may be used as the semiconductor layer in the semiconductor device after using known means such as peeling from the substrate or the like, or may be used as the semiconductor layer in the semiconductor device as it is. may be used.
  • the source electrode is not particularly limited as long as it has conductivity, as long as it does not hinder the object of the present invention.
  • the constituent material of the source electrode may be a conductive inorganic material or a conductive organic material.
  • the material of the source electrode is preferably metal.
  • Suitable examples of the metal include at least one metal selected from Groups 4 to 10 of the periodic table. Examples of metals belonging to Group 4 of the periodic table include titanium (Ti), zirconium (Zr), hafnium (Hf), and the like. Examples of metals belonging to Group 5 of the periodic table include vanadium (V), niobium (Nb), and tantalum (Ta).
  • Examples of Group 6 metals of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W).
  • Examples of metals of Group 7 of the periodic table include manganese (Mn), technetium (Tc), and rhenium (Re).
  • Examples of metals belonging to Group 8 of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os).
  • Examples of metals belonging to Group 9 of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir).
  • Examples of metals of Group 10 of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt).
  • the source electrode preferably contains at least one metal selected from titanium (Ti), tantalum (Ta) and tungsten (W).
  • the source electrode may contain a conductive metal oxide.
  • the conductive metal oxide contained in the source electrode include metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO).
  • the source electrode may be composed of a single layer, or may include a plurality of metal layers. If the source electrode comprises a plurality of metal layers, for example using Group 4 metals for the first and third layers, a metal layer located between the first and third layers.
  • a method for forming the source electrode is not particularly limited. Specific examples of the method for forming the source electrode include a dry method and a wet method. Dry methods include, for example, sputtering, vacuum deposition, and CVD. Wet methods include, for example, screen printing and die coating.
  • the source electrode preferably forms contact with the current blocking layer, and more preferably forms direct contact with the current blocking layer. With such a preferable configuration, the responsiveness of the semiconductor device can be further improved.
  • the semiconductor device of the present invention is useful for various semiconductor elements, especially for power devices.
  • the semiconductor element includes a horizontal element (horizontal device) in which an electrode is formed on one side of a semiconductor layer and current flows in a direction perpendicular to the film thickness direction of the semiconductor layer (horizontal device), and electrodes are formed on both front and back sides of the semiconductor layer.
  • a horizontal element horizontal device
  • vertical device vertical device
  • the semiconductor device is suitable for both horizontal and vertical devices.
  • it is preferably used for a vertical device.
  • the semiconductor device examples include metal semiconductor field effect transistors (MESFET), high electron mobility transistors (HEMT), metal oxide semiconductor field effect transistors (MOSFET), static induction transistors (SIT), junction field effect transistors ( JFET) or an insulated gate bipolar transistor (IGBT).
  • the semiconductor device is preferably MOSFET, SIT, JFET or IGBT, more preferably MOSFET or IGBT.
  • FIG. 1 shows the main part of a metal oxide semiconductor field effect transistor (MOSFET) which is one of the preferred embodiments of the present invention.
  • the MOSFET of FIG. 1 includes a drain electrode 5c, an n + type semiconductor layer 3, an n ⁇ type semiconductor layer 7 as a drift layer, a current blocking layer (current blocking region) 2, a channel layer 6, and a source region (n + type semiconductor layer) 1. , a gate insulating film 4a, an interlayer insulating film 4b, a gate electrode 5a and a source electrode 5b.
  • MOSFET metal oxide semiconductor field effect transistor
  • the n + type semiconductor layer 3, the n ⁇ type semiconductor layer (drift layer) 7, the current blocking layer 2, the channel layer 6 and the n + type semiconductor layer ( A source layer) 1 is formed in this order.
  • the n+ type semiconductor layer 3, the n ⁇ type semiconductor layer 7, the channel layer 6, the current blocking layer 2, and the n+ type semiconductor layer 1 constitute a crystalline oxide semiconductor layer 8.
  • the current blocking layer 2 is formed by ion implantation and is a layer containing crystal defects (not shown) due to the ion implantation.
  • the current blocking layer overlaps the source electrode in plan view when viewed from the thickness direction of the crystalline oxide semiconductor layer 8, and overlaps a part of the channel layer in plan view.
  • the current blocking layer is configured so as not to partially overlap the channel layer when viewed in the thickness direction of the crystalline oxide semiconductor layer 8 . Such a configuration secures a current path while maintaining the current blocking effect.
  • the width W of the current path is not particularly limited as long as it does not hinder the object of the present invention. In an embodiment of the present invention, it is preferable that the width W of the current path is 2 ⁇ m or less, particularly when a material having a large bandgap such as gallium oxide is used for the drift layer. Also, the thickness d of the current blocking layer is not particularly limited as long as the object of the present invention is not hindered.
  • the thickness d of the current blocking layer is preferably 0.15 ⁇ m or more, more preferably 0.2 ⁇ m or more. It is more preferable to have In the ON state of the MOSFET in FIG. 1, when a voltage is applied between the source electrode 5b and the drain electrode 5c, and a positive voltage is applied to the gate electrode 5a with respect to the source electrode 5b, electrons (holes) are generated. is injected into the channel layer 6 and turned on. In the OFF state, the channel layer 6 is filled with a depletion layer by setting the voltage of the gate electrode to 0 V, and the transistor is turned off.
  • the current blocking layer contains a dopant element, and the current blocking layer includes a region having a dopant element concentration of 5.0 ⁇ 10 17 /cm 3 or more.
  • the withstand voltage can be further improved.
  • the source region (n + -type semiconductor layer) 1 may be at least partially embedded in the channel layer 6 .
  • FIG. 4 shows an example in which the source region (n + -type semiconductor layer) 1 is embedded in the channel layer 6 . According to the structure shown in FIG. 4, the electric field concentration applied to the gate insulating film is less likely to occur, and the reliability of the gate insulating film can be further improved.
  • FIG. 9 shows the main part of a metal oxide semiconductor field effect transistor (MOSFET), which is one of the preferred embodiments of the present invention.
  • the MOSFET of FIG. 9 has a trench penetrating through at least the channel layer 6 in the crystalline oxide semiconductor layer 8, and the current blocking layer 2 is positioned immediately below the channel layer 6. Different from MOSFET.
  • the thickness of the current blocking layer 2 is preferably 0.2 ⁇ m or less, more preferably 0.1 ⁇ m or less. With such a preferable thickness, it is possible to achieve a current blocking effect while suppressing the influence on the rising voltage (Vth) of the MOSFET.
  • FIG. 10 shows the main part of a metal oxide semiconductor field effect transistor (MOSFET), which is one of the preferred embodiments of the present invention.
  • the MOSFET of FIG. 1 includes a drain electrode 5c, an n + type semiconductor layer 3, an n ⁇ type semiconductor layer 7 as a drift layer, a current blocking layer (current blocking region) 2, a channel layer 6, and a source region (n + type semiconductor layer) 1. , a gate insulating film 4, a gate electrode 5a and a source electrode 5b.
  • the n+ type semiconductor layer 3, the n ⁇ type semiconductor layer 7, the channel layer 6, the current blocking layer 2 and the n+ type semiconductor layer 1 constitute an oxide semiconductor layer 8.
  • the current blocking layer 2 is formed on the drift layer 7 by epitaxial growth.
  • the current blocking layer overlaps the source electrode in plan view when viewed from the thickness direction of the crystalline oxide semiconductor layer 8, and overlaps a part of the channel layer in plan view.
  • the current blocking layer is configured so as not to partially overlap the channel layer when viewed in the thickness direction of the crystalline oxide semiconductor layer 8 .
  • Such a configuration secures a current path while maintaining the current blocking effect.
  • the semiconductor since the first crystalline oxide as the main component of the drift layer 7 and the second crystalline oxide as the main component of the current blocking layer have different compositions, the semiconductor It is possible to further improve the breakdown voltage while maintaining the MOSFET operation (normally-off operation) of the device.
  • each layer in FIGS. 1, 4, 9 and 10 is not particularly limited as long as it does not hinder the object of the present invention, and may be known means. For example, after forming a film by a vacuum vapor deposition method, a CVD method, a sputtering method, or various coating techniques, a means for patterning by a photolithographic method, or a means for directly patterning using a printing technique or the like can be used.
  • FIG. 2(a) shows a laminated structure in which an n+ type semiconductor layer 3 and a drift layer (n type semiconductor layer) 7 are laminated in this order on a substrate 9.
  • FIG. A current blocking layer (crystal defect region) 2 is formed in the drift layer (n-type semiconductor layer) 7 of the laminate shown in FIG. 2(b) is obtained by forming the n+ type semiconductor layer 1 of FIG.
  • the implantation energy of the ion implantation is not particularly limited. In an embodiment of the invention, the implantation energy of said ion implantation is, for example, in the range of 10 keV to 2 MeV.
  • the n+ type semiconductor layer 1 is patterned by forming a film using an epitaxial growth method such as a mist CVD method and then etching using a known etching technique.
  • a gate insulating film 4a and a gate electrode 5a are formed on the laminate shown in FIG. 2(b), and an interlayer insulating film 4b and contact holes are formed to obtain the laminate shown in FIG. 2(c).
  • the gate insulating film 4a and the gate electrode 5a can be processed into the shape shown in FIG. 2(c) by etching using a known etching technique after forming films using a known film forming method. can.
  • the source electrode 5b is formed on the laminate shown in FIG. 2(c) using a known film formation method to obtain the laminate shown in FIG. 3(d).
  • a method for forming the source electrode 5b the above-described dry method, wet method, or the like can be used.
  • the semiconductor device of FIG. 3(e) can be obtained by forming the drain electrode 5c using a known film forming method.
  • the semiconductor device of FIG. 3(e) has a current blocking region (current blocking layer) made up of a crystal defect region, so that the MOSFET operation is maintained and the breakdown voltage is improved.
  • FIG. 11(a) shows a laminated structure in which an n+ type semiconductor layer 3, a drift layer (n ⁇ type semiconductor layer) 7, and a current blocking layer (current blocking region) 2 are stacked in this order on a substrate 9. .
  • the current blocking layer 2 is patterned using known patterning techniques.
  • a channel layer 6 and an n+ type semiconductor layer 1 as a source region on the layered structure of FIG. 11(a)
  • the layered structure of FIG. 11(b) is obtained.
  • the n+ type semiconductor layer 1 is patterned by forming a film using an epitaxial growth method such as a mist CVD method and then etching using a known etching technique.
  • a gate insulating film 4a and a gate electrode 5a are formed on the layered structure shown in FIG. 11(b), and an interlayer insulating film 4b and contact holes are formed to obtain the layered structure shown in FIG. 11(c).
  • the gate insulating film 4a and the gate electrode 5a can be processed into the shape shown in FIG. 11(c) by etching using a known etching technique after forming films using a known film forming method. can.
  • the source electrode 5b is formed on the laminate shown in FIG. 11(c) using a known film formation method to obtain the laminate shown in FIG. 12(d).
  • a method for forming the source electrode 5b the above-described dry method, wet method, or the like can be used.
  • the semiconductor device of FIG. 12(e) can be obtained by forming the drain electrode 5c using a known film formation method.
  • Example 1 a semiconductor device having a structure similar to that of the semiconductor device shown in FIG.
  • the configuration of Example 1 is as follows. An n ⁇ type semiconductor layer made of tin-doped ⁇ -Ga 2 O 3 was used as the n ⁇ type semiconductor layer 3, and an n+ type semiconductor layer made of tin doped ⁇ -Ga 2 O 3 was used as the n+ type semiconductor layer 1a. Nitrogen (Example 1) and tin (Example 2) were used as elements to be implanted by ion implantation. The ion implantation was performed so that Example 1 had a single profile, and Example 2 had a box profile.
  • Comparative Example 1 a semiconductor device was prototyped in the same manner as in Example 1, except that no current blocking region having a dopant element concentration of 5.0 ⁇ 10 17 /cm 3 or more was formed.
  • Results of IV measurement of the semiconductor devices manufactured in Examples 1, 2 and Comparative Example 1 are shown in FIG.
  • the semiconductor devices of Examples 1 and 2 according to the embodiment of the present invention are superior in withstand voltage to the semiconductor device of Comparative Example 1.
  • FIG. 5 This is a new finding that was first obtained when a semiconductor device using gallium oxide (especially ⁇ -Ga 2 O 3 ) was manufactured on a trial basis.
  • the SIMS measurement results in Examples 1 and 2 are shown in FIGS. 5 and 6, respectively.
  • FIG. 5 and 6 The SIMS measurement results in Examples 1 and 2 are shown in FIGS. 5 and 6, respectively.
  • the current blocking layer obtained in Example 1 has a region with a dopant element concentration of 5.0 ⁇ 10 17 /cm 3 or more.
  • the current blocking layer obtained in Example 2 has a region with a dopant element concentration of 1.0 ⁇ 10 18 /cm 3 or more.
  • a semiconductor device (MOSFET) having a structure similar to the semiconductor device shown in FIG. 1 was manufactured in the same manner as in Example 1, and the result of IV measurement is shown in FIG. As is clear from FIG. 8, the MOSFET in this embodiment works well as a transistor. It was found that a semiconductor device (MOSFET) having a structure similar to that of the semiconductor device shown in FIG.
  • the semiconductor device according to the embodiment of the present invention described above can be applied to power converters such as inverters and converters in order to exhibit the functions described above. More specifically, it can be applied as a switching element such as a thyristor, a power transistor, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and the like.
  • FIG. 14 is a block configuration diagram showing an example of a control system using a semiconductor device according to an embodiment of the present invention
  • FIG. 15 is a circuit diagram of the same control system, which is particularly suitable for mounting on an electric vehicle. control system.
  • the control system 500 has a battery (power supply) 501, a boost converter 502, a step-down converter 503, an inverter 504, a motor (driven object) 505, and a drive control unit 506, which are mounted on an electric vehicle.
  • the battery 501 is composed of a storage battery such as a nickel-metal hydride battery or a lithium-ion battery, and stores electric power by charging at a power supply station or regenerative energy during deceleration, and is necessary for the operation of the running system and electrical system of the electric vehicle. DC voltage can be output.
  • the boost converter 502 is, for example, a voltage conversion device equipped with a chopper circuit, and boosts the DC voltage of, for example, 200 V supplied from the battery 501 to, for example, 650 V by the switching operation of the chopper circuit, and outputs it to a running system such as a motor. be able to.
  • the step-down converter 503 is also a voltage converter equipped with a chopper circuit. It can be output to the electrical system including
  • the inverter 504 converts the DC voltage supplied from the boost converter 502 into a three-phase AC voltage by switching operation, and outputs the three-phase AC voltage to the motor 505 .
  • a motor 505 is a three-phase AC motor that constitutes the driving system of the electric vehicle, and is rotationally driven by the three-phase AC voltage output from the inverter 504. The rotational driving force is transmitted to the wheels of the electric vehicle via a transmission or the like (not shown). to
  • various sensors are used to measure actual values such as the number of revolutions and torque of the wheels and the amount of depression of the accelerator pedal (acceleration amount) from the running electric vehicle. is entered.
  • the output voltage value of inverter 504 is also input to drive control section 506 .
  • the drive control unit 506 has the function of a controller equipped with a calculation unit such as a CPU (Central Processing Unit) and a data storage unit such as a memory. By outputting it as a feedback signal, the switching operation of the switching element is controlled.
  • the AC voltage applied to the motor 505 by the inverter 504 is corrected instantaneously, so that the operation control of the electric vehicle can be accurately executed, and safe and comfortable operation of the electric vehicle is realized. It is also possible to control the output voltage to the inverter 504 by giving the feedback signal from the drive control unit 506 to the boost converter 502 .
  • FIG. 15 is a circuit configuration excluding the step-down converter 503 in FIG. 14, that is, only a configuration for driving the motor 505.
  • the semiconductor device of the present invention is employed as a Schottky barrier diode in a boost converter 502 and an inverter 504 for switching control.
  • Boost converter 502 is incorporated in a chopper circuit to perform chopper control
  • inverter 504 is incorporated in a switching circuit including IGBTs to perform switching control.
  • An inductor (such as a coil) is interposed in the output of the battery 501 to stabilize the current. It is stabilizing the voltage.
  • the driving control unit 506 is provided with an operation unit 507 made up of a CPU (Central Processing Unit) and a storage unit 508 made up of a non-volatile memory.
  • a signal input to the drive control unit 506 is supplied to the calculation unit 507, and a feedback signal for each semiconductor element is generated by performing necessary calculations.
  • the storage unit 508 temporarily holds the calculation result by the calculation unit 507, accumulates physical constants and functions required for drive control in the form of a table, and outputs them to the calculation unit 507 as appropriate.
  • the calculation unit 507 and the storage unit 508 can employ known configurations, and their processing capabilities can be arbitrarily selected.
  • diodes and switching elements such as thyristors, power transistors, IGBTs, MOSFETs, and the like are used for the switching operations of the boost converter 502, the step-down converter 503, and the inverter 504.
  • gallium oxide (Ga 2 O 3 ) especially corundum-type gallium oxide ( ⁇ -Ga 2 O 3 ), as the material for these semiconductor elements, the switching characteristics are greatly improved. Furthermore, by applying the semiconductor device or the like according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be realized.
  • each of the boost converter 502, the step-down converter 503, and the inverter 504 can expect the effects of the present invention.
  • the effect of the present invention can be expected in any of the above.
  • the control system 500 described above can apply the semiconductor device of the present invention not only to the control system of an electric vehicle, but also to a control system for various purposes such as stepping up or stepping down power from a DC power supply or converting power from DC to AC. can be applied to It is also possible to use a power source such as a solar cell as the battery.
  • FIG. 16 is a block configuration diagram showing another example of a control system employing a semiconductor device according to an embodiment of the present invention
  • FIG. 17 is a circuit diagram of the same control system, showing infrastructure equipment that operates on power from an AC power supply. This control system is suitable for installation in home appliances, etc.
  • a control system 600 receives power supplied from an external, for example, a three-phase AC power source (power source) 601, and includes an AC/DC converter 602, an inverter 604, a motor (to be driven) 605, It has a drive control unit 606, which can be mounted on various devices (described later).
  • the three-phase AC power supply 601 is, for example, a power generation facility of an electric power company (a thermal power plant, a hydroelectric power plant, a geothermal power plant, a nuclear power plant, etc.), and its output is stepped down via a substation and supplied as an AC voltage. be.
  • the AC/DC converter 602 is a voltage conversion device that converts AC voltage into DC voltage, and converts AC voltage of 100V or 200V supplied from the three-phase AC power supply 601 into a predetermined DC voltage. Specifically, the voltage is converted into a generally used desired DC voltage such as 3.3V, 5V, or 12V. When the object to be driven is a motor, conversion to 12V is performed.
  • a single-phase AC power supply may be used instead of the three-phase AC power supply. In that case, the same system configuration can be achieved by using a single-phase input AC/DC converter.
  • the inverter 604 converts the DC voltage supplied from the AC/DC converter 602 into a three-phase AC voltage by switching operation, and outputs the three-phase AC voltage to the motor 605 .
  • the form of the motor 604 differs depending on the object to be controlled. When the object to be controlled is a train, the motor 604 drives the wheels. It is a three-phase AC motor, and is rotationally driven by a three-phase AC voltage output from an inverter 604, and transmits its rotational driving force to a drive target (not shown).
  • the control system 600 does not require the inverter 604, and as shown in FIG. 14, the DC voltage is supplied from the AC/DC converter 602 to the driven object.
  • a personal computer is supplied with a DC voltage of 3.3V
  • an LED lighting device is supplied with a DC voltage of 5V.
  • various sensors are used to measure actual values such as the rotation speed and torque of the driven object, or the temperature and flow rate of the surrounding environment of the driven object, and these measurement signals are input to the drive control unit 606.
  • the output voltage value of inverter 604 is also input to drive control section 606 .
  • drive control section 606 gives a feedback signal to inverter 604 to control the switching operation of the switching element.
  • the AC voltage applied to the motor 605 by the inverter 604 is corrected instantaneously, so that the operation control of the object to be driven can be accurately executed, and the object to be driven can be operated stably.
  • FIG. 17 shows the circuit configuration of FIG.
  • the semiconductor device of the present invention is employed as a Schottky barrier diode in an AC/DC converter 602 and an inverter 604 for switching control.
  • the AC/DC converter 602 uses, for example, a Schottky barrier diode circuit configured in a bridge shape, and performs DC conversion by converting and rectifying the negative voltage component of the input voltage into a positive voltage.
  • the inverter 604 is incorporated in the switching circuit in the IGBT to perform switching control.
  • a capacitor (such as an electrolytic capacitor) is interposed between the AC/DC converter 602 and the inverter 604 to stabilize the voltage.
  • the drive control unit 606 is provided with an operation unit 607 made up of a CPU and a storage unit 608 made up of a non-volatile memory.
  • a signal input to the drive control unit 606 is supplied to the calculation unit 607, and a feedback signal for each semiconductor element is generated by performing necessary calculations.
  • the storage unit 608 also temporarily stores the results of calculations by the calculation unit 607, accumulates physical constants and functions necessary for drive control in the form of a table, and outputs them to the calculation unit 607 as appropriate.
  • the calculation unit 607 and the storage unit 608 can employ known configurations, and their processing capabilities can be arbitrarily selected.
  • the rectifying operation and switching operation of the AC/DC converter 602 and the inverter 604 are performed by diodes, switching elements such as thyristors and power transistors. , IGBT, MOSFET, etc. are used. Switching characteristics are improved by using gallium oxide (Ga 2 O 3 ), particularly corundum type gallium oxide ( ⁇ -Ga 2 O 3 ), as the material for these semiconductor elements. Furthermore, by applying the semiconductor film and the semiconductor device according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be realized. That is, the AC/DC converter 602 and the inverter 604 can each be expected to have the effect of the present invention. can be expected.
  • FIGS. 16 and 17 exemplify the motor 605 as an object to be driven
  • the object to be driven is not necessarily limited to mechanically operating objects, and can be applied to many devices that require AC voltage.
  • the control system 600 as long as the drive object is driven by inputting power from an AC power supply, it can be applied to infrastructure equipment (for example, power equipment such as buildings and factories, communication equipment, traffic control equipment, water and sewage treatment Equipment, system equipment, labor-saving equipment, trains, etc.) and home appliances (e.g., refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.). can.
  • infrastructure equipment for example, power equipment such as buildings and factories, communication equipment, traffic control equipment, water and sewage treatment Equipment, system equipment, labor-saving equipment, trains, etc.
  • home appliances e.g., refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.
  • the semiconductor device of the present invention can be used in various fields such as semiconductors (for example, compound semiconductor electronic devices), electronic parts/electrical equipment parts, optical/electrophotographic equipment, industrial materials, etc., but it is particularly useful for power devices. be.

Abstract

The present invention provides a semiconductor device that has excellent pressure resistance and is particularly useful in power devices. Provided is a semiconductor device which comprises at least a crystalline oxide semiconductor layer (8) including a channel layer (6) and a drift layer (7), a gate electrode (5a) disposed upon the channel layer with a gate insulator film (4a) therebetween, and a current-interrupting layer (2) disposed between the channel layer and the drift layer, wherein: the current-interrupting layer contains a dopant element; and the current-interrupting layer includes a region in which the dopant element concentration is at least 5.0×1017/cm3.

Description

半導体装置semiconductor equipment
　本発明は、パワーデバイス等として有用な半導体装置に関する。 The present invention relates to a semiconductor device useful as a power device or the like.
　酸化ガリウム（Ｇａ２Ｏ３）は、室温において４．８－５．３ｅＶという広いバンドギャップを持ち、可視光及び紫外光をほとんど吸収しない透明半導体である。そのため、特に、深紫外光線領域で動作する光・電子デバイスや透明エレクトロニクスにおいて使用するための有望な材料であり、近年においては、酸化ガリウム（Ｇａ２Ｏ３）を基にした、光検知器、発光ダイオード（ＬＥＤ）及びトランジスタの開発が行われている（非特許文献１参照）。当該酸化ガリウムは特許文献４によると、インジウムやアルミニウムをそれぞれ、あるいは組み合わせて混晶とすることによりバンドギャップ制御することが可能であり、ＩｎＡｌＧａＯ系半導体として極めて魅力的な材料系統を構成している。ここでＩｎＡｌＧａＯ系半導体とはＩｎＸＡｌＹＧａＺＯ３（０≦Ｘ≦２、０≦Ｙ≦２、０≦Ｚ≦２、Ｘ＋Ｙ＋Ｚ＝１．５～２．５）を示し、酸化ガリウムを内包する同一材料系統として俯瞰することができる。 Gallium oxide (Ga 2 O 3 ) is a transparent semiconductor that has a wide bandgap of 4.8-5.3 eV at room temperature and hardly absorbs visible and ultraviolet light. It is therefore a particularly promising material for use in opto - electronic devices and transparent electronics operating in the deep UV region. Light-emitting diodes (LEDs) and transistors have been developed (see Non-Patent Document 1). According to Patent Document 4, the gallium oxide can control the bandgap by forming a mixed crystal of indium and aluminum, respectively or in combination, and constitutes an extremely attractive material system as an InAlGaO-based semiconductor. . Here, the InAlGaO-based semiconductor indicates InXAlYGaZO3 ( 0≦ X ≦2, 0≦ Y ≦2, 0≦Z≦2, X+Y+Z=1.5 to 2.5), and gallium oxide. It can be viewed from a bird's-eye view as the same material system that is included.
　また、酸化ガリウム（Ｇａ２Ｏ３）には、α、β、γ、σ、εの５つの結晶構造が存在し、一般的に最も安定な構造は、β－Ｇａ２Ｏ３である。しかしながら、β－Ｇａ２Ｏ３はβガリア構造であるので、一般に電子材料等で利用する結晶系とは異なり、半導体装置への利用は必ずしも好適ではない。また、β－Ｇａ２Ｏ３薄膜の成長は高い基板温度や高い真空度を必要とするので、製造コストも増大するといった問題もある。また、非特許文献２にも記載されているように、β－Ｇａ２Ｏ３では、高濃度（例えば１×１０１９／ｃｍ３以上）のドーパント（Ｓｉ）でさえも、イオン注入後、８００℃～１１００℃の高温にてアニール処理を施さなければドナーとして使えなかった。
　一方、α－Ｇａ２Ｏ３は、既に汎用されているサファイア基板と同じ結晶構造を有するため、光・電子デバイスへの利用には好適であり、さらに、β－Ｇａ２Ｏ３よりも広いバンドギャップをもつため、パワーデバイスに特に有用であり、そのため、α－Ｇａ２Ｏ３を半導体として用いた半導体装置が待ち望まれている状況である。 Gallium oxide (Ga 2 O 3 ) has five crystal structures α, β, γ, σ, and ε, and generally the most stable structure is β-Ga 2 O 3 . However, since β-Ga 2 O 3 has a β-Gallic structure, it is not necessarily suitable for use in semiconductor devices, unlike crystal systems generally used in electronic materials and the like. In addition, since the growth of the β-Ga 2 O 3 thin film requires a high substrate temperature and a high degree of vacuum, there is also the problem of increased manufacturing costs. In addition, as described in Non-Patent Document 2, in β-Ga 2 O 3 , even a high concentration (for example, 1×10 19 /cm 3 or more) of dopant (Si) is 800% after ion implantation. C. to 1100.degree. C., it could not be used as a donor without annealing.
On the other hand, α-Ga 2 O 3 has the same crystal structure as the sapphire substrate that has already been widely used, so it is suitable for use in optoelectronic devices, and has a wider band than β-Ga 2 O 3 . Since it has a gap, it is particularly useful for power devices. Therefore, semiconductor devices using α-Ga 2 O 3 as a semiconductor are eagerly awaited.
　特許文献１には、ドナーを含むＧａ２Ｏ３系結晶層と、前記Ｇａ２Ｏ３系結晶層の少なくとも一部に形成されたＮ添加領域とを有し、前記Ｎ添加領域が、チャネル領域を含む又は電流経路となる開口領域を有する電流遮断領域である縦型ＭＯＳＦＥＴが開示されている。しかしながら、実際に縦型ＭＯＳＦＥＴとして動作することは確認されておらず、また、耐圧等の信頼性においても十分に満足できるようなものではなかった。 Patent Document 1 discloses a Ga 2 O 3 -based crystal layer containing donors and an N-doped region formed in at least a part of the Ga 2 O 3 -based crystal layer, wherein the N-doped region is a channel region. A vertical MOSFET is disclosed that is a current blocking region that includes or has an open region that provides a current path. However, it has not been confirmed that it actually operates as a vertical MOSFET, and its reliability such as withstand voltage is not sufficiently satisfactory.
特開２０１８－１８６２４６号公報JP 2018-186246 A
　本発明は、耐圧に優れた半導体装置を提供することを目的とする。 An object of the present invention is to provide a semiconductor device with excellent withstand voltage.
　本発明者らは、上記目的を達成すべく鋭意検討した結果、チャネル層およびドリフト層を含む結晶性酸化物半導体層と、該チャネル層上にゲート絶縁膜を介して配置されているゲート電極と、前記チャネル層と前記ドリフト層との間に配置されている電流遮断層とを少なくとも備える半導体装置であって、前記電流遮断層がドーパント元素を含有し、前記電流遮断層中に、前記ドーパント元素の濃度が５．０×１０１７／ｃｍ３以上である領域を含む半導体装置が、このような電流遮断層を有しない構造と比較して耐圧性が向上されたものとなることを見出し、このようにして得られた半導体装置が、上記した従来の問題を解決できるものであることを見出した。
　また、本発明者らは、上記知見を得た後、さらに検討を重ねて本発明を完成させるに至った。 As a result of intensive studies to achieve the above object, the present inventors have found that a crystalline oxide semiconductor layer including a channel layer and a drift layer and a gate electrode disposed on the channel layer with a gate insulating film interposed therebetween. and a current blocking layer disposed between the channel layer and the drift layer, wherein the current blocking layer contains a dopant element, and the current blocking layer contains the dopant element concentration of 5.0×10 17 /cm 3 or more has improved withstand voltage compared to a structure without such a current blocking layer. It has been found that the semiconductor device thus obtained can solve the conventional problems described above.
Moreover, after obtaining the above knowledge, the inventors of the present invention completed the present invention through further studies.
　すなわち、本発明は、以下の発明に関する。
［１］　チャネル層およびドリフト層を含む結晶性酸化物半導体層と、該チャネル層上にゲート絶縁膜を介して配置されているゲート電極と、前記チャネル層と前記ドリフト層との間に配置されている電流遮断層とを少なくとも備える半導体装置であって、前記電流遮断層がドーパント元素を含有し、前記電流遮断層中に、前記ドーパント元素の濃度が５．０×１０１７／ｃｍ３以上である領域を含むことを特徴とする半導体装置。
［２］　前記ドーパント元素が、ｐ型ドーパントの元素である前記［１］記載の半導体装置。
［３］　前記電流遮断層中の前記ドーパント元素の濃度が１．０×１０１８／ｃｍ３以上である前記［１］または［２］に記載の半導体装置。
［４］　前記電流遮断層中の前記ドーパント元素の濃度が５．０×１０１７／ｃｍ３以上である領域の厚みが２００ｎｍ以上である前記［１］～［３］のいずれかに記載の半導体装置。
［５］　前記ドーパント元素がイオン注入によってドーピングされている前記［１］～［４］のいずれかに記載の半導体装置。
［６］　前記電流遮断層が、結晶性酸化物を主成分として含む前記［１］～［５］のいずれかに記載の半導体装置。
［７］　前記チャネル層の少なくとも一部にソース領域を有しており、前記ソース領域上にソース電極を備えている前記［１］～［６］のいずれかに記載の半導体装置。
［８］　前記ソース電極が、前記電流遮断層とコンタクトを形成している前記［１］～［７］のいずれかに記載の半導体装置。
［９］　前記結晶性酸化物半導体層が、少なくとも前記チャネル層を貫通するトレンチを有しており、該トレンチ内に前記ゲート電極の少なくとも一部が前記ゲート絶縁膜を介して埋め込まれている前記［１］～［８］のいずれかに記載の半導体装置。
［１０］　前記結晶性酸化物半導体層が、アルミニウム、インジウムおよびガリウムから選ばれる少なくとも１種の金属を含有する前記［１］～［９］のいずれかに記載の半導体装置。
［１１］　前記結晶性酸化物半導体層が、コランダム構造を有する前記［１］～［１０］のいずれかに記載の半導体装置。
［１２］　トランジスタである前記［１］～［１１］のいずれかに記載の半導体装置。
［１３］　前記［１］～［１２］のいずれかに記載の半導体装置を用いた電力変換装置。
［１４］　前記［１］～［１２］のいずれかに記載の半導体装置を用いた制御システム。 Specifically, the present invention relates to the following inventions.
[1] A crystalline oxide semiconductor layer including a channel layer and a drift layer, a gate electrode disposed on the channel layer with a gate insulating film interposed therebetween, and a gate electrode disposed between the channel layer and the drift layer wherein the current blocking layer contains a dopant element, and the concentration of the dopant element in the current blocking layer is 5.0×10 17 /cm 3 or more. A semiconductor device comprising a region.
[2] The semiconductor device according to [1], wherein the dopant element is a p-type dopant element.
[3] The semiconductor device according to [1] or [2], wherein the concentration of the dopant element in the current blocking layer is 1.0×10 18 /cm 3 or more.
[4] The semiconductor according to any one of [1] to [3], wherein the thickness of the region in the current blocking layer where the concentration of the dopant element is 5.0×10 17 /cm 3 or more is 200 nm or more. Device.
[5] The semiconductor device according to any one of [1] to [4], wherein the dopant element is doped by ion implantation.
[6] The semiconductor device according to any one of [1] to [5], wherein the current blocking layer contains a crystalline oxide as a main component.
[7] The semiconductor device according to any one of [1] to [6], wherein at least part of the channel layer has a source region, and a source electrode is provided on the source region.
[8] The semiconductor device according to any one of [1] to [7], wherein the source electrode forms a contact with the current blocking layer.
[9] The crystalline oxide semiconductor layer has a trench penetrating at least the channel layer, and at least part of the gate electrode is embedded in the trench via the gate insulating film. The semiconductor device according to any one of [1] to [8].
[10] The semiconductor device according to any one of [1] to [9], wherein the crystalline oxide semiconductor layer contains at least one metal selected from aluminum, indium and gallium.
[11] The semiconductor device according to any one of [1] to [10], wherein the crystalline oxide semiconductor layer has a corundum structure.
[12] The semiconductor device according to any one of [1] to [11], which is a transistor.
[13] A power converter using the semiconductor device according to any one of [1] to [12].
[14] A control system using the semiconductor device according to any one of [1] to [12].
　本発明によれば、耐圧性に優れた半導体装置を提供することができる。 According to the present invention, a semiconductor device with excellent pressure resistance can be provided.
本発明の実施態様にかかる金属酸化膜半導体電界効果トランジスタ（ＭＯＳＦＥＴ）を模式的に示す図である。1 schematically illustrates a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the invention; FIG. 本発明の実施態様にかかる金属酸化膜半導体電界効果トランジスタ（ＭＯＳＦＥＴ）の好適な製造工程を模式的に示す図である。1 schematically illustrates a preferred manufacturing process for a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention; FIG. 本発明の実施態様にかかる金属酸化膜半導体電界効果トランジスタ（ＭＯＳＦＥＴ）の好適な製造工程を模式的に示す図である。1 schematically illustrates a preferred manufacturing process for a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention; FIG. 本発明の実施態様にかかる金属酸化膜半導体電界効果トランジスタ（ＭＯＳＦＥＴ）を模式的に示す図である。1 schematically illustrates a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the invention; FIG. 実施例におけるＳＩＭＳ（二次イオン質量分析）測定結果を示す図である。It is a figure which shows the SIMS (secondary ion mass spectrometry) measurement result in an Example. 実施例におけるＳＩＭＳ（二次イオン質量分析）測定結果を示す図である。It is a figure which shows the SIMS (secondary ion mass spectrometry) measurement result in an Example. 実施例および比較例におけるＩ－Ｖ測定の結果を示す図である。FIG. 4 is a diagram showing the results of IV measurements in Examples and Comparative Examples. 実施例におけるＩ－Ｖ測定の結果を示す図である。FIG. 4 is a diagram showing results of IV measurement in Examples. 本発明の実施態様にかかる金属酸化膜半導体電界効果トランジスタ（ＭＯＳＦＥＴ）を模式的に示す図である。1 schematically illustrates a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the invention; FIG. 本発明の実施態様にかかる金属酸化膜半導体電界効果トランジスタ（ＭＯＳＦＥＴ）を模式的に示す図である。1 schematically illustrates a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the invention; FIG. 本発明の実施態様にかかる金属酸化膜半導体電界効果トランジスタ（ＭＯＳＦＥＴ）の好適な製造工程を模式的に示す図である。1 schematically illustrates a preferred manufacturing process for a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention; FIG. 本発明の実施態様にかかる金属酸化膜半導体電界効果トランジスタ（ＭＯＳＦＥＴ）の好適な製造工程を模式的に示す図である。1 schematically illustrates a preferred manufacturing process for a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention; FIG. 本発明の実施態様において用いられるミストＣＶＤ装置の構成図である。1 is a configuration diagram of a mist CVD apparatus used in an embodiment of the present invention; FIG. 本発明の実施態様にかかる半導体装置を採用した制御システムの一例を示すブロック構成図である。1 is a block configuration diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention; FIG. 本発明の実施態様にかかる半導体装置を採用した制御システムの一例を示す回路図である。1 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention; FIG. 本発明の実施態様にかかる半導体装置を採用した制御システムの一例を示すブロック構成図である。1 is a block configuration diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention; FIG. 本発明の実施態様にかかる半導体装置を採用した制御システムの一例を示す回路図である。1 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention; FIG.
　本発明の実施態様にかかる半導体装置は、チャネル層およびドリフト層を含む結晶性酸化物半導体層と、該チャネル層上にゲート絶縁膜を介して配置されているゲート電極と、前記チャネル層と前記ドリフト層との間に配置されている電流遮断層とを少なくとも備える半導体装置であって、前記電流遮断層がドーパント元素を含有し、前記電流遮断層中に、前記ドーパント元素の濃度が５．０×１０１７／ｃｍ３以上である領域を含むことを特長とする。 A semiconductor device according to an embodiment of the present invention includes a crystalline oxide semiconductor layer including a channel layer and a drift layer, a gate electrode disposed on the channel layer with a gate insulating film interposed therebetween, the channel layer and the A semiconductor device comprising at least a current blocking layer disposed between a drift layer and a drift layer, wherein the current blocking layer contains a dopant element, and the concentration of the dopant element in the current blocking layer is 5.0. It is characterized by including a region having a density of 10 17 /cm 3 or more.
　前記結晶性酸化物半導体層は、本発明の目的を阻害しない限り、特に限定されない。本発明の実施態様においては、前記結晶性酸化物半導体層が、結晶性酸化物半導体を主成分として含むのが好ましい。前記結晶性酸化物半導体としては、例えば、アルミニウム、ガリウム、インジウム、鉄、クロム、バナジウム、チタン、ロジウム、ニッケル、コバルトおよびイリジウムから選ばれる１種または２種以上の金属を含む金属酸化物などがあげられる。本発明の実施態様においては、前記結晶性酸化物半導体層が、アルミニウム、インジウムおよびガリウムから選ばれる少なくとも１種の金属を含有するのが好ましく、少なくともガリウムを含むのがより好ましく、α－Ｇａ２Ｏ３またはその混晶であるのが最も好ましい。本発明の実施態様によれば、例えば酸化ガリウムまたはその混晶等のバンドギャップの大きい半導体を含む半導体装置であっても、絶縁耐圧を向上させることができる。前記結晶性酸化物半導体層の結晶構造も、本発明の目的を阻害しない限り、特に限定されない。前記結晶性酸化物半導体層の結晶構造としては、例えば、コランダム構造、β－ガリア構造、六方晶構造（例えば、ε型構造等）、直方晶構造（例えばκ型構造等）、立方晶構造、または正方晶構造等が挙げられる。本発明の実施態様においては、前記結晶性酸化物半導体層が、コランダム構造、β－ガリア構造または六方晶構造（例えば、ε型構造等）を有するのが好ましく、コランダム構造を有するのがより好ましい。なお、「主成分」とは、前記結晶性酸化物半導体が、原子比で、前記結晶性酸化物半導体層の全成分に対し、好ましくは５０％以上、より好ましくは７０％以上、さらにより好ましくは９０％以上含まれることを意味し、１００％であってもよいことを意味する。例えば、前記結晶性酸化物半導体が酸化ガリウムである場合、前記結晶性酸化物半導体層中に含まれる全ての金属元素中のガリウムの原子比が０．５以上の割合で前記結晶性酸化物半導体層中に結晶性酸化物半導体としての酸化ガリウムが含まれていればそれでよい。前記結晶性酸化物半導体層中に含まれる全ての金属元素中のガリウムの原子比は、０．７以上であるのが好ましく、０．９以上であるのがより好ましい。また、前記結晶性酸化物半導体層の厚さは、特に限定されず、１μｍ以下であってもよいし、１μｍ以上であってもよいが、本発明の実施態様においては、５μｍ以上であるのが好ましく、１０μｍ以上であるのがより好ましい。前記半導体膜の（平面視における）表面積は特に限定されないが、１ｍｍ２以上であってもよいし、１ｍｍ２以下であってもよいが、１０ｍｍ２～３００ｍｍ２であるのが好ましく、１０ｍｍ２～１００ｍｍ２であるのがより好ましい。また、前記結晶性酸化物半導体層は、通常、単結晶であるが、多結晶であってもよい。また、前記結晶性酸化物半導体層は、通常、２以上の半導体層を含んでいる。前記結晶性酸化物半導体層は、例えば、ｎ＋型半導体層、ドリフト層（ｎ－型半導体層）、チャネル層、およびソース領域（ｎ＋型半導体層）を少なくとも含む。また、前記結晶性酸化物半導体層のキャリア密度は、ドーピング量を調節することにより、適宜設定することができる。 The crystalline oxide semiconductor layer is not particularly limited as long as it does not hinder the object of the present invention. In an embodiment of the present invention, the crystalline oxide semiconductor layer preferably contains a crystalline oxide semiconductor as a main component. Examples of the crystalline oxide semiconductor include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt and iridium. can give. In an embodiment of the present invention, the crystalline oxide semiconductor layer preferably contains at least one metal selected from aluminum, indium and gallium, more preferably at least gallium, and α-Ga 2 Most preferred is O3 or mixed crystals thereof. According to the embodiments of the present invention, it is possible to improve the withstand voltage even in a semiconductor device including a semiconductor having a large bandgap such as gallium oxide or a mixed crystal thereof. The crystal structure of the crystalline oxide semiconductor layer is also not particularly limited as long as the object of the present invention is not hindered. The crystal structure of the crystalline oxide semiconductor layer includes, for example, a corundum structure, a β-gallia structure, a hexagonal crystal structure (eg, ε-type structure, etc.), an orthogonal crystal structure (eg, κ-type structure, etc.), a cubic crystal structure, Alternatively, a tetragonal crystal structure or the like can be mentioned. In the embodiment of the present invention, the crystalline oxide semiconductor layer preferably has a corundum structure, a β-gallia structure or a hexagonal crystal structure (e.g., ε-type structure, etc.), and more preferably has a corundum structure. . Note that the “main component” means that the crystalline oxide semiconductor accounts for preferably 50% or more, more preferably 70% or more, and even more preferably 70% or more, in atomic ratio, of all components of the crystalline oxide semiconductor layer. means that the content is 90% or more, and may be 100%. For example, when the crystalline oxide semiconductor is gallium oxide, the crystalline oxide semiconductor has an atomic ratio of gallium in all metal elements contained in the crystalline oxide semiconductor layer of 0.5 or more. It is sufficient if the layer contains gallium oxide as a crystalline oxide semiconductor. The atomic ratio of gallium in all metal elements contained in the crystalline oxide semiconductor layer is preferably 0.7 or more, more preferably 0.9 or more. The thickness of the crystalline oxide semiconductor layer is not particularly limited, and may be 1 μm or less or 1 μm or more. is preferred, and 10 µm or more is more preferred. The surface area (in plan view) of the semiconductor film is not particularly limited, but may be 1 mm 2 or more or 1 mm 2 or less, preferably 10 mm 2 to 300 mm 2 , and preferably 10 mm 2 to 300 mm 2 . More preferably 100 mm 2 . Further, the crystalline oxide semiconductor layer is usually single crystal, but may be polycrystal. Moreover, the crystalline oxide semiconductor layer usually includes two or more semiconductor layers. The crystalline oxide semiconductor layer includes, for example, at least an n+ type semiconductor layer, a drift layer (n− type semiconductor layer), a channel layer, and a source region (n+ type semiconductor layer). Further, the carrier density of the crystalline oxide semiconductor layer can be appropriately set by adjusting the doping amount.
　前記結晶性酸化物半導体層は、ドーパントを含むのが好ましい。前記ドーパントは、特に限定されず、公知のものであってよい。本発明の実施形態においては、特に、前記半導体層がガリウムを含む結晶性酸化物を主成分とする場合、前記ドーパントの好適な例としては、例えば、スズ、ゲルマニウム、ケイ素、チタン、ジルコニウム、バナジウムまたはニオブ等のｎ型ドーパント、またはＭｇ、Ｈ、Ｌｉ、Ｎａ、Ｋ、Ｒｂ、Ｃｓ、Ｆｒ、Ｂｅ、Ｃａ、Ｓｒ、Ｂａ、Ｒａ、Ｍｎ、Ｆｅ、Ｃｏ、Ｎｉ、Ｐｄ、Ｃｕ、Ａｇ、Ａｕ、Ｚｎ、Ｃｄ、Ｈｇ、Ｔｉ、Ｐｂ、Ｎ、もしくはＰ等のｐ型ドーパントなどが挙げられる。本発明の実施態様においては、前記ｎ型ドーパントが、Ｓｎ、ＧｅおよびＳｉから選ばれる少なくとも１種であるのが好ましい。ドーパントの含有量は、前記半導体層の組成中、０．００００１原子％以上であるのが好ましく、０．００００１原子％～２０原子％であるのがより好ましく、０．００００１原子％～１０原子％であるのが最も好ましい。より具体的には、ドーパントの濃度は、通常、約１×１０１６／ｃｍ３～１×１０２２／ｃｍ３であってもよいし、また、ドーパントの濃度を例えば約１×１０１７／ｃｍ３以下の低濃度にしてもよい。また、さらに、本発明によれば、ドーパントを約１×１０２０／ｃｍ３以上の高濃度で含有させてもよい。 The crystalline oxide semiconductor layer preferably contains a dopant. The dopant is not particularly limited and may be a known one. In the embodiment of the present invention, particularly when the semiconductor layer is mainly composed of a crystalline oxide containing gallium, suitable examples of the dopant include tin, germanium, silicon, titanium, zirconium and vanadium. or n-type dopants such as niobium, or Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au , Zn, Cd, Hg, Ti, Pb, N, or P, and the like. In an embodiment of the present invention, the n-type dopant is preferably at least one selected from Sn, Ge and Si. The content of the dopant is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and more preferably 0.00001 atomic % to 10 atomic % in the composition of the semiconductor layer. is most preferred. More specifically, the dopant concentration may typically be about 1×10 16 /cm 3 to 1×10 22 /cm 3 , and the dopant concentration may be, for example, about 1×10 17 /cm 3 . A low concentration of 3 or less may be used. Further, according to the present invention, the dopant may be contained at a high concentration of about 1×10 20 /cm 3 or higher.
　本発明の実施態様においては、前記結晶性酸化物半導体層は、チャネル層を含み、該チャネル層上に前記ゲート絶縁膜を介してゲート電極が配置されている。前記チャネル層の構成材料は、上記した前記結晶性酸化物半導体層の構成材料と同様であってよい。また、前記チャネル層の導電型も、特に限定されず、ｎ型であってもよいし、ｐ型であってもよい。前記チャネル層の導電型がｎ型である場合、前記チャネル層の構成材料としては、好適には、例えば、α－Ｇａ２Ｏ３またはその混晶等が挙げられる。また、前記チャネル層の導電型がｐ型である場合、前記チャネル層の構成材料としては、好適には、例えば、ｐ型ドーパントを含むα－Ｇａ２Ｏ３またはその混晶、周期律表第６族から選ばれる少なくとも１種の金属を含む金属酸化物（例えば、α－Ｃｒ２Ｏ３等）、周期律表第９族から選ばれる少なくとも１種の金属を含む金属酸化物（例えば、α－Ｉｒ２Ｏ３、α－Ｃｒ２Ｏ３、α－Ｒｈ２Ｏ３）等が挙げられる。なお、周期律表第６族から選ばれる少なくとも１種の金属を含む金属酸化物または周期律表第９族から選ばれる少なくとも１種の金属を含む金属酸化物は、他の金属酸化物（例えばＧａ２Ｏ３）との混晶であってもよい。 In an embodiment of the present invention, the crystalline oxide semiconductor layer includes a channel layer, and a gate electrode is arranged on the channel layer with the gate insulating film interposed therebetween. The constituent material of the channel layer may be the same as the constituent material of the crystalline oxide semiconductor layer described above. Also, the conductivity type of the channel layer is not particularly limited, and may be n-type or p-type. When the conductivity type of the channel layer is the n-type, preferable examples of the constituent material of the channel layer include α-Ga 2 O 3 and mixed crystals thereof. In addition, when the conductivity type of the channel layer is p-type, the constituent material of the channel layer is preferably, for example, α-Ga 2 O 3 containing a p-type dopant or a mixed crystal thereof. Metal oxides containing at least one metal selected from Group 6 (eg, α-Cr 2 O 3 etc.), Metal oxides containing at least one metal selected from Group 9 of the periodic table (eg, α -Ir 2 O 3 , α-Cr 2 O 3 , α-Rh 2 O 3 ) and the like. The metal oxide containing at least one metal selected from Group 6 of the periodic table or the metal oxide containing at least one metal selected from Group 9 of the periodic table may be other metal oxides (e.g. Ga 2 O 3 ) may be a mixed crystal.
　前記ゲート絶縁膜（層間絶縁膜）の構成材料は、特に限定されず、公知の材料であってよい。前記ゲート絶縁膜の材料としては、例えば、ＳｉＯ２膜、リン添加ＳｉＯ２膜（ＰＳＧ膜）、ボロン添加ＳｉＯ２膜、リンーボロン添加ＳｉＯ２膜（ＢＰＳＧ膜）等が挙げられる。前記ゲート絶縁膜の形成方法としては、例えば、ＣＶＤ法、大気圧ＣＶＤ法、プラズマＣＶＤ法、ミストＣＶＤ法等が挙げられる。本発明の実施態様においては、前記ゲート絶縁膜の形成方法が、ミストＣＶＤ法または大気圧ＣＶＤ法であるのが好ましい。また、前記ゲート電極の構成材料は、特に限定されず、公知の電極材料であってよい。前記ゲート電極の構成材料としては、例えば、上記した前記ソース電極の構成材料等が挙げられる。前記ゲート電極の形成方法は、特に限定されない。前記ゲート電極の形成方法としては、具体的には例えば、ドライ法やウェット法などが挙げられる。ドライ法としては、例えば、スパッタ、真空蒸着、ＣＶＤ等が挙げられる。ウェット法としては、例えば、スクリーン印刷やダイコート等が挙げられる。 A constituent material of the gate insulating film (interlayer insulating film) is not particularly limited, and may be a known material. Examples of the material of the gate insulating film include SiO 2 film, phosphorus-added SiO 2 film (PSG film), boron-added SiO 2 film, phosphorus-boron-added SiO 2 film (BPSG film), and the like. Examples of methods for forming the gate insulating film include CVD, atmospheric pressure CVD, plasma CVD, mist CVD, and the like. In an embodiment of the present invention, the method for forming the gate insulating film is preferably mist CVD or atmospheric pressure CVD. Further, the constituent material of the gate electrode is not particularly limited, and may be a known electrode material. Examples of the constituent material of the gate electrode include the constituent materials of the source electrode described above. A method for forming the gate electrode is not particularly limited. Specific examples of the method for forming the gate electrode include a dry method and a wet method. Dry methods include, for example, sputtering, vacuum deposition, and CVD. Wet methods include, for example, screen printing and die coating.
　前記ドリフト層の構成材料としては、例えば、上記した前記結晶性酸化物半導体層の構成材料が挙げられる。本発明の実施態様においては、前記ドリフト層が、結晶性酸化物半導体を主成分として含むのが好ましい。また、前記結晶性酸化物半導体は。アルミニウム、インジウムおよびガリウムから選ばれる少なくとも１種の金属を含有するのが好ましく、少なくともガリウムを含むのがより好ましく、α－Ｇａ２Ｏ３またはその混晶であるのが最も好ましい。また、本発明の実施態様においては、前記ドリフト層の導電型はｎ型であるのが好ましい。本発明の実施態様においては、電流遮断層として上記した好ましい電流遮断層を用いるので、酸化ガリウムまたはその混晶等のバンドギャップの大きい酸化物半導体をドリフト層に用いた場合であっても、本来の機能を半導体装置（ＭＯＳＦＥＴ等）において好適に発揮させることができる。 Examples of the constituent material of the drift layer include the constituent materials of the crystalline oxide semiconductor layer described above. In an embodiment of the present invention, the drift layer preferably contains a crystalline oxide semiconductor as a main component. Further, the crystalline oxide semiconductor is: It preferably contains at least one metal selected from aluminum, indium and gallium, more preferably at least gallium, and most preferably α-Ga 2 O 3 or a mixed crystal thereof. Moreover, in the embodiment of the present invention, the conductivity type of the drift layer is preferably n-type. In the embodiment of the present invention, the preferred current blocking layer described above is used as the current blocking layer. function can be suitably exhibited in a semiconductor device (such as a MOSFET).
　前記電流遮断層は、前記半導体装置内において、前記チャネル層と前記ドリフト層との間に設けられているものであって、ドーパント元素を含有し、前記電流遮断層中に、前記ドーパント元素の濃度が５．０×１０１７／ｃｍ３以上である領域を含むものであれば、特に限定されない。本発明の実施態様においては、前記電流遮断層が、前記ドリフト層内に設けられてもよいし、前記ドリフト層上に設けられていてもよい。前記ドーパント元素は、イオン注入によって前記電流遮断層中に導入されていてもよいし、エピタキシャル成長により前記電流遮断層中に導入されていてもよい。なお、イオン注入のプロファイルは、特に限定されない。本発明の実施態様においては、イオン注入がボックスプロファイルとなるように行われているのが好ましい。このような好ましい構成とすることにより、前記電流遮断領域におけるリーク電流をより低減することができる。イオン注入において注入される元素は、特に限定されない。前記ドーパント元素としては、例えば、Ｓｎ、Ｇｅ、Ｓｉ、Ｔｉ、Ｚｒ、Ｖ、Ｎｂ、Ｍｇ、Ｈ、Ｌｉ、Ｎａ、Ｋ、Ｒｂ、Ｃｓ、Ｆｒ、Ｂｅ、Ｃａ、Ｓｒ、Ｂａ、Ｒａ、Ｍｎ、Ｆｅ、Ｃｏ、Ｎｉ、Ｐｄ、Ｃｕ、Ａｇ、Ａｕ、Ｚｎ、Ｃｄ、Ｈｇ、Ｔｉ、Ｐｂ、ＡｌおよびＮ等などが挙げられる。前記電流遮断層中に含まれる前記ドーパント元素濃度は、好ましくは、１，０×１０１８／ｃｍ３以上である。本発明の実施態様においては、前記電流遮断層中の前記ドーパント元素の濃度が５．０×１０１７／ｃｍ３以上である領域の厚みが２００ｎｍ以上であるのが好ましい。このような好ましい構成とすることにより、耐圧性の向上効果をより促進させることができる。また、本発明の実施態様においては、前記ドーパント元素がエピタキシャル成長により前記電流遮断層中に導入されている場合、前記ドーパント元素は好ましくは、Ｍｇ、Ｈ、Ｌｉ、Ｎａ、Ｋ、Ｒｂ、Ｃｓ、Ｆｒ、Ｂｅ、Ｃａ、Ｓｒ、Ｂａ、Ｒａ、Ｍｎ、Ｆｅ、Ｃｏ、Ｎｉ、Ｐｄ、Ｃｕ、Ａｇ、Ａｕ、Ｚｎ、Ｃｄ、Ｈｇ、Ｔｉ、Ｐｂ、Ｎ、もしくはＰ等のｐ型ドーパントであり、より好ましくは、Ｍｇである。 The current blocking layer is provided between the channel layer and the drift layer in the semiconductor device, contains a dopant element, and the concentration of the dopant element in the current blocking layer is is not particularly limited as long as it includes a region in which is 5.0×10 17 /cm 3 or more. In an embodiment of the present invention, the current blocking layer may be provided within the drift layer or may be provided on the drift layer. The dopant element may be introduced into the current blocking layer by ion implantation, or may be introduced into the current blocking layer by epitaxial growth. Note that the ion implantation profile is not particularly limited. In embodiments of the present invention, the ion implantation is preferably performed with a box profile. By adopting such a preferable configuration, it is possible to further reduce the leakage current in the current blocking region. Elements to be implanted in ion implantation are not particularly limited. Examples of the dopant elements include Sn, Ge, Si, Ti, Zr, V, Nb, Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, Al, N and the like. The dopant element concentration contained in the current blocking layer is preferably 1.0×10 18 /cm 3 or more. In an embodiment of the present invention, it is preferable that the thickness of the region where the concentration of the dopant element in the current blocking layer is 5.0×10 17 /cm 3 or more is 200 nm or more. By adopting such a preferable configuration, the effect of improving pressure resistance can be further promoted. Further, in the embodiment of the present invention, when the dopant element is introduced into the current blocking layer by epitaxial growth, the dopant element is preferably Mg, H, Li, Na, K, Rb, Cs, Fr , Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, or P, and more Mg is preferred.
　前記ソース領域は、ｎ＋型半導体層を含むものであれば、特に限定されない。本発明の実施態様においては、前記ソース領域が、ｎ＋型半導体層、および該ｎ＋型半導体層上に配置されており該ｎ＋型半導体層よりもキャリア密度が大きいｎ＋＋型半導体層を少なくとも含むのが好ましい。なお、キャリア密度は、公知の方法を用いて求めることができる。前記キャリア密度を求める方法としては、例えば、ＳＩＭＳ（二次イオン質量分析法）、ＳＣＭ（走査型静電容量顕微鏡法）、ＳＭＭ（走査型マイクロ波顕微鏡法）、およびＳＲＡ（広がり抵抗測定法）等が挙げられる。前記ｎ＋型半導体層の主成分と、前記ｎ＋＋型半導体層の主成分とは同じであってもよいし、異なっていてもよい。本発明の実施態様においては、前記ｎ＋型半導体層の主成分と前記ｎ＋＋型半導体層の主成分とが同じであるのが好ましい。また、本発明の実施態様においては、前記ｎ＋型半導体層と前記ｎ＋＋型半導体層とが同じ結晶構造を有しているのが好ましく、前記ｎ＋型半導体層と前記ｎ＋＋型半導体層とがコランダム構造を有しているのがより好ましい。なお、ここで、「主成分」とは、例えば、前記ｎ＋型半導体層の主成分が酸化ガリウムである場合、前記ｎ＋型半導体層中の全ての金属元素中におけるガリウムの原子比が５０％以上の割合で含まれていればそれでよい。本発明の実施態様においては、前記ｎ＋型半導体層中の全ての金属元素中におけるガリウムの原子比が好ましくは７０％以上、更に好ましくは９０％以上含まれ、１００％であってもよい。本発明の実施態様においては、前記ｎ＋＋型半導体層が、エピタキシャル層であるのが好ましく、前記ｎ＋＋型半導体層がエピタキシャルドーピングされているのがより好ましい。上記したような好ましい前記ｎ＋＋型半導体層を用いることにより、コンタクト抵抗をより良好に低減することができる。ここで、エピタキシャルドーピングとは、例えば、イオン注入等によるドーピングではなく、エピタキシャル成長によってドーピングされていることをいう。前記ｎ＋型半導体層および／または前記ｎ＋＋型半導体層中に含まれるｎ型ドーパントとしては、例えば、スズ、ゲルマニウム、ケイ素、チタン、ジルコニウム、バナジウムおよびニオブから選ばれる少なくとも１種のｎ型ドーパント等が挙げられる。本発明の実施態様においては、前記ｎ型ドーパントが、Ｓｎ、ＧｅおよびＳｉから選ばれる少なくとも１種であるのが好ましい。前記ｎ＋＋型半導体層のキャリア密度は、前記ｎ＋型半導体層のキャリア密度よりも大きければ、特に限定されない。本発明の実施態様においては、前記ｎ＋＋型半導体層のキャリア密度が、１．０×１０１９／ｃｍ３以上であるのが好ましく、６．０×１０１９／ｃｍ３以上であるのがより好ましい。前記ｎ＋＋型半導体層のキャリア密度をこのような好ましい値とすることにより、コンタクト抵抗をより良好に低減することができる。また、前記ｎ＋型半導体層のキャリア密度も、特に限定されない。本発明の実施態様においては、前記ｎ＋型半導体層のキャリア密度が、１．０×１０１７／ｃｍ３以上１．０×１０１９／ｃｍ３未満の範囲内であるのが好ましい。前記ｎ＋型半導体層のキャリア密度を上記のような好ましい範囲とすることにより、ソース抵抗をより良好に低減することができる。なお、本発明の実施態様においては、前記ｎ＋型半導体層へのドーピング方法は、特に限定されず、拡散またはイオン注入であってもよいし、エピタキシャル成長法であってもよい。本発明の実施態様においては、前記ｎ＋型半導体層の移動度が前記ｎ＋＋型半導体層の移動度よりも大きいのが好ましい。前記ｎ＋＋型半導体層の厚みは、本発明の目的を阻害しない限り、特に限定されない。本発明の実施態様においては、前記ｎ＋＋型半導体層の厚みが、１ｎｍ～１μｍの範囲内であるのが好ましく、１０ｎｍ～１００ｎｍの範囲内であるのがより好ましい。本発明の実施態様においては、前記ｎ＋型半導体層の厚みが、前記ｎ＋＋型半導体層の厚みよりも大きいのが好ましい。前記ｎ＋型半導体層および前記ｎ＋＋型半導体層を上記した好ましい組合せとすることにより、前記半導体装置におけるソースコンタクト抵抗およびソース抵抗をより良好に低減することができるので、より素子抵抗が低減された前記半導体装置を実現することができる。 The source region is not particularly limited as long as it includes an n+ type semiconductor layer. In an embodiment of the present invention, the source region includes at least an n + -type semiconductor layer and an n++ -type semiconductor layer disposed on the n + -type semiconductor layer and having a higher carrier density than the n + -type semiconductor layer. preferable. Note that the carrier density can be determined using a known method. Examples of methods for determining the carrier density include SIMS (secondary ion mass spectrometry), SCM (scanning capacitance microscopy), SMM (scanning microwave microscopy), and SRA (spreading resistance measurement). etc. The main component of the n+ type semiconductor layer and the main component of the n++ type semiconductor layer may be the same or different. In an embodiment of the present invention, it is preferable that the main component of the n + -type semiconductor layer and the main component of the n++ -type semiconductor layer are the same. Further, in the embodiment of the present invention, it is preferable that the n + type semiconductor layer and the n ++ type semiconductor layer have the same crystal structure, and the n + type semiconductor layer and the n ++ type semiconductor layer have a corundum structure. It is more preferable to have Here, the “main component” means, for example, when the main component of the n + type semiconductor layer is gallium oxide, the atomic ratio of gallium in all metal elements in the n + type semiconductor layer is 50% or more. If it is included in the ratio of In an embodiment of the present invention, the atomic ratio of gallium in all metal elements in the n + -type semiconductor layer is preferably 70% or more, more preferably 90% or more, and may be 100%. In an embodiment of the present invention, the n++ type semiconductor layer is preferably an epitaxial layer, and more preferably the n++ type semiconductor layer is epitaxially doped. By using the above-described preferable n++ type semiconductor layer, the contact resistance can be reduced more satisfactorily. Here, epitaxial doping means doping by epitaxial growth, not doping by ion implantation or the like. Examples of the n-type dopant contained in the n + -type semiconductor layer and/or the n++-type semiconductor layer include at least one n-type dopant selected from tin, germanium, silicon, titanium, zirconium, vanadium and niobium. mentioned. In an embodiment of the present invention, the n-type dopant is preferably at least one selected from Sn, Ge and Si. The carrier density of the n++ type semiconductor layer is not particularly limited as long as it is higher than the carrier density of the n+ type semiconductor layer. In an embodiment of the present invention, the n++ type semiconductor layer preferably has a carrier density of 1.0×10 19 /cm 3 or more, more preferably 6.0×10 19 /cm 3 or more. . By setting the carrier density of the n++ type semiconductor layer to such a preferable value, the contact resistance can be reduced more satisfactorily. Also, the carrier density of the n+ type semiconductor layer is not particularly limited. In an embodiment of the present invention, it is preferable that the carrier density of the n+ type semiconductor layer is in the range of 1.0×10 17 /cm 3 or more and less than 1.0×10 19 /cm 3 . By setting the carrier density of the n + -type semiconductor layer within the preferred range as described above, the source resistance can be reduced more satisfactorily. In the embodiment of the present invention, the method of doping the n+ type semiconductor layer is not particularly limited, and may be diffusion, ion implantation, or epitaxial growth. In an embodiment of the present invention, it is preferable that the mobility of the n+ type semiconductor layer is higher than the mobility of the n++ type semiconductor layer. The thickness of the n++ type semiconductor layer is not particularly limited as long as the object of the present invention is not hindered. In an embodiment of the present invention, the n++ type semiconductor layer preferably has a thickness in the range of 1 nm to 1 μm, more preferably in the range of 10 nm to 100 nm. In an embodiment of the present invention, the thickness of the n+ type semiconductor layer is preferably larger than the thickness of the n++ type semiconductor layer. Since the source contact resistance and the source resistance in the semiconductor device can be satisfactorily reduced by using the above-described preferable combination of the n + -type semiconductor layer and the n++ -type semiconductor layer, the element resistance is further reduced. A semiconductor device can be realized.
　前記結晶性酸化物半導体層（以下、「酸化物半導体層」、「半導体膜」または「半導体層」ともいう。）は、公知の手段を用いて形成されてよい。前記半導体層の形成手段としては、例えば、ＣＶＤ法、ＭＯＣＶＤ法、ＭＯＶＰＥ法、ミストＣＶＤ法、ミスト・エピタキシー法、ＭＢＥ法、ＨＶＰＥ法、パルス成長法またはＡＬＤ法などが挙げられる。本発明の実施態様においては、前記半導体層の形成手段が、ＭＯＣＶＤ法、ミストＣＶＤ法、ミスト・エピタキシー法またはＨＶＰＥ法であるのが好ましく、ミストＣＶＤ法またはミスト・エピタキシー法であるのが好ましい。前記のミストＣＶＤ法またはミスト・エピタキシー法では、例えば図１３に示すミストＣＶＤ装置を用いて、原料溶液を霧化し（霧化工程）、液滴を浮遊させ、霧化後、得られた霧化液滴をキャリアガスでもって基体上まで搬送し（搬送工程）、ついで、前記基体近傍で前記霧化液滴を熱反応させることによって、基体上に結晶性酸化物半導体を主成分として含む半導体膜を積層する（成膜工程）ことにより前記半導体層を形成する。 The crystalline oxide semiconductor layer (hereinafter also referred to as "oxide semiconductor layer", "semiconductor film" or "semiconductor layer") may be formed using known means. Examples of means for forming the semiconductor layer include CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulse growth, and ALD. In an embodiment of the present invention, the means for forming the semiconductor layer is preferably MOCVD, mist CVD, mist epitaxy or HVPE, preferably mist CVD or mist epitaxy. In the mist CVD method or mist epitaxy method, for example, the mist CVD apparatus shown in FIG. A semiconductor film containing a crystalline oxide semiconductor as a main component is formed on a substrate by transporting droplets onto a substrate with a carrier gas (transporting step) and then thermally reacting the atomized droplets in the vicinity of the substrate. (film formation step) to form the semiconductor layer.
（霧化工程）
　霧化工程は、前記原料溶液を霧化する。前記原料溶液の霧化手段は、前記原料溶液を霧化できさえすれば特に限定されず、公知の手段であってよいが、本発明の実施態様においては、超音波を用いる霧化手段が好ましい。超音波を用いて得られた霧化液滴は、初速度がゼロであり、空中に浮遊するので好ましく、例えば、スプレーのように吹き付けるのではなく、空間に浮遊してガスとして搬送することが可能なミストであるので衝突エネルギーによる損傷がないため、非常に好適である。液滴サイズは、特に限定されず、数ｍｍ程度の液滴であってもよいが、好ましくは５０μｍ以下であり、より好ましくは１００ｎｍ～１０μｍである。 (Atomization process)
The atomization step atomizes the raw material solution. The means for atomizing the raw material solution is not particularly limited as long as it can atomize the raw material solution, and may be any known means. In the embodiment of the present invention, atomizing means using ultrasonic waves is preferable. . Atomized droplets obtained using ultrasonic waves have an initial velocity of zero and are preferable because they float in the air. Since it is a possible mist, there is no damage due to collision energy, so it is very suitable. The droplet size is not particularly limited, and may be droplets of several millimeters, preferably 50 μm or less, more preferably 100 nm to 10 μm.
（原料溶液）
　前記原料溶液は、霧化または液滴化が可能であり、半導体膜を形成可能な原料を含んでいれば特に限定されず、無機材料であっても、有機材料であってもよい。本発明の実施態様においては、前記原料が、金属または金属化合物であるのが好ましく、アルミニウム、ガリウム、インジウム、鉄、クロム、バナジウム、チタン、ロジウム、ニッケル、コバルトおよびイリジウムから選ばれる１種または２種以上の金属を含むのがより好ましい。 (raw material solution)
The raw material solution is not particularly limited as long as it contains a raw material capable of being atomized or dropletized and capable of forming a semiconductor film, and may be an inorganic material or an organic material. In an embodiment of the present invention, the raw material is preferably a metal or a metal compound, and one or two selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt and iridium. More preferably, it contains more than one species of metal.
　本発明の実施態様においては、前記原料溶液として、前記金属を錯体または塩の形態で有機溶媒または水に溶解または分散させたものを好適に用いることができる。錯体の形態としては、例えば、アセチルアセトナート錯体、カルボニル錯体、アンミン錯体、ヒドリド錯体などが挙げられる。塩の形態としては、例えば、有機金属塩（例えば金属酢酸塩、金属シュウ酸塩、金属クエン酸塩等）、硫化金属塩、硝化金属塩、リン酸化金属塩、ハロゲン化金属塩（例えば塩化金属塩、臭化金属塩、ヨウ化金属塩等）などが挙げられる。 In the embodiment of the present invention, as the raw material solution, a solution in which the metal is dissolved or dispersed in an organic solvent or water in the form of a complex or salt can be preferably used. Examples of forms of the complex include acetylacetonate complexes, carbonyl complexes, ammine complexes, hydride complexes, and the like. Examples of the salt form include organic metal salts (e.g., metal acetates, metal oxalates, metal citrates, etc.), metal sulfide salts, metal nitrate salts, metal phosphate salts, metal halide salts (e.g., metal chlorides, salts, metal bromides, metal iodides, etc.).
　また、前記原料溶液には、ハロゲン化水素酸や酸化剤等の添加剤を混合するのが好ましい。前記ハロゲン化水素酸としては、例えば、臭化水素酸、塩酸、ヨウ化水素酸などが挙げられるが、中でも、異常粒の発生をより効率的に抑制できるとの理由から、臭化水素酸またはヨウ化水素酸が好ましい。前記酸化剤としては、例えば、過酸化水素（Ｈ２Ｏ２）、過酸化ナトリウム（Ｎａ２Ｏ２）、過酸化バリウム（ＢａＯ２）、過酸化ベンゾイル（Ｃ６Ｈ５ＣＯ）２Ｏ２等の過酸化物、次亜塩素酸（ＨＣｌＯ）、過塩素酸、硝酸、オゾン水、過酢酸やニトロベンゼン等の有機過酸化物などが挙げられる。 Moreover, it is preferable to mix additives such as hydrohalic acid and an oxidizing agent into the raw material solution. Examples of the hydrohalic acid include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Among them, hydrobromic acid or Hydroiodic acid is preferred. Examples of the oxidizing agent include hydrogen peroxide (H 2 O 2 ), sodium peroxide (Na 2 O 2 ), barium peroxide (BaO 2 ), benzoyl peroxide (C 6 H 5 CO) 2 O 2 and the like. , hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, and organic peroxides such as peracetic acid and nitrobenzene.
　前記原料溶液には、ドーパントが含まれていてもよい。原料溶液にドーパントを含ませることで、ドーピングを良好に行うことができる。前記ドーパントは、本発明の目的を阻害しない限り、特に限定されない。前記ドーパントとしては、例えば、スズ、ゲルマニウム、ケイ素、チタン、ジルコニウム、バナジウムまたはニオブ等のｎ型ドーパント、またはＭｇ、Ｈ、Ｌｉ、Ｎａ、Ｋ、Ｒｂ、Ｃｓ、Ｆｒ、Ｂｅ、Ｃａ、Ｓｒ、Ｂａ、Ｒａ、Ｍｎ、Ｆｅ、Ｃｏ、Ｎｉ、Ｐｄ、Ｃｕ、Ａｇ、Ａｕ、Ｚｎ、Ｃｄ、Ｈｇ、Ｔｉ、Ｐｂ、Ｎ、もしくはＰ等のｐ型ドーパントなどが挙げられる。前記ドーパントの含有量は、所望のキャリア密度に対するドーパントの原料中の濃度の関係を示す検量線を用いることにより適宜設定される。 The raw material solution may contain a dopant. By including the dopant in the raw material solution, the doping can be performed well. The dopant is not particularly limited as long as it does not interfere with the object of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium or niobium, or Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba , Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N or P, and the like. The content of the dopant is appropriately set by using a calibration curve showing the relationship between the concentration of the dopant in the raw material and the desired carrier density.
　原料溶液の溶媒は、特に限定されず、水等の無機溶媒であってもよいし、アルコール等の有機溶媒であってもよいし、無機溶媒と有機溶媒との混合溶媒であってもよい。本発明の実施態様においては、前記溶媒が水を含むのが好ましく、水または水とアルコールとの混合溶媒であるのがより好ましい。 The solvent of the raw material solution is not particularly limited, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In an embodiment of the present invention, the solvent preferably contains water, more preferably water or a mixed solvent of water and alcohol.
（搬送工程）
　搬送工程では、キャリアガスでもって前記霧化液滴を成膜室内に搬送する。前記キャリアガスとしては、本発明の目的を阻害しない限り特に限定されず、例えば、酸素、オゾン、窒素やアルゴン等の不活性ガス、または水素ガスやフォーミングガス等の還元ガスなどが好適な例として挙げられる。また、キャリアガスの種類は１種類であってよいが、２種類以上であってもよく、流量を下げた希釈ガス（例えば１０倍希釈ガス等）などを、第２のキャリアガスとしてさらに用いてもよい。また、キャリアガスの供給箇所も１箇所だけでなく、２箇所以上あってもよい。キャリアガスの流量は、特に限定されないが、０．０１～２０Ｌ／分であるのが好ましく、１～１０Ｌ／分であるのがより好ましい。希釈ガスの場合には、希釈ガスの流量が、０．００１～２Ｌ／分であるのが好ましく、０．１～１Ｌ／分であるのがより好ましい。 (Conveyance process)
In the transporting step, the atomized liquid droplets are transported into the film forming chamber using a carrier gas. The carrier gas is not particularly limited as long as it does not interfere with the object of the present invention. Suitable examples include oxygen, ozone, inert gases such as nitrogen and argon, and reducing gases such as hydrogen gas and forming gas. mentioned. In addition, although one type of carrier gas may be used, two or more types may be used, and a diluted gas with a reduced flow rate (for example, a 10-fold diluted gas, etc.) may be further used as a second carrier gas. good too. In addition, the carrier gas may be supplied at two or more locations instead of at one location. Although the flow rate of the carrier gas is not particularly limited, it is preferably 0.01 to 20 L/min, more preferably 1 to 10 L/min. In the case of diluent gas, the flow rate of diluent gas is preferably 0.001 to 2 L/min, more preferably 0.1 to 1 L/min.
（成膜工程）
　成膜工程では、前記基体近傍で前記霧化液滴を熱反応させることによって、基体上に、前記半導体膜を成膜する。熱反応は、熱でもって前記霧化液滴が反応すればそれでよく、反応条件等も本発明の目的を阻害しない限り特に限定されない。本工程においては、前記熱反応を、通常、溶媒の蒸発温度以上の温度で行うが、高すぎない温度（例えば１０００℃）以下が好ましく、６５０℃以下がより好ましく、３００℃～６５０℃が最も好ましい。また、熱反応は、本発明の目的を阻害しない限り、真空下、非酸素雰囲気下（例えば、不活性ガス雰囲気下等）、還元ガス雰囲気下および酸素雰囲気下のいずれの雰囲気下で行われてもよいが、不活性ガス雰囲気下または酸素雰囲気下で行われるのが好ましい。また、大気圧下、加圧下および減圧下のいずれの条件下で行われてもよいが、本発明の実施態様においては、大気圧下で行われるのが好ましい。なお、膜厚は、成膜時間を調整することにより、設定することができる。 (Film formation process)
In the film forming step, the semiconductor film is formed on the substrate by thermally reacting the atomized droplets in the vicinity of the substrate. The thermal reaction is not particularly limited as long as the atomized droplets react with heat, and the reaction conditions and the like are not particularly limited as long as they do not interfere with the object of the present invention. In this step, the thermal reaction is usually carried out at a temperature equal to or higher than the evaporation temperature of the solvent, preferably at a temperature that is not too high (for example, 1000° C.), more preferably 650° C. or less, most preferably from 300° C. to 650° C. preferable. In addition, the thermal reaction is carried out under vacuum, under a non-oxygen atmosphere (for example, under an inert gas atmosphere, etc.), under a reducing gas atmosphere, or under an oxygen atmosphere, as long as the object of the present invention is not hindered. However, it is preferably carried out under an inert gas atmosphere or an oxygen atmosphere. The reaction may be carried out under atmospheric pressure, increased pressure or reduced pressure, but is preferably carried out under atmospheric pressure in the embodiment of the present invention. Note that the film thickness can be set by adjusting the film formation time.
（基体）
　前記基体は、前記半導体膜を支持できるものであれば特に限定されない。前記基体の材料も、本発明の目的を阻害しない限り特に限定されず、公知の基体であってよく、有機化合物であってもよいし、無機化合物であってもよい。前記基体の形状としては、どのような形状のものであってもよく、あらゆる形状に対して有効であり、例えば、平板や円板等の板状、繊維状、棒状、円柱状、角柱状、筒状、螺旋状、球状、リング状などが挙げられるが、本発明の実施態様においては、基板が好ましい。基板の厚さは、本発明の実施態様においては特に限定されない。 (substrate)
The substrate is not particularly limited as long as it can support the semiconductor film. The material of the substrate is also not particularly limited as long as it does not interfere with the object of the present invention, and may be a known substrate, an organic compound, or an inorganic compound. The shape of the substrate may be any shape, and is effective for all shapes. Cylindrical, helical, spherical, ring-shaped, etc. are mentioned, but in the embodiment of the present invention, the substrate is preferable. The thickness of the substrate is not particularly limited in embodiments of the present invention.
　前記基板は、板状であって、前記半導体膜の支持体となるものであれば特に限定されない。絶縁体基板であってもよいし、半導体基板であってもよいし、金属基板や導電性基板であってもよいが、前記基板が、絶縁体基板であるのが好ましく、また、表面に金属膜を有する基板であるのも好ましい。前記基板としては、例えば、コランダム構造を有する基板材料を主成分として含む下地基板、またはβ－ガリア構造を有する基板材料を主成分として含む下地基板、六方晶構造を有する基板材料を主成分として含む下地基板などが挙げられる。ここで、「主成分」とは、前記特定の結晶構造を有する基板材料が、原子比で、基板材料の全成分に対し、好ましくは５０％以上、より好ましくは７０％以上、更に好ましくは９０％以上含まれることを意味し、１００％であってもよい。 The substrate is not particularly limited as long as it has a plate shape and serves as a support for the semiconductor film. The substrate may be an insulator substrate, a semiconductor substrate, a metal substrate, or a conductive substrate. A substrate with a membrane is also preferred. As the substrate, for example, a base substrate containing a substrate material having a corundum structure as a main component, or a base substrate containing a substrate material having a β-gallia structure as a main component, a substrate material having a hexagonal crystal structure as a main component. A base substrate etc. are mentioned. Here, the “main component” means that the substrate material having the specific crystal structure accounts for preferably 50% or more, more preferably 70% or more, and even more preferably 90%, in atomic ratio, of all components of the substrate material. % or more, and may be 100%.
　基板材料は、本発明の目的を阻害しない限り、特に限定されず、公知のものであってよい。前記のコランダム構造を有する基板材料としては、例えば、α－Ａｌ２Ｏ３（サファイア基板）またはα－Ｇａ２Ｏ３が好適に挙げられ、ａ面サファイア基板、ｍ面サファイア基板、ｒ面サファイア基板、ｃ面サファイア基板や、α型酸化ガリウム基板（ａ面、ｍ面またはｒ面）などがより好適な例として挙げられる。β－ガリア構造を有する基板材料を主成分とする下地基板としては、例えばβ－Ｇａ２Ｏ３基板、又はＧａ２Ｏ３とＡｌ２Ｏ３とを含みＡｌ２Ｏ３が０ｗｔ％より多くかつ６０ｗｔ％以下である混晶体基板などが挙げられる。また、六方晶構造を有する基板材料を主成分とする下地基板としては、例えば、ＳｉＣ基板、ＺｎＯ基板、ＧａＮ基板などが挙げられる。 The substrate material is not particularly limited as long as it does not interfere with the object of the present invention, and may be any known material. The substrate material having the corundum structure, for example, α-Al 2 O 3 (sapphire substrate) or α-Ga 2 O 3 are preferably mentioned, a-plane sapphire substrate, m-plane sapphire substrate, r-plane sapphire substrate , a c-plane sapphire substrate, an α-type gallium oxide substrate (a-plane, m-plane, or r-plane) and the like are more preferable examples. The base substrate mainly composed of a substrate material having a β-Gallia structure is, for example, a β-Ga 2 O 3 substrate, or a substrate containing Ga 2 O 3 and Al 2 O 3 with more than 0 wt % of Al 2 O 3 and A mixed crystal substrate having a content of 60 wt % or less may be used. Examples of base substrates mainly composed of a substrate material having a hexagonal crystal structure include SiC substrates, ZnO substrates, and GaN substrates.
　本発明の実施態様においては、前記成膜工程の後、アニール処理を行ってもよい。アニールの処理温度は、本発明の目的を阻害しない限り特に限定されず、通常、３００℃～６５０℃であり、好ましくは３５０℃～５５０℃である。また、アニールの処理時間は、通常、１分間～４８時間であり、好ましくは１０分間～２４時間であり、より好ましくは３０分間～１２時間である。なお、アニール処理は、本発明の目的を阻害しない限り、どのような雰囲気下で行われてもよい。非酸素雰囲気下であってもよいし、酸素雰囲気下であってもよい。非酸素雰囲気下としては、例えば、不活性ガス雰囲気下（例えば、窒素雰囲気下）または還元ガス雰囲気下等が挙げられるが、本発明の実施態様においては、不活性ガス雰囲気下が好ましく、窒素雰囲気下であるのがより好ましい。 In the embodiment of the present invention, annealing may be performed after the film formation process. Annealing treatment temperature is not particularly limited as long as the object of the present invention is not impaired, and is usually 300°C to 650°C, preferably 350°C to 550°C. The annealing treatment time is usually 1 minute to 48 hours, preferably 10 minutes to 24 hours, more preferably 30 minutes to 12 hours. The annealing treatment may be performed under any atmosphere as long as the object of the present invention is not hindered. A non-oxygen atmosphere or an oxygen atmosphere may be used. The non-oxygen atmosphere includes, for example, an inert gas atmosphere (e.g., nitrogen atmosphere), a reducing gas atmosphere, etc. In the embodiment of the present invention, an inert gas atmosphere is preferable, and a nitrogen atmosphere Lower is more preferred.
　また、本発明の実施態様においては、前記基体上に、直接、前記半導体膜を設けてもよいし、応力緩和層（例えば、バッファ層、ＥＬＯ層等）、剥離犠牲層等の他の層を介して前記半導体膜を設けてもよい。各層の形成手段は、特に限定されず、公知の手段であってよいが、本発明の実施態様においては、ミストＣＶＤ法が好ましい。 Further, in the embodiment of the present invention, the semiconductor film may be directly provided on the substrate, or other layers such as a stress relaxation layer (for example, a buffer layer, an ELO layer, etc.), a peeling sacrificial layer, etc. may be formed on the substrate. The semiconductor film may be provided via the semiconductor film. The means for forming each layer is not particularly limited, and known means may be used. In the embodiment of the present invention, the mist CVD method is preferred.
　本発明の実施態様においては、前記半導体膜を、前記基体等から剥離する等の公知の手段を用いた後に、前記半導体層として半導体装置に用いてもよいし、そのまま前記半導体層として半導体装置に用いてもよい。 In the embodiment of the present invention, the semiconductor film may be used as the semiconductor layer in the semiconductor device after using known means such as peeling from the substrate or the like, or may be used as the semiconductor layer in the semiconductor device as it is. may be used.
　前記ソース電極は、導電性を有するものであれば、本発明の目的を阻害しない限り、特に限定されない。前記ソース電極の構成材料は、導電性無機材料であってもよいし、導電性有機材料であってもよい。本発明の実施態様においては、前記ソース電極の材料が、金属であるのが好ましい。前記金属としては、好適には、例えば、周期律表第４族～第１０族から選ばれる少なくとも１種の金属等が挙げられる。周期律表第４族の金属としては、例えば、チタン（Ｔｉ）、ジルコニウム（Ｚｒ）、ハフニウム（Ｈｆ）などが挙げられる。周期律表第５族の金属としては、例えば、バナジウム（Ｖ）、ニオブ（Ｎｂ）、タンタル（Ｔａ）などが挙げられる。周期律表第６族の金属としては、例えば、クロム（Ｃｒ）、モリブデン（Ｍｏ）およびタングステン（Ｗ）などが挙げられる。周期律表第７族の金属としては、例えば、マンガン（Ｍｎ）、テクネチウム（Ｔｃ）、レニウム（Ｒｅ）などが挙げられる。周期律表第８族の金属としては、例えば、鉄（Ｆｅ）、ルテニウム（Ｒｕ）、オスミウム（Ｏｓ）などが挙げられる。周期律表第９族の金属としては、例えば、コバルト（Ｃｏ）、ロジウム（Ｒｈ）、イリジウム（Ｉｒ）などが挙げられる。周期律表第１０族の金属としては、例えば、ニッケル（Ｎｉ）、パラジウム（Ｐｄ）、白金（Ｐｔ）などが挙げられる。本発明の実施態様においては、前記ソース電極が、チタン（Ｔｉ）、タンタル（Ｔａ）およびタングステン（Ｗ）から選ばれる少なくとも１種の金属を含むのが好ましい。また、本発明の実施態様においては、前記ソース電極が導電性金属酸化物を含んでいてもよい。前記ソース電極に含まれる導電性金属酸化物としては、例えば、酸化錫、酸化亜鉛、酸化インジウム、酸化インジウム錫（ＩＴＯ）、酸化亜鉛インジウム（ＩＺＯ）等の金属酸化物導電膜が挙げられる。前記ソース電極は、単層で構成されていてもよいし、複数の金属層を含むものであってもよい。前記ソース電極が複数の金属層を含む場合、例えば、第１の層および第３の層に周期律表第４族金属を用いて、第１層の層と第３の層との間に位置する第２の層に周期律表第１３族金属（例えば、Ａｌ等）を用いるのが好ましい。このような好ましい構成のソース電極を用いることにより、ソース電極・ソース領域間のオーミック特性の信頼性をより向上させることができる。前記ソース電極の形成方法は、特に限定されない。前記ソース電極の形成方法としては、具体的には例えば、ドライ法やウェット法などが挙げられる。ドライ法としては、例えば、スパッタ、真空蒸着、ＣＶＤ等が挙げられる。ウェット法としては、例えば、スクリーン印刷やダイコート等が挙げられる。 The source electrode is not particularly limited as long as it has conductivity, as long as it does not hinder the object of the present invention. The constituent material of the source electrode may be a conductive inorganic material or a conductive organic material. In an embodiment of the present invention, the material of the source electrode is preferably metal. Suitable examples of the metal include at least one metal selected from Groups 4 to 10 of the periodic table. Examples of metals belonging to Group 4 of the periodic table include titanium (Ti), zirconium (Zr), hafnium (Hf), and the like. Examples of metals belonging to Group 5 of the periodic table include vanadium (V), niobium (Nb), and tantalum (Ta). Examples of Group 6 metals of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W). Examples of metals of Group 7 of the periodic table include manganese (Mn), technetium (Tc), and rhenium (Re). Examples of metals belonging to Group 8 of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os). Examples of metals belonging to Group 9 of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals of Group 10 of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt). In an embodiment of the present invention, the source electrode preferably contains at least one metal selected from titanium (Ti), tantalum (Ta) and tungsten (W). Moreover, in the embodiment of the present invention, the source electrode may contain a conductive metal oxide. Examples of the conductive metal oxide contained in the source electrode include metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO). The source electrode may be composed of a single layer, or may include a plurality of metal layers. If the source electrode comprises a plurality of metal layers, for example using Group 4 metals for the first and third layers, a metal layer located between the first and third layers. It is preferable to use a Group 13 metal of the periodic table (for example, Al or the like) for the second layer. By using the source electrode having such a preferable configuration, the reliability of the ohmic characteristics between the source electrode and the source region can be further improved. A method for forming the source electrode is not particularly limited. Specific examples of the method for forming the source electrode include a dry method and a wet method. Dry methods include, for example, sputtering, vacuum deposition, and CVD. Wet methods include, for example, screen printing and die coating.
　本発明の実施態様においては、前記ソース電極が、前記電流遮断層とコンタクトを形成しているのが好ましく、前記ソース電極が、前記電流遮断層と直接コンタクトを形成しているのがより好ましい。このような好ましい構成とすることにより、前記半導体装置の応答性をより向上することができる。 In an embodiment of the present invention, the source electrode preferably forms contact with the current blocking layer, and more preferably forms direct contact with the current blocking layer. With such a preferable configuration, the responsiveness of the semiconductor device can be further improved.
　本発明の半導体装置は、様々な半導体素子に有用であり、とりわけ、パワーデバイスに有用である。また、半導体素子は、電極が半導体層の片面側に形成され、半導体層の膜厚方向と垂直方向に電流が流れる横型の素子（横型デバイス）と、半導体層の表裏両面側にそれぞれ電極を有し、半導体層の膜厚方向に電流が流れる縦型の素子（縦型デバイス）に分類することができ、本発明の実施態様においては、前記半導体素子を横型デバイスにも縦型デバイスにも好適に用いることができるが、中でも縦型デバイスに用いることが好ましい。前記半導体素子としては、例えば、金属半導体電界効果トランジスタ（ＭＥＳＦＥＴ）、高電子移動度トランジスタ（ＨＥＭＴ）、金属酸化膜半導体電界効果トランジスタ（ＭＯＳＦＥＴ）、静電誘導トランジスタ（ＳＩＴ）、接合電界効果トランジスタ（ＪＦＥＴ）または絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）などが挙げられる。本発明の実施態様においては、前記半導体装置が、ＭＯＳＦＥＴ、ＳＩＴ、ＪＦＥＴまたはＩＧＢＴであるのが好ましく、ＭＯＳＦＥＴまたはＩＧＢＴであるのがより好ましい。 The semiconductor device of the present invention is useful for various semiconductor elements, especially for power devices. In addition, the semiconductor element includes a horizontal element (horizontal device) in which an electrode is formed on one side of a semiconductor layer and current flows in a direction perpendicular to the film thickness direction of the semiconductor layer (horizontal device), and electrodes are formed on both front and back sides of the semiconductor layer. However, it can be classified into a vertical device (vertical device) in which current flows in the thickness direction of the semiconductor layer, and in the embodiment of the present invention, the semiconductor device is suitable for both horizontal and vertical devices. However, it is preferably used for a vertical device. Examples of the semiconductor device include metal semiconductor field effect transistors (MESFET), high electron mobility transistors (HEMT), metal oxide semiconductor field effect transistors (MOSFET), static induction transistors (SIT), junction field effect transistors ( JFET) or an insulated gate bipolar transistor (IGBT). In an embodiment of the present invention, the semiconductor device is preferably MOSFET, SIT, JFET or IGBT, more preferably MOSFET or IGBT.
　以下、前記半導体装置の好適な例を、図面を用いて説明するが、本発明はこれら実施の態様に限定されるものではない。なお、以下に例示する半導体装置において、本発明の目的を阻害しない限り、さらに他の層（例えば絶縁体層、半絶縁体層、導体層、半導体層、緩衝層またはその他中間層等）などが含まれていてもよいし、また、緩衝層（バッファ層）なども適宜省いてもよい。 Preferred examples of the semiconductor device will be described below with reference to the drawings, but the present invention is not limited to these embodiments. In the semiconductor devices exemplified below, other layers (for example, an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers, etc.), etc., as long as the object of the present invention is not hindered. It may be included, or a buffer layer (buffer layer) and the like may be omitted as appropriate.
　図１は、本発明の好適な実施態様の一つである金属酸化膜半導体電界効果トランジスタ（ＭＯＳＦＥＴ）の主要部を示す。図１のＭＯＳＦＥＴは、ドレイン電極５ｃ、ｎ＋型半導体層３、ドリフト層としてのｎ－型半導体層７、電流遮断層（電流遮断領域）２、チャネル層６、ソース領域（ｎ＋型半導体層）１、ゲート絶縁膜４ａ、層間絶縁膜４ｂ、ゲート電極５ａおよびソース電極５ｂを備える。図１のＭＯＳＦＥＴにおいては、図１から明らかなとおり、ドレイン電極５ｃ上にｎ＋型半導体層３、ｎ－型半導体層（ドリフト層）７、電流遮断層２、チャネル層６およびｎ＋型半導体層（ソース層）１がこの順に形成されている。ここで、前記ｎ＋型半導体層３、ｎ－型半導体層７、チャネル層６、電流遮断層２、ｎ＋型半導体層１が結晶性酸化物半導体層８を構成している。なお、電流遮断層２は、イオン注入によって形成されており、イオン注入による結晶欠陥（図示しない）を含む層である。前記電流遮断層は、前記結晶性酸化物半導体層８の厚み方向からみて前記ソース電極と平面視で重なっており、且つチャネル層の一部と平面視で重なっている。なお、前記電流遮断層は、前記結晶性酸化物半導体層８の厚み方向からみて前記チャネル層の一部とは重ならないような構成となっている。このような構成により、電流遮断効果を維持しつつ、電流経路が確保されている。なお、前記電流経路の幅Ｗは、本発明の目的を阻害しない限り、特に限定されない。本発明の実施態様においては、特に、ドリフト層として酸化ガリウム等のバンドギャップの大きな材料を用いる場合、前記電流経路の幅Ｗが、２μｍ以下であるのが好ましい。また、前記電流遮断層の厚さｄも、本発明の目的を阻害しない限り、特に限定されない。本発明の実施態様においては、特に、ドリフト層として酸化ガリウム等のバンドギャップの大きな材料を用いる場合、前記電流遮断層の厚さｄは０．１５μｍ以上であるのが好ましく、０．２μｍ以上であるのがより好ましい。図１のＭＯＳＦＥＴのオン状態では、前記ソース電極５ｂとでドレイン電極５ｃとの間に電圧を印加し、前記ゲート電極５ａに前記ソース電極５ｂに対して正の電圧を与えると、電子（ホール）がチャネル層６に注入され、ターンオンする。オフ状態は、前記ゲート電極の電圧を０Ｖとすることにより、チャネル層６が空乏層で満たされた状態となり、ターンオフする。本発明の実施態様においては、前記電流遮断層がドーパント元素を含有し、前記電流遮断層中に、前記ドーパント元素の濃度が５．０×１０１７／ｃｍ３以上である領域を含んでいるため、前記半導体装置のＭＯＳＦＥＴ動作を保ちつつ、耐圧性をより向上させることができる。なお、他の好適な実施態様として、図１の半導体装置において、ソース領域（ｎ＋型半導体層）１は、チャネル層６内に少なくとも一部が埋め込まれていてもよい。ソース領域（ｎ＋型半導体層）１がチャネル層６内に埋め込まれている場合の例を図４に示す。図４に示す構造によれば、ゲート絶縁膜にかかる電界の電界集中が生じにくく、ゲート絶縁膜の信頼性をより向上させることができる。 FIG. 1 shows the main part of a metal oxide semiconductor field effect transistor (MOSFET) which is one of the preferred embodiments of the present invention. The MOSFET of FIG. 1 includes a drain electrode 5c, an n + type semiconductor layer 3, an n− type semiconductor layer 7 as a drift layer, a current blocking layer (current blocking region) 2, a channel layer 6, and a source region (n + type semiconductor layer) 1. , a gate insulating film 4a, an interlayer insulating film 4b, a gate electrode 5a and a source electrode 5b. In the MOSFET of FIG. 1, as is clear from FIG. 1, the n + type semiconductor layer 3, the n− type semiconductor layer (drift layer) 7, the current blocking layer 2, the channel layer 6 and the n + type semiconductor layer ( A source layer) 1 is formed in this order. Here, the n+ type semiconductor layer 3, the n− type semiconductor layer 7, the channel layer 6, the current blocking layer 2, and the n+ type semiconductor layer 1 constitute a crystalline oxide semiconductor layer 8. FIG. The current blocking layer 2 is formed by ion implantation and is a layer containing crystal defects (not shown) due to the ion implantation. The current blocking layer overlaps the source electrode in plan view when viewed from the thickness direction of the crystalline oxide semiconductor layer 8, and overlaps a part of the channel layer in plan view. The current blocking layer is configured so as not to partially overlap the channel layer when viewed in the thickness direction of the crystalline oxide semiconductor layer 8 . Such a configuration secures a current path while maintaining the current blocking effect. The width W of the current path is not particularly limited as long as it does not hinder the object of the present invention. In an embodiment of the present invention, it is preferable that the width W of the current path is 2 μm or less, particularly when a material having a large bandgap such as gallium oxide is used for the drift layer. Also, the thickness d of the current blocking layer is not particularly limited as long as the object of the present invention is not hindered. In an embodiment of the present invention, particularly when a material having a large bandgap such as gallium oxide is used for the drift layer, the thickness d of the current blocking layer is preferably 0.15 μm or more, more preferably 0.2 μm or more. It is more preferable to have In the ON state of the MOSFET in FIG. 1, when a voltage is applied between the source electrode 5b and the drain electrode 5c, and a positive voltage is applied to the gate electrode 5a with respect to the source electrode 5b, electrons (holes) are generated. is injected into the channel layer 6 and turned on. In the OFF state, the channel layer 6 is filled with a depletion layer by setting the voltage of the gate electrode to 0 V, and the transistor is turned off. In the embodiment of the present invention, the current blocking layer contains a dopant element, and the current blocking layer includes a region having a dopant element concentration of 5.0×10 17 /cm 3 or more. , while maintaining the MOSFET operation of the semiconductor device, the withstand voltage can be further improved. As another preferred embodiment, in the semiconductor device of FIG. 1, the source region (n + -type semiconductor layer) 1 may be at least partially embedded in the channel layer 6 . FIG. 4 shows an example in which the source region (n + -type semiconductor layer) 1 is embedded in the channel layer 6 . According to the structure shown in FIG. 4, the electric field concentration applied to the gate insulating film is less likely to occur, and the reliability of the gate insulating film can be further improved.
　図９は、本発明の好適な実施態様の一つである金属酸化膜半導体電界効果トランジスタ（ＭＯＳＦＥＴ）の主要部を示す。図９のＭＯＳＦＥＴは、結晶性酸化物半導体層８が少なくともチャネル層６を貫通するトレンチを有しており、且つ、電流遮断層２がチャネル層６の直下に位置している点で図１のＭＯＳＦＥＴと異なる。本発明の実施態様においては、このようなトレンチ型ＭＯＳＦＥＴの場合には、前記電流遮断層２の厚みが０．２μｍ以下であるのが好ましく、０．１μｍ以下であるのがより好ましい。このような好ましい厚みとすることにより、ＭＯＳＦＥＴの立ち上がり電圧（Ｖｔｈ）への影響を抑えつつ電流遮断効果を奏することができる。 FIG. 9 shows the main part of a metal oxide semiconductor field effect transistor (MOSFET), which is one of the preferred embodiments of the present invention. The MOSFET of FIG. 9 has a trench penetrating through at least the channel layer 6 in the crystalline oxide semiconductor layer 8, and the current blocking layer 2 is positioned immediately below the channel layer 6. Different from MOSFET. In the embodiment of the present invention, in the case of such a trench type MOSFET, the thickness of the current blocking layer 2 is preferably 0.2 μm or less, more preferably 0.1 μm or less. With such a preferable thickness, it is possible to achieve a current blocking effect while suppressing the influence on the rising voltage (Vth) of the MOSFET.
　図１０は、本発明の好適な実施態様の一つである金属酸化膜半導体電界効果トランジスタ（ＭＯＳＦＥＴ）の主要部を示す。図１のＭＯＳＦＥＴは、ドレイン電極５ｃ、ｎ＋型半導体層３、ドリフト層としてのｎ－型半導体層７、電流遮断層（電流遮断領域）２、チャネル層６、ソース領域（ｎ＋型半導体層）１、ゲート絶縁膜４、ゲート電極５ａおよびソース電極５ｂを備える。ここで、前記ｎ＋型半導体層３、ｎ－型半導体層７、チャネル層６、電流遮断層２およびｎ＋型半導体層１が酸化物半導体層８を構成している。なお、電流遮断層２は、ドリフト層７上にエピタキシャル成長により形成されている。前記電流遮断層は、前記結晶性酸化物半導体層８の厚み方向からみて前記ソース電極と平面視で重なっており、且つチャネル層の一部と平面視で重なっている。なお、前記電流遮断層は、前記結晶性酸化物半導体層８の厚み方向からみて前記チャネル層の一部とは重ならないような構成となってる。このような構成により、電流遮断効果を維持しつつ、電流経路が確保されている。本発明の実施態様においては、ドリフト層７の主成分としての第１の結晶性酸化物と前記電流遮断層の主成分としての第２の結晶性酸化物とが異なる組成を有するので、前記半導体装置のＭＯＳＦＥＴ動作（ノーマリーオフ動作）を保ちつつ、耐圧性をより向上させることができる。 FIG. 10 shows the main part of a metal oxide semiconductor field effect transistor (MOSFET), which is one of the preferred embodiments of the present invention. The MOSFET of FIG. 1 includes a drain electrode 5c, an n + type semiconductor layer 3, an n− type semiconductor layer 7 as a drift layer, a current blocking layer (current blocking region) 2, a channel layer 6, and a source region (n + type semiconductor layer) 1. , a gate insulating film 4, a gate electrode 5a and a source electrode 5b. Here, the n+ type semiconductor layer 3, the n− type semiconductor layer 7, the channel layer 6, the current blocking layer 2 and the n+ type semiconductor layer 1 constitute an oxide semiconductor layer 8. FIG. The current blocking layer 2 is formed on the drift layer 7 by epitaxial growth. The current blocking layer overlaps the source electrode in plan view when viewed from the thickness direction of the crystalline oxide semiconductor layer 8, and overlaps a part of the channel layer in plan view. The current blocking layer is configured so as not to partially overlap the channel layer when viewed in the thickness direction of the crystalline oxide semiconductor layer 8 . Such a configuration secures a current path while maintaining the current blocking effect. In the embodiment of the present invention, since the first crystalline oxide as the main component of the drift layer 7 and the second crystalline oxide as the main component of the current blocking layer have different compositions, the semiconductor It is possible to further improve the breakdown voltage while maintaining the MOSFET operation (normally-off operation) of the device.
　図１、図４、図９および図１０の各層の形成手段は、本発明の目的を阻害しない限り、特に限定されず、公知の手段であってよい。例えば、真空蒸着法やＣＶＤ法、スパッタ法、各種コーティング技術により成膜した後、フォトリソグラフィー法によりパターニングする手段、または印刷技術などを用いて直接パターニングを行う手段などが挙げられる。 The means for forming each layer in FIGS. 1, 4, 9 and 10 is not particularly limited as long as it does not hinder the object of the present invention, and may be known means. For example, after forming a film by a vacuum vapor deposition method, a CVD method, a sputtering method, or various coating techniques, a means for patterning by a photolithographic method, or a means for directly patterning using a printing technique or the like can be used.
　以下、図１の半導体装置を製造する好適な例を用いて、本発明をより詳細に説明する。図２（ａ）は、基板９上に、ｎ＋型半導体層３およびドリフト層（ｎ型半導体層）７がこの順に積層されている積層構造体を示す。図２（ａ）の積層体の前記ドリフト層（ｎ－型半導体層）７中に、イオン注入を用いて電流遮断層（結晶欠陥領域）２を形成し、ついで、チャネル層６、ソース領域としてのｎ＋型半導体層１を形成することにより、図２（ｂ）の積層体を得る。前記イオン注入の注入エネルギーは、特に限定されない。本発明の実施態様においては、前記イオン注入の注入エネルギーは、例えば、１０ｋｅＶ～２ＭｅＶの範囲内である。なお、前記ｎ＋型半導体層１は、例えばミストＣＶＤ法等のエピタキシャル成長方法を用いて成膜した後、公知のエッチング技術を用いてエッチングすることにより、パターン形成される。ついで、図２（ｂ）の積層体上に、ゲート絶縁膜４ａおよびゲート電極５ａを形成し、さらに、層間絶縁膜４ｂおよびコンタクトホールを形成することにより、図２（ｃ）の積層体を得る。前記ゲート絶縁膜４ａおよびゲート電極５ａは、それぞれ公知の成膜方法を用いて成膜した後、公知のエッチング技術を用いてエッチングすることにより、図２（ｃ）に示す形状に加工することができる。 The present invention will be described in more detail below using a preferred example of manufacturing the semiconductor device of FIG. FIG. 2(a) shows a laminated structure in which an n+ type semiconductor layer 3 and a drift layer (n type semiconductor layer) 7 are laminated in this order on a substrate 9. FIG. A current blocking layer (crystal defect region) 2 is formed in the drift layer (n-type semiconductor layer) 7 of the laminate shown in FIG. 2(b) is obtained by forming the n+ type semiconductor layer 1 of FIG. The implantation energy of the ion implantation is not particularly limited. In an embodiment of the invention, the implantation energy of said ion implantation is, for example, in the range of 10 keV to 2 MeV. The n+ type semiconductor layer 1 is patterned by forming a film using an epitaxial growth method such as a mist CVD method and then etching using a known etching technique. Next, a gate insulating film 4a and a gate electrode 5a are formed on the laminate shown in FIG. 2(b), and an interlayer insulating film 4b and contact holes are formed to obtain the laminate shown in FIG. 2(c). . The gate insulating film 4a and the gate electrode 5a can be processed into the shape shown in FIG. 2(c) by etching using a known etching technique after forming films using a known film forming method. can.
　次に、図２（ｃ）の積層体上に、公知の成膜方法を用いてソース電極５ｂを形成して、図３（ｄ）の積層体を得る。前記ソース電極５ｂの成膜方法としては、上記したドライ法またはウェット法等が挙げられる。ついで、図３（ｄ）の積層体における基板９を除去した後、公知の成膜方法を用いてドレイン電極５ｃを形成することにより、図３（ｅ）の半導体装置を得ることができる。図３（ｅ）の半導体装置は、上述のように、結晶欠陥領域からなる電流遮断領域（電流遮断層）を備えているため、ＭＯＳＦＥＴ動作を保ちつつ、耐圧性により優れたものとなる。 Next, the source electrode 5b is formed on the laminate shown in FIG. 2(c) using a known film formation method to obtain the laminate shown in FIG. 3(d). As a method for forming the source electrode 5b, the above-described dry method, wet method, or the like can be used. Next, after removing the substrate 9 in the laminate of FIG. 3(d), the semiconductor device of FIG. 3(e) can be obtained by forming the drain electrode 5c using a known film forming method. As described above, the semiconductor device of FIG. 3(e) has a current blocking region (current blocking layer) made up of a crystal defect region, so that the MOSFET operation is maintained and the breakdown voltage is improved.
　以下、図１０の半導体装置を製造する好適な例を用いて、本発明をより詳細に説明する。図１１（ａ）は、基板９上に、ｎ＋型半導体層３、ドリフト層（ｎ－型半導体層）７および電流遮断層（電流遮断領域）２がこの順に積層されている積層構造体を示す。前記電流遮断層２は、公知のパターニング技術を用いてパターン形成されている。図１１（ａ）の積層体上に、チャネル層６、ソース領域としてのｎ＋型半導体層１を形成することにより、図１１（ｂ）の積層体を得る。なお、前記ｎ＋型半導体層１は、例えばミストＣＶＤ法等のエピタキシャル成長方法を用いて成膜した後、公知のエッチング技術を用いてエッチングすることにより、パターン形成される。ついで、図１１（ｂ）の積層体上に、ゲート絶縁膜４ａおよびゲート電極５ａを形成し、さらに、層間絶縁膜４ｂおよびコンタクトホールを形成することにより、図１１（ｃ）の積層体を得る。前記ゲート絶縁膜４ａおよびゲート電極５ａは、それぞれ公知の成膜方法を用いて成膜した後、公知のエッチング技術を用いてエッチングすることにより、図１１（ｃ）に示す形状に加工することができる。 The present invention will be described in more detail below using a preferred example of manufacturing the semiconductor device of FIG. FIG. 11(a) shows a laminated structure in which an n+ type semiconductor layer 3, a drift layer (n− type semiconductor layer) 7, and a current blocking layer (current blocking region) 2 are stacked in this order on a substrate 9. . The current blocking layer 2 is patterned using known patterning techniques. By forming a channel layer 6 and an n+ type semiconductor layer 1 as a source region on the layered structure of FIG. 11(a), the layered structure of FIG. 11(b) is obtained. The n+ type semiconductor layer 1 is patterned by forming a film using an epitaxial growth method such as a mist CVD method and then etching using a known etching technique. Next, a gate insulating film 4a and a gate electrode 5a are formed on the layered structure shown in FIG. 11(b), and an interlayer insulating film 4b and contact holes are formed to obtain the layered structure shown in FIG. 11(c). . The gate insulating film 4a and the gate electrode 5a can be processed into the shape shown in FIG. 11(c) by etching using a known etching technique after forming films using a known film forming method. can.
　次に、図１１（ｃ）の積層体上に、公知の成膜方法を用いてソース電極５ｂを形成して、図１２（ｄ）の積層体を得る。前記ソース電極５ｂの成膜方法としては、上記したドライ法またはウェット法等が挙げられる。ついで、図１２（ｄ）の積層体における基板９を除去した後、公知の成膜方法を用いてドレイン電極５ｃを形成することにより、図１２（ｅ）の半導体装置を得ることができる。 Next, the source electrode 5b is formed on the laminate shown in FIG. 11(c) using a known film formation method to obtain the laminate shown in FIG. 12(d). As a method for forming the source electrode 5b, the above-described dry method, wet method, or the like can be used. Next, after removing the substrate 9 in the laminate of FIG. 12(d), the semiconductor device of FIG. 12(e) can be obtained by forming the drain electrode 5c using a known film formation method.
　また、本実施例として、前記結晶欠陥領域による耐圧向上効果を確認するために、図１に示す半導体装置に準ずる構造の半導体装置を、上記手順に準じて、試作した。実施例１の構成は以下に示すとおりである。ｎ－型半導体層３として、スズドープα－Ｇａ２Ｏ３からなるｎ－型半導体層、ｎ＋型半導体層１ａとして、スズドープα－Ｇａ２Ｏ３からなるｎ＋型半導体層を用いた。イオン注入によって注入する元素として、窒素（実施例１）および錫（実施例２）を用いた。イオン注入は、実施例１はシングルプロファイルとなるように、実施例２はボックスプロファイルとなるように行った。また、比較例１として、ドーパント元素の濃度５．０×１０１７／ｃｍ３以上の領域を有する電流遮断領域を形成しなかったこと以外は、実施例１と同様にして半導体装置を試作した。実施例１、実施例２および比較例１で作製した半導体装置のＩ－Ｖ測定の結果を図７に示す。図７から明らかなように、本発明の実施態様にかかる実施例１および実施例２の半導体装置は、比較例１の半導体装置と比較して耐圧性に優れていることがわかる。このことは、酸化ガリウム（特にα－Ｇａ２Ｏ３）を用いた半導体装置を試作して初めて得られた新知見である。なお、実施例１および実施例２におけるＳＩＭＳ測定結果をそれぞれ図５および図６に示す。図５から明らかなように、実施例１において得られた電流遮断層は、ドーパント元素の濃度が５．０×１０１７／ｃｍ３以上の領域を有することが分かる。また、図６から明らかなように、実施例２において得られた電流遮断層は、ドーパント元素の濃度が１．０×１０１８／ｃｍ３以上の領域を有することがわかる。実施例１と同様にして図１に示す半導体装置に準ずる構造の半導体装置（ＭＯＳＦＥＴ）を作製し、Ｉ－Ｖ測定を行った結果を図８に示す。図８から明らかなように、本実施例におけるＭＯＳＦＥＴはトランジスタとして良好に動作することがわかる。なお、実施例２と同様にして図１に示す半導体装置に準ずる構造の半導体装置（ＭＯＳＦＥＴ）を作製した場合にも、実施例１と同様にトランジスタとして良好に動作することがわかった。 In addition, as a present example, a semiconductor device having a structure similar to that of the semiconductor device shown in FIG. The configuration of Example 1 is as follows. An n− type semiconductor layer made of tin-doped α-Ga 2 O 3 was used as the n− type semiconductor layer 3, and an n+ type semiconductor layer made of tin doped α-Ga 2 O 3 was used as the n+ type semiconductor layer 1a. Nitrogen (Example 1) and tin (Example 2) were used as elements to be implanted by ion implantation. The ion implantation was performed so that Example 1 had a single profile, and Example 2 had a box profile. Further, as Comparative Example 1, a semiconductor device was prototyped in the same manner as in Example 1, except that no current blocking region having a dopant element concentration of 5.0×10 17 /cm 3 or more was formed. Results of IV measurement of the semiconductor devices manufactured in Examples 1, 2 and Comparative Example 1 are shown in FIG. As is clear from FIG. 7, the semiconductor devices of Examples 1 and 2 according to the embodiment of the present invention are superior in withstand voltage to the semiconductor device of Comparative Example 1. FIG. This is a new finding that was first obtained when a semiconductor device using gallium oxide (especially α-Ga 2 O 3 ) was manufactured on a trial basis. The SIMS measurement results in Examples 1 and 2 are shown in FIGS. 5 and 6, respectively. As is clear from FIG. 5, the current blocking layer obtained in Example 1 has a region with a dopant element concentration of 5.0×10 17 /cm 3 or more. As is clear from FIG. 6, the current blocking layer obtained in Example 2 has a region with a dopant element concentration of 1.0×10 18 /cm 3 or more. A semiconductor device (MOSFET) having a structure similar to the semiconductor device shown in FIG. 1 was manufactured in the same manner as in Example 1, and the result of IV measurement is shown in FIG. As is clear from FIG. 8, the MOSFET in this embodiment works well as a transistor. It was found that a semiconductor device (MOSFET) having a structure similar to that of the semiconductor device shown in FIG.
　上述した本発明の実施態様にかかる半導体装置は、上記した機能を発揮させるべく、インバータやコンバータなどの電力変換装置に適用することができる。より具体的には、スイッチング素子であるサイリスタ、パワートランジスタ、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）、ＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）等として適用することができる。図１４は、本発明の実施態様に係る半導体装置を用いた制御システムの一例を示すブロック構成図、図１５は同制御システムの回路図であり、特に電気自動車（Ｅｌｅｃｔｒｉｃ　Ｖｅｈｉｃｌｅ）への搭載に適した制御システムである。 The semiconductor device according to the embodiment of the present invention described above can be applied to power converters such as inverters and converters in order to exhibit the functions described above. More specifically, it can be applied as a switching element such as a thyristor, a power transistor, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and the like. FIG. 14 is a block configuration diagram showing an example of a control system using a semiconductor device according to an embodiment of the present invention, and FIG. 15 is a circuit diagram of the same control system, which is particularly suitable for mounting on an electric vehicle. control system.
　図１４に示すように、制御システム５００はバッテリー（電源）５０１、昇圧コンバータ５０２、降圧コンバータ５０３、インバータ５０４、モータ（駆動対象）５０５、駆動制御部５０６を有し、これらは電気自動車に搭載されてなる。バッテリー５０１は例えばニッケル水素電池やリチウムイオン電池などの蓄電池からなり、給電ステーションでの充電あるいは減速時の回生エネルギーなどにより電力を貯蔵するとともに、電気自動車の走行系や電装系の動作に必要となる直流電圧を出力することができる。昇圧コンバータ５０２は例えばチョッパ回路を搭載した電圧変換装置であり、バッテリー５０１から供給される例えば２００Ｖの直流電圧を、チョッパ回路のスイッチング動作により例えば６５０Ｖに昇圧して、モータなどの走行系に出力することができる。降圧コンバータ５０３も同様にチョッパ回路を搭載した電圧変換装置であるが、バッテリー５０１から供給される例えば２００Ｖの直流電圧を、例えば１２Ｖ程度に降圧することで、パワーウインドーやパワーステアリング、あるいは車載の電気機器などを含む電装系に出力することができる。 As shown in FIG. 14, the control system 500 has a battery (power supply) 501, a boost converter 502, a step-down converter 503, an inverter 504, a motor (driven object) 505, and a drive control unit 506, which are mounted on an electric vehicle. It becomes The battery 501 is composed of a storage battery such as a nickel-metal hydride battery or a lithium-ion battery, and stores electric power by charging at a power supply station or regenerative energy during deceleration, and is necessary for the operation of the running system and electrical system of the electric vehicle. DC voltage can be output. The boost converter 502 is, for example, a voltage conversion device equipped with a chopper circuit, and boosts the DC voltage of, for example, 200 V supplied from the battery 501 to, for example, 650 V by the switching operation of the chopper circuit, and outputs it to a running system such as a motor. be able to. The step-down converter 503 is also a voltage converter equipped with a chopper circuit. It can be output to the electrical system including
　インバータ５０４は、昇圧コンバータ５０２から供給される直流電圧をスイッチング動作により三相の交流電圧に変換してモータ５０５に出力する。モータ５０５は電気自動車の走行系を構成する三相交流モータであり、インバータ５０４から出力される三相の交流電圧によって回転駆動され、その回転駆動力を図示しないトランスミッション等を介して電気自動車の車輪に伝達する。 The inverter 504 converts the DC voltage supplied from the boost converter 502 into a three-phase AC voltage by switching operation, and outputs the three-phase AC voltage to the motor 505 . A motor 505 is a three-phase AC motor that constitutes the driving system of the electric vehicle, and is rotationally driven by the three-phase AC voltage output from the inverter 504. The rotational driving force is transmitted to the wheels of the electric vehicle via a transmission or the like (not shown). to
　一方、図示しない各種センサを用いて、走行中の電気自動車から車輪の回転数やトルク、アクセルペダルの踏み込み量（アクセル量）などの実測値が計測され、これらの計測信号が駆動制御部５０６に入力される。また同時に、インバータ５０４の出力電圧値も駆動制御部５０６に入力される。駆動制御部５０６はＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）などの演算部やメモリなどのデータ保存部を備えたコントローラの機能を有するもので、入力された計測信号を用いて制御信号を生成してインバータ５０４にフィードバック信号として出力することで、スイッチング素子によるスイッチング動作を制御する。これによって、インバータ５０４がモータ５０５に与える交流電圧が瞬時に補正されることで、電気自動車の運転制御を正確に実行させることができ、電気自動車の安全・快適な動作が実現する。なお、駆動制御部５０６からのフィードバック信号を昇圧コンバータ５０２に与えることで、インバータ５０４への出力電圧を制御することも可能である。 On the other hand, various sensors (not shown) are used to measure actual values such as the number of revolutions and torque of the wheels and the amount of depression of the accelerator pedal (acceleration amount) from the running electric vehicle. is entered. At the same time, the output voltage value of inverter 504 is also input to drive control section 506 . The drive control unit 506 has the function of a controller equipped with a calculation unit such as a CPU (Central Processing Unit) and a data storage unit such as a memory. By outputting it as a feedback signal, the switching operation of the switching element is controlled. As a result, the AC voltage applied to the motor 505 by the inverter 504 is corrected instantaneously, so that the operation control of the electric vehicle can be accurately executed, and safe and comfortable operation of the electric vehicle is realized. It is also possible to control the output voltage to the inverter 504 by giving the feedback signal from the drive control unit 506 to the boost converter 502 .
　図１５は、図１４における降圧コンバータ５０３を除いた回路構成、すなわちモータ５０５を駆動するための構成のみを示した回路構成である。同図に示されるように、本発明の半導体装置は、例えばショットキーバリアダイオードとして昇圧コンバータ５０２およびインバータ５０４に採用されることでスイッチング制御に供される。昇圧コンバータ５０２においてはチョッパ回路に組み込まれてチョッパ制御を行い、またインバータ５０４においてはＩＧＢＴを含むスイッチング回路に組み込まれてスイッチング制御を行う。なお、バッテリー５０１の出力にインダクタ（コイルなど）を介在させることで電流の安定化を図り、またバッテリー５０１、昇圧コンバータ５０２、インバータ５０４のそれぞれの間にキャパシタ（電解コンデンサなど）を介在させることで電圧の安定化を図っている。 FIG. 15 is a circuit configuration excluding the step-down converter 503 in FIG. 14, that is, only a configuration for driving the motor 505. In FIG. As shown in the figure, the semiconductor device of the present invention is employed as a Schottky barrier diode in a boost converter 502 and an inverter 504 for switching control. Boost converter 502 is incorporated in a chopper circuit to perform chopper control, and inverter 504 is incorporated in a switching circuit including IGBTs to perform switching control. An inductor (such as a coil) is interposed in the output of the battery 501 to stabilize the current. It is stabilizing the voltage.
　また、図１５中に点線で示すように、駆動制御部５０６内にはＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）からなる演算部５０７と不揮発性メモリからなる記憶部５０８が設けられている。駆動制御部５０６に入力された信号は演算部５０７に与えられ、必要な演算を行うことで各半導体素子に対するフィードバック信号を生成する。また記憶部５０８は、演算部５０７による演算結果を一時的に保持したり、駆動制御に必要な物理定数や関数などをテーブルの形で蓄積して演算部５０７に適宜出力する。演算部５０７や記憶部５０８は公知の構成を採用することができ、その処理能力等も任意に選定できる。 In addition, as indicated by the dotted line in FIG. 15, the driving control unit 506 is provided with an operation unit 507 made up of a CPU (Central Processing Unit) and a storage unit 508 made up of a non-volatile memory. A signal input to the drive control unit 506 is supplied to the calculation unit 507, and a feedback signal for each semiconductor element is generated by performing necessary calculations. Further, the storage unit 508 temporarily holds the calculation result by the calculation unit 507, accumulates physical constants and functions required for drive control in the form of a table, and outputs them to the calculation unit 507 as appropriate. The calculation unit 507 and the storage unit 508 can employ known configurations, and their processing capabilities can be arbitrarily selected.
　図１４や図１５に示されるように、制御システム５００においては、昇圧コンバータ５０２、降圧コンバータ５０３、インバータ５０４のスイッチング動作にはダイオードやスイッチング素子であるサイリスタ、パワートランジスタ、ＩＧＢＴ、ＭＯＳＦＥＴ等が用いられる。これらの半導体素子に酸化ガリウム（Ｇａ２Ｏ３）、特にコランダム型酸化ガリウム（α－Ｇａ２Ｏ３）をその材料として用いることでスイッチング特性が大幅に向上する。さらに、本発明に係る半導体装置等を適用することで、極めて良好なスイッチング特性が期待できるとともに、制御システム５００の一層の小型化やコスト低減が実現可能となる。すなわち、昇圧コンバータ５０２、降圧コンバータ５０３、インバータ５０４のそれぞれが本発明による効果を期待できるものとなり、これらのいずれか一つ、もしくは任意の二つ以上の組合せ、あるいは駆動制御部５０６も含めた形態のいずれにおいても本発明の効果を期待することができる。
　なお、上述の制御システム５００は本発明の半導体装置を電気自動車の制御システムに適用できるだけではなく、直流電源からの電力を昇圧・降圧したり、直流から交流へ電力変換するといったあらゆる用途の制御システムに適用することが可能である。また、バッテリーとして太陽電池などの電源を用いることも可能である。 As shown in FIGS. 14 and 15, in the control system 500, diodes and switching elements such as thyristors, power transistors, IGBTs, MOSFETs, and the like are used for the switching operations of the boost converter 502, the step-down converter 503, and the inverter 504. . By using gallium oxide (Ga 2 O 3 ), especially corundum-type gallium oxide (α-Ga 2 O 3 ), as the material for these semiconductor elements, the switching characteristics are greatly improved. Furthermore, by applying the semiconductor device or the like according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be realized. That is, each of the boost converter 502, the step-down converter 503, and the inverter 504 can expect the effects of the present invention. The effect of the present invention can be expected in any of the above.
Note that the control system 500 described above can apply the semiconductor device of the present invention not only to the control system of an electric vehicle, but also to a control system for various purposes such as stepping up or stepping down power from a DC power supply or converting power from DC to AC. can be applied to It is also possible to use a power source such as a solar cell as the battery.
　図１６は、本発明の実施態様に係る半導体装置を採用した制御システムの他の例を示すブロック構成図、図１７は同制御システムの回路図であり、交流電源からの電力で動作するインフラ機器や家電機器等への搭載に適した制御システムである。 FIG. 16 is a block configuration diagram showing another example of a control system employing a semiconductor device according to an embodiment of the present invention, and FIG. 17 is a circuit diagram of the same control system, showing infrastructure equipment that operates on power from an AC power supply. This control system is suitable for installation in home appliances, etc.
　図１６に示すように、制御システム６００は、外部の例えば三相交流電源（電源）６０１から供給される電力を入力するもので、ＡＣ／ＤＣコンバータ６０２、インバータ６０４、モータ（駆動対象）６０５、駆動制御部６０６を有し、これらは様々な機器（後述する）に搭載することができる。三相交流電源６０１は、例えば電力会社の発電施設（火力発電所、水力発電所、地熱発電所、原子力発電所など）であり、その出力は変電所を介して降圧されながら交流電圧として供給される。また、例えば自家発電機等の形態でビル内や近隣施設内に設置されて電力ケーブルで供給される。ＡＣ／ＤＣコンバータ６０２は交流電圧を直流電圧に変換する電圧変換装置であり、三相交流電源６０１から供給される１００Ｖや２００Ｖの交流電圧を所定の直流電圧に変換する。具体的には、電圧変換により３．３Ｖや５Ｖ、あるいは１２Ｖといった、一般的に用いられる所望の直流電圧に変換される。駆動対象がモータである場合には１２Ｖへの変換が行われる。なお、三相交流電源に代えて単相交流電源を採用することも可能であり、その場合にはＡＣ／ＤＣコンバータを単相入力のものとすれば同様のシステム構成とすることができる。 As shown in FIG. 16, a control system 600 receives power supplied from an external, for example, a three-phase AC power source (power source) 601, and includes an AC/DC converter 602, an inverter 604, a motor (to be driven) 605, It has a drive control unit 606, which can be mounted on various devices (described later). The three-phase AC power supply 601 is, for example, a power generation facility of an electric power company (a thermal power plant, a hydroelectric power plant, a geothermal power plant, a nuclear power plant, etc.), and its output is stepped down via a substation and supplied as an AC voltage. be. In addition, for example, in the form of a private power generator or the like, it is installed in a building or in a nearby facility and supplied by a power cable. The AC/DC converter 602 is a voltage conversion device that converts AC voltage into DC voltage, and converts AC voltage of 100V or 200V supplied from the three-phase AC power supply 601 into a predetermined DC voltage. Specifically, the voltage is converted into a generally used desired DC voltage such as 3.3V, 5V, or 12V. When the object to be driven is a motor, conversion to 12V is performed. A single-phase AC power supply may be used instead of the three-phase AC power supply. In that case, the same system configuration can be achieved by using a single-phase input AC/DC converter.
　インバータ６０４は、ＡＣ／ＤＣコンバータ６０２から供給される直流電圧をスイッチング動作により三相の交流電圧に変換してモータ６０５に出力する。モータ６０４は、制御対象によりその形態が異なるが、制御対象が電車の場合には車輪を、工場設備の場合にはポンプや各種動力源を、家電機器の場合にはコンプレッサなどを駆動するための三相交流モータであり、インバータ６０４から出力される三相の交流電圧によって回転駆動され、その回転駆動力を図示しない駆動対象に伝達する。 The inverter 604 converts the DC voltage supplied from the AC/DC converter 602 into a three-phase AC voltage by switching operation, and outputs the three-phase AC voltage to the motor 605 . The form of the motor 604 differs depending on the object to be controlled. When the object to be controlled is a train, the motor 604 drives the wheels. It is a three-phase AC motor, and is rotationally driven by a three-phase AC voltage output from an inverter 604, and transmits its rotational driving force to a drive target (not shown).
　なお、例えば家電機器においてはＡＣ／ＤＣコンバータ３０２から出力される直流電圧をそのまま供給することが可能な駆動対象も多く（例えばパソコン、ＬＥＤ照明機器、映像機器、音響機器など）、その場合には制御システム６００にインバータ６０４は不要となり、図１４中に示すように、ＡＣ／ＤＣコンバータ６０２から駆動対象に直流電圧を供給する。この場合、例えばパソコンなどには３．３Ｖの直流電圧が、ＬＥＤ照明機器などには５Ｖの直流電圧が供給される。 For example, in home appliances, there are many objects to be driven that can be directly supplied with the DC voltage output from the AC/DC converter 302 (for example, personal computers, LED lighting equipment, video equipment, audio equipment, etc.). The control system 600 does not require the inverter 604, and as shown in FIG. 14, the DC voltage is supplied from the AC/DC converter 602 to the driven object. In this case, for example, a personal computer is supplied with a DC voltage of 3.3V, and an LED lighting device is supplied with a DC voltage of 5V.
　一方、図示しない各種センサを用いて、駆動対象の回転数やトルク、あるいは駆動対象の周辺環境の温度や流量などといった実測値が計測され、これらの計測信号が駆動制御部６０６に入力される。また同時に、インバータ６０４の出力電圧値も駆動制御部６０６に入力される。これらの計測信号をもとに、駆動制御部６０６はインバータ６０４にフィードバック信号を与え、スイッチング素子によるスイッチング動作を制御する。これによって、インバータ６０４がモータ６０５に与える交流電圧が瞬時に補正されることで、駆動対象の運転制御を正確に実行させることができ、駆動対象の安定した動作が実現する。また、上述のように、駆動対象が直流電圧で駆動可能な場合には、インバータへのフィードバックに代えてＡＣ／ＤＣコンバータ６０２をフィードバック制御することも可能である。 On the other hand, various sensors (not shown) are used to measure actual values such as the rotation speed and torque of the driven object, or the temperature and flow rate of the surrounding environment of the driven object, and these measurement signals are input to the drive control unit 606. At the same time, the output voltage value of inverter 604 is also input to drive control section 606 . Based on these measurement signals, drive control section 606 gives a feedback signal to inverter 604 to control the switching operation of the switching element. As a result, the AC voltage applied to the motor 605 by the inverter 604 is corrected instantaneously, so that the operation control of the object to be driven can be accurately executed, and the object to be driven can be operated stably. Further, as described above, when the object to be driven can be driven with a DC voltage, it is possible to feedback-control the AC/DC converter 602 instead of the feedback to the inverter.
　図１７は、図１６の回路構成を示したものである。同図に示されるように、本発明の半導体装置は、例えばショットキーバリアダイオードとしてＡＣ／ＤＣコンバータ６０２およびインバータ６０４に採用されることでスイッチング制御に供される。ＡＣ／ＤＣコンバータ６０２は、例えばショットキーバリアダイオードをブリッジ状に回路構成したものが用いられ、入力電圧の負電圧分を正電圧に変換整流することで直流変換を行う。またインバータ６０４においてはＩＧＢＴにおけるスイッチング回路に組み込まれてスイッチング制御を行う。なお、ＡＣ／ＤＣコンバータ６０２とインバータ６０４の間にキャパシタ（電解コンデンサなど）を介在させることで電圧の安定化を図っている。 FIG. 17 shows the circuit configuration of FIG. As shown in the figure, the semiconductor device of the present invention is employed as a Schottky barrier diode in an AC/DC converter 602 and an inverter 604 for switching control. The AC/DC converter 602 uses, for example, a Schottky barrier diode circuit configured in a bridge shape, and performs DC conversion by converting and rectifying the negative voltage component of the input voltage into a positive voltage. Also, the inverter 604 is incorporated in the switching circuit in the IGBT to perform switching control. A capacitor (such as an electrolytic capacitor) is interposed between the AC/DC converter 602 and the inverter 604 to stabilize the voltage.
　また、図１７中に点線で示すように、駆動制御部６０６内にはＣＰＵからなる演算部６０７と不揮発性メモリからなる記憶部６０８が設けられている。駆動制御部６０６に入力された信号は演算部６０７に与えられ、必要な演算を行うことで各半導体素子に対するフィードバック信号を生成する。また記憶部６０８は、演算部６０７による演算結果を一時的に保持したり、駆動制御に必要な物理定数や関数などをテーブルの形で蓄積して演算部６０７に適宜出力する。演算部６０７や記憶部６０８は公知の構成を採用することができ、その処理能力等も任意に選定できる。 Further, as indicated by the dotted line in FIG. 17, the drive control unit 606 is provided with an operation unit 607 made up of a CPU and a storage unit 608 made up of a non-volatile memory. A signal input to the drive control unit 606 is supplied to the calculation unit 607, and a feedback signal for each semiconductor element is generated by performing necessary calculations. The storage unit 608 also temporarily stores the results of calculations by the calculation unit 607, accumulates physical constants and functions necessary for drive control in the form of a table, and outputs them to the calculation unit 607 as appropriate. The calculation unit 607 and the storage unit 608 can employ known configurations, and their processing capabilities can be arbitrarily selected.
　このような制御システム６００においても、図１４や図１５に示した制御システム５００と同様に、ＡＣ／ＤＣコンバータ６０２やインバータ６０４の整流動作やスイッチング動作にはダイオードやスイッチング素子であるサイリスタ、パワートランジスタ、ＩＧＢＴ、ＭＯＳＦＥＴ等が用いられる。これら半導体素子に酸化ガリウム（Ｇａ２Ｏ３）、特にコランダム型酸化ガリウム（α－Ｇａ２Ｏ３）をその材料として用いることでスイッチング特性が向上する。さらに、本発明に係る半導体膜や半導体装置を適用することで、極めて良好なスイッチング特性が期待できるとともに、制御システム６００の一層の小型化やコスト低減が実現可能となる。すなわち、ＡＣ／ＤＣコンバータ６０２、インバータ６０４のそれぞれが本発明による効果を期待できるものとなり、これらのいずれか一つ、もしくは組合せ、あるいは駆動制御部６０６も含めた形態のいずれにおいても本発明の効果を期待することができる。 In such a control system 600, as in the control system 500 shown in FIGS. 14 and 15, the rectifying operation and switching operation of the AC/DC converter 602 and the inverter 604 are performed by diodes, switching elements such as thyristors and power transistors. , IGBT, MOSFET, etc. are used. Switching characteristics are improved by using gallium oxide (Ga 2 O 3 ), particularly corundum type gallium oxide (α-Ga 2 O 3 ), as the material for these semiconductor elements. Furthermore, by applying the semiconductor film and the semiconductor device according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be realized. That is, the AC/DC converter 602 and the inverter 604 can each be expected to have the effect of the present invention. can be expected.
　なお、図１６および図１７では駆動対象としてモータ６０５を例示したが、駆動対象は必ずしも機械的に動作するものに限られず、交流電圧を必要とする多くの機器を対象とすることができる。制御システム６００においては、交流電源から電力を入力して駆動対象を駆動する限りにおいては適用が可能であり、インフラ機器（例えばビルや工場等の電力設備、通信設備、交通管制機器、上下水処理設備、システム機器、省力機器、電車など）や家電機器（例えば、冷蔵庫、洗濯機、パソコン、ＬＥＤ照明機器、映像機器、音響機器など）といった機器を対象とした駆動制御のために搭載することができる。 Although FIGS. 16 and 17 exemplify the motor 605 as an object to be driven, the object to be driven is not necessarily limited to mechanically operating objects, and can be applied to many devices that require AC voltage. In the control system 600, as long as the drive object is driven by inputting power from an AC power supply, it can be applied to infrastructure equipment (for example, power equipment such as buildings and factories, communication equipment, traffic control equipment, water and sewage treatment Equipment, system equipment, labor-saving equipment, trains, etc.) and home appliances (e.g., refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.). can.
　本発明の半導体装置は、半導体（例えば化合物半導体電子デバイス等）、電子部品・電気機器部品、光学・電子写真関連装置、工業部材などあらゆる分野に用いることができるが、とりわけ、パワーデバイスに有用である。 The semiconductor device of the present invention can be used in various fields such as semiconductors (for example, compound semiconductor electronic devices), electronic parts/electrical equipment parts, optical/electrophotographic equipment, industrial materials, etc., but it is particularly useful for power devices. be.
　１　　　　　ソース領域（ｎ＋型半導体層）
　２　　　　　電流遮断層
　３　　　　　ｎ－型半導体層
　４ａ　　　　ゲート絶縁膜
　４ｂ　　　　層間絶縁膜
　５ａ　　　　ゲート電極
　５ｂ　　　　ソース電極
　５ｃ　　　　ドレイン電極
　６　　　　　チャネル層
　７　　　　　ｎ－型半導体層
　８　　　　　結晶性酸化物半導体層
　９　　　　　基板
　２１　　　　成膜装置（ミストＣＶＤ装置）
　２２ａ　　　キャリアガス源
　２２ｂ　　　キャリアガス（希釈）源
　２３ａ　　　流量調節弁
　２３ｂ　　　流量調節弁
　２４　　　　ミスト発生源
　２４ａ　　　原料溶液
　２４ｂ　　　原料微粒子
　２５　　　　容器
　２５ａ　　　水
　２６　　　　超音波振動子
　２７　　　　成膜室
　２８　　　　ホットプレート
　２９　　　　供給管
　３０　　　　基板
　５００　　　制御システム
　５０１　　　バッテリー（電源）
　５０２　　　昇圧コンバータ
　５０３　　　降圧コンバータ
　５０４　　　インバータ
　５０５　　　モータ（駆動対象）
　５０６　　　駆動制御部
　５０７　　　演算部
　５０８　　　記憶部
　６００　　　制御システム
　６０１　　　三相交流電源（電源）
　６０２　　　ＡＣ／ＤＣコンバータ
　６０４　　　インバータ
　６０５　　　モータ（駆動対象）
　６０６　　　駆動制御部
　６０７　　　演算部
　６０８　　　記憶部 1 source region (n + type semiconductor layer)
2 current blocking layer 3 n-type semiconductor layer 4a gate insulating film 4b interlayer insulating film 5a gate electrode 5b source electrode 5c drain electrode 6 channel layer 7 n-type semiconductor layer 8 crystalline oxide semiconductor layer 9 substrate 21 film forming apparatus ( mist CVD equipment)
22a Carrier gas source 22b Carrier gas (dilution) source 23a Flow control valve 23b Flow control valve 24 Mist generation source 24a Raw material solution 24b Raw fine particles 25 Container 25a Water 26 Ultrasonic vibrator 27 Film forming chamber 28 Hot plate 29 Supply pipe 30 Substrate 500 control system 501 battery (power supply)
502 Boost converter 503 Buck converter 504 Inverter 505 Motor (driven object)
506 drive control unit 507 calculation unit 508 storage unit 600 control system 601 three-phase AC power supply (power supply)
602 AC/DC converter 604 Inverter 605 Motor (to be driven)
606 drive control unit 607 calculation unit 608 storage unit

Claims (14)

  1. 　チャネル層およびドリフト層を含む結晶性酸化物半導体層と、該チャネル層上にゲート絶縁膜を介して配置されているゲート電極と、前記チャネル層と前記ドリフト層との間に配置されている電流遮断層とを少なくとも備える半導体装置であって、前記電流遮断層がドーパント元素を含有し、前記電流遮断層中に、前記ドーパント元素の濃度が５．０×１０１７／ｃｍ３以上である領域を含むことを特徴とする半導体装置。 A crystalline oxide semiconductor layer including a channel layer and a drift layer, a gate electrode arranged on the channel layer with a gate insulating film interposed therebetween, and a current arranged between the channel layer and the drift layer and a blocking layer, wherein the current blocking layer contains a dopant element, and the current blocking layer has a region in which the concentration of the dopant element is 5.0×10 17 /cm 3 or more. A semiconductor device comprising:
  2. 　前記ドーパント元素が、ｐ型ドーパントの元素である請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the dopant element is a p-type dopant element.
  3. 　前記電流遮断層中の前記ドーパント元素の濃度が１．０×１０１８／ｃｍ３以上である請求項１または２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the concentration of said dopant element in said current blocking layer is 1.0*10< 18 >/cm< 3 > or more.
  4. 　前記電流遮断層中の前記ドーパント元素の濃度が５．０×１０１７／ｃｍ３以上である領域の厚みが２００ｎｍ以上である請求項１～３のいずれかに記載の半導体装置。 4. The semiconductor device according to claim 1, wherein the thickness of the region of the current blocking layer where the concentration of the dopant element is 5.0×10 17 /cm 3 or more is 200 nm or more.
  5. 　前記ドーパント元素がイオン注入によってドーピングされている請求項１～４のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 4, wherein the dopant element is doped by ion implantation.
  6. 　前記電流遮断層が、結晶性酸化物を主成分として含む請求項１～５のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 5, wherein the current blocking layer contains a crystalline oxide as a main component.
  7. 　前記チャネル層の少なくとも一部にソース領域を有しており、前記ソース領域上にソース電極を備えている請求項１～６のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 6, wherein at least part of said channel layer has a source region, and a source electrode is provided on said source region.
  8. 　前記ソース電極が、前記電流遮断層とコンタクトを形成している請求項１～７のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 7, wherein said source electrode forms a contact with said current blocking layer.
  9. 　前記結晶性酸化物半導体層が、少なくとも前記チャネル層を貫通するトレンチを有しており、該トレンチ内に前記ゲート電極の少なくとも一部が前記ゲート絶縁膜を介して埋め込まれている請求項１～８のいずれかに記載の半導体装置。 2. The crystalline oxide semiconductor layer has a trench penetrating at least the channel layer, and at least part of the gate electrode is embedded in the trench via the gate insulating film. 9. The semiconductor device according to any one of 8.
  10. 　前記結晶性酸化物半導体層が、アルミニウム、インジウムおよびガリウムから選ばれる少なくとも１種の金属を含有する請求項１～９のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 9, wherein the crystalline oxide semiconductor layer contains at least one metal selected from aluminum, indium and gallium.
  11. 　前記結晶性酸化物半導体層が、コランダム構造を有する請求項１～１０のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 10, wherein the crystalline oxide semiconductor layer has a corundum structure.
  12. 　トランジスタである請求項１～１１のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 11, which is a transistor.
  13. 　請求項１～１２のいずれかに記載の半導体装置を用いた電力変換装置。 A power converter using the semiconductor device according to any one of claims 1 to 12.
  14. 　請求項１～１２のいずれかに記載の半導体装置を用いた制御システム。

          A control system using the semiconductor device according to any one of claims 1 to 12.
PCT/JP2022/018790 2021-04-26 2022-04-25 Semiconductor device WO2022230834A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018060992A (en) * 2015-12-18 2018-04-12 株式会社Flosfia Semiconductor device
JP2018186246A (en) * 2017-04-27 2018-11-22 国立研究開発法人情報通信研究機構 Ga2O3-BASED SEMICONDUCTOR DEVICE

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018060992A (en) * 2015-12-18 2018-04-12 株式会社Flosfia Semiconductor device
JP2018186246A (en) * 2017-04-27 2018-11-22 国立研究開発法人情報通信研究機構 Ga2O3-BASED SEMICONDUCTOR DEVICE

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
WONG MAN HOI; MURAKAMI HISASHI; KUMAGAI YOSHINAO; HIGASHIWAKI MASATAKA: "Enhancement-Mode $\beta$ -Ga2O3 Current Aperture Vertical MOSFETs With N-Ion-Implanted Blocker", IEEE ELECTRON DEVICE LETTERS, vol. 41, no. 2, 26 December 2019 (2019-12-26), USA, pages 296 - 299, XP011768906, ISSN: 0741-3106, DOI: 10.1109/LED.2019.2962657 *

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