JP2022187480A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device with reduced leakage current, especially useful for a power device.SOLUTION: A semiconductor device has at least an n+ type semiconductor layer, an n-type semiconductor layer disposed on the n+ type semiconductor layer, a high resistivity layer at least partially embedded in the n-type semiconductor layer, and a Schottky electrode forming a Schottky junction with the n-type semiconductor layer, and the n+ type semiconductor layer and the n-type semiconductor layer each contain a crystalline oxide semiconductor as a major component, the distance between the bottom surface of said high-resistance layer and the top surface of the n+ type semiconductor layer is less than 1.5 μm, and the edge of the Schottky electrode is located above the high-resistance layer.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device useful as a power device or the like.

Gallium oxide (Ga ₂ O ₃ ) is a transparent semiconductor that has a wide bandgap of 4.8-5.3 eV at room temperature and hardly absorbs visible and ultraviolet light. It is therefore a particularly promising material for use in _{opto -} electronic devices and transparent electronics operating in the deep UV region. Light-emitting diodes (LEDs) and transistors have been developed (see Non-Patent Document 1). According to Patent Document 3, the gallium oxide can control the bandgap by forming a mixed crystal of indium and aluminum, respectively, or in combination, and constitutes an extremely attractive material system as an InAlGaO-based semiconductor. . Here, the InAlGaO-based semiconductor indicates _{InXAlYGaZO3 (} 0≦ _X ≦2, 0≦ _Y ≦2, 0≦Z≦2, X+Y+Z=1.5 to 2.5), and gallium oxide. It can be viewed from a bird's-eye view as the same material system that is included.

Gallium oxide (Ga ₂ O ₃ ) has five crystal structures α, β, γ, σ, and ε, and generally the most stable structure is β-Ga ₂ O ₃ . However, since β-Ga ₂ O ₃ has a β-Gallic structure, it is not necessarily suitable for use in semiconductor devices, unlike crystal systems generally used in electronic materials and the like. In addition, since the growth of the β-Ga ₂ O ₃ thin film requires a high substrate temperature and a high degree of vacuum, there is also the problem of increased manufacturing costs. In addition, as described in Non-Patent Document 2, in β-Ga ₂ O ₃ , even a high concentration (for example, 1×10 ¹⁹ /cm ³ or more) of dopant (Si) is 800% after ion implantation. C. to 1100.degree. C., it could not be used as a donor without annealing.
On the other hand, α-Ga ₂ O ₃ has the same crystal structure as the sapphire substrate that has already been widely used, so it is suitable for use in optoelectronic devices, and has a wider band than β-Ga ₂ O ₃ . Since it has a gap, it is particularly useful for power devices. Therefore, semiconductor devices using α-Ga ₂ O ₃ as a semiconductor are eagerly awaited.

Patent Document 1 discloses a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide provided on the semiconductor substrate, an anode electrode in Schottky contact with the drift layer, and a cathode in ohmic contact with the semiconductor substrate. electrodes, and the drift layer has a peripheral trench provided at a position surrounding the anode electrode in plan view. Further, Patent Document 2 describes a Ga ₂ O ₃ -based high-resistance crystal layer having a thickness of 750 nm or less including Mg and ion implantation damage, and a Mg concentration higher than that of the Ga ₂ O ₃ -based high-resistance crystal layer. and an impurity concentration gradient layer with a thickness of 100 nm or more under the Ga ₂ O ₃ -based high resistance crystal layer in which the Mg concentration is low and the Mg concentration is graded in the depth direction. ing.
However, the semiconductor devices described in Patent Documents 1 and 2 have a problem of leakage current near the end of the Schottky electrode or at the interface between the Schottky electrode and the high resistance crystal layer, and are practically satisfactory as a semiconductor device. I couldn't get what I could.

JP 2019-050290 A Japanese Patent No. 6344718 WO2014/050793

Jun Liang Zhao et al, “UV and Visible Electroluminescence From a Sn:Ga2O3/n+-Si Heterojunction by Metal-Organic Chemical Vapor Deposition”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.58, NO.5 MAY 2011 Kohei Sasaki et al, “Si-Ion Implantation Doping in β-Ga2O3 and Its Application to Fabrication of Low-Resistance Ohmic Contacts”, Applied Physics Express 6 (2013) 086502

An object of the present invention is to provide a semiconductor device in which leak current is suppressed.

As a result of intensive studies aimed at achieving the above object, the present inventors have found that an n + -type semiconductor layer, an n - -type semiconductor layer disposed on the n + -type semiconductor layer, at least a portion of the n - -type semiconductor layer and a Schottky electrode, wherein the n+ type semiconductor layer and the n− type semiconductor layer each contain a crystalline oxide semiconductor as a main component, and the high resistance The distance between the bottom surface of the layer and the top surface of the n + -type semiconductor layer is less than 1.5 μm, and the end of the Schottky electrode is located on the high resistance semiconductor device, We have found that the current can be reduced, and that the semiconductor device thus obtained can solve the above-described conventional problems.
Moreover, after obtaining the above knowledge, the inventors of the present invention completed the present invention through further studies.

Specifically, the present invention relates to the following inventions.
[1] an n+ type semiconductor layer, an n− type semiconductor layer disposed on the n+ type semiconductor layer, a high resistance layer at least partially embedded in the n− type semiconductor layer, and the n− type A semiconductor device comprising at least a Schottky electrode forming a Schottky junction with a semiconductor layer,
The n+ type semiconductor layer and the n− type semiconductor layer each contain a crystalline oxide semiconductor as a main component, and the distance between the bottom surface of the high resistance layer and the top surface of the n+ type semiconductor layer is less than 1.5 μm. A semiconductor device characterized by:
[2] The semiconductor device according to [1], wherein the crystalline oxide semiconductor contains one or more metals selected from aluminum, indium and gallium.
[3] The semiconductor device according to [1] or [2], wherein the crystalline oxide semiconductor contains at least gallium.
[4] The semiconductor device according to any one of [1] to [3], wherein the crystalline oxide semiconductor has a corundum structure or a β-gallia structure.
[5] The semiconductor device according to any one of [1] to [4], wherein the distance between the bottom surface of the high resistance layer and the top surface of the n + -type semiconductor layer is 1.0 μm or less.
[6] any of the above [1] to [5], wherein the bottom surface of the high resistance layer is at the same height as the top surface of the n + -type semiconductor layer, or located below the top surface of the n + -type semiconductor layer; 1. The semiconductor device according to claim 1.
[7] The semiconductor device according to any one of [1] to [6], wherein the high resistance layer contains SiO ₂ .
[8] The above [1] to [7], further comprising an insulator layer formed on the n-type semiconductor layer, and an end portion of the Schottky electrode is located on the insulator layer. The semiconductor device according to any one of 1.
[9] The high resistance layer has a first region located inside the semiconductor device and a second region located outside the semiconductor device, and the bottom surface of the first region and the n + -type Any one of the above [1] to [8], wherein the distance from the top surface of the semiconductor layer is less than 1.5 μm, and the bottom surface of the second region is located above the bottom surface of the first region. The semiconductor device according to .
[10] The semiconductor device according to any one of [1] to [9], further comprising a passivation film covering the outer edge of the Schottky electrode and at least part of the surface of the n− semiconductor layer.
[11] The semiconductor device according to any one of [1] to [10], which is a diode.
[12] The semiconductor device according to any one of [1] to [11], which is a power device.
[13] A power converter using the semiconductor device according to any one of [1] to [12].
[14] A control system using the semiconductor device according to any one of [1] to [12].

According to the present invention, leak current in a semiconductor device can be suppressed.

1 is a diagram schematically showing a Schottky barrier diode (SBD) according to an embodiment of the invention; FIG. FIG. 4 is a diagram schematically showing a preferred manufacturing process of a Schottky barrier diode (SBD) according to an embodiment of the invention; 1 is a diagram schematically showing a Schottky barrier diode (SBD) according to an embodiment of the invention; FIG. 1 is a diagram schematically showing a Schottky barrier diode (SBD) according to an embodiment of the invention; FIG. 1 is a configuration diagram of a mist CVD apparatus used in an embodiment of the present invention; FIG. FIG. 10 is a diagram showing simulation results in an example and a comparative example; FIG. 10 is a diagram showing simulation results in an example and a comparative example; 1 is a block configuration diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention; FIG. 1 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention; FIG. 1 is a block configuration diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention; FIG. 1 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention; FIG. 1 is a diagram schematically showing a Schottky barrier diode (SBD) according to an embodiment of the invention; FIG. It is a figure which shows the observation result of the cross-sectional scanning electron microscope (SEM) in an Example. It is a figure which shows the observation result of the cross-sectional scanning electron microscope (SEM) in a comparative example. FIG. 4 is a diagram showing the results of IV measurements in Examples and Comparative Examples. FIG. 4 is a diagram showing results of IV measurement in Examples. FIG. 4 is a diagram schematically showing a Schottky barrier diode (SBD) according to another embodiment of the invention; FIG. 4 is a diagram showing results of IV measurement in Examples. The vertical and horizontal axes are in arbitrary units.

A semiconductor device of the present invention comprises an n+ type semiconductor layer, an n− type semiconductor layer disposed on the n+ type semiconductor layer, a high resistance layer at least partially embedded in the n− type semiconductor layer, and at least a Schottky electrode forming a Schottky junction with the n− type semiconductor layer, wherein the n+ type semiconductor layer and the n− type semiconductor layer each contain a crystalline oxide semiconductor as a main component. and a distance between the bottom surface of the high resistance layer and the top surface of the n+ type semiconductor layer is less than 1.5 μm.

The n+ type semiconductor layer is not particularly limited as long as it has a higher carrier density than the n− type semiconductor layer and contains a crystalline oxide semiconductor as a main component. Examples of the crystalline oxide semiconductor include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt and iridium. be done. In an embodiment of the present invention, the crystalline oxide semiconductor preferably contains at least one metal selected from aluminum, indium and gallium, more preferably at least gallium, and α-Ga ₂ O ₃ or mixed crystals thereof are most preferred. According to the embodiments of the present invention, it is possible to satisfactorily reduce leakage current even when a semiconductor having a large bandgap such as gallium oxide or a mixed crystal thereof is used. The crystal structure of the crystalline oxide semiconductor is also not particularly limited as long as the object of the present invention is not hindered. The crystal structure of the crystalline oxide semiconductor includes, for example, a corundum structure, a β-gallia structure, a hexagonal structure (eg, ε-type structure, etc.), an orthogonal crystal structure (eg, κ-type structure, etc.), a cubic crystal structure, or A tetragonal crystal structure and the like can be mentioned. In an embodiment of the present invention, the crystalline oxide semiconductor preferably has a corundum structure, a β-gallia structure or a hexagonal crystal structure (eg, ε-type structure, etc.), and more preferably has a corundum structure. Note that the “main component” means that the crystalline oxide semiconductor accounts for preferably 50% or more, more preferably 70% or more, and even more preferably 90%, in atomic ratio, of all components of the n + -type semiconductor layer. % or more, and may be 100%. Also, the thickness of the n+ type semiconductor layer is not particularly limited, and may be 1 μm or less or 1 μm or more. In an embodiment of the present invention, the thickness of the n+ type semiconductor layer is preferably 1 μm or more, more preferably 3 μm or more. The area of the semiconductor film in plan view is not particularly limited, but may be 1 mm ² or more or 1 mm ² or less, preferably 10 mm ² to 300 cm ² , and 100 mm ² to 100 cm ² . is more preferable. Moreover, the +-type semiconductor layer is usually single crystal, but may be polycrystal. The carrier density of the semiconductor layer can be appropriately set by adjusting the doping amount.

The n+ type semiconductor layer preferably contains a dopant. The dopant is not particularly limited and may be a known one. In the embodiment of the present invention, particularly when the semiconductor layer is mainly composed of a crystalline oxide semiconductor containing gallium, preferred examples of the dopant include tin, germanium, silicon, titanium, zirconium, n-type dopants such as vanadium or niobium are included. In an embodiment of the present invention, said n-type dopant is preferably Sn, Ge or Si. The content of the dopant is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and more preferably 0.00001 atomic % to 10 atomic % in the composition of the semiconductor layer. is most preferred. More specifically, the dopant concentration may typically be between about 1×10 ¹⁶ /cm ³ and 1×10 ²² /cm ³ . Embodiments of the present invention may contain dopants at high concentrations of about 1×10 ²⁰ /cm ³ or higher. In the embodiment of the present invention, it is preferable to contain the carrier concentration of 1×10 ¹⁷ /cm ³ or more.

The n− type semiconductor layer is not particularly limited as long as it is a semiconductor layer having a lower carrier density than the n+ type semiconductor layer and containing a crystalline oxide semiconductor as a main component. Examples of the crystalline oxide semiconductor include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt and iridium. can give. In an embodiment of the present invention, the crystalline oxide semiconductor preferably contains at least one metal selected from aluminum, indium and gallium, more preferably at least gallium, and α-Ga ₂ O ₃ or mixed crystals thereof are most preferred. Note that in the embodiment of the present invention, the crystalline oxide semiconductor that is the main component of the n + -type semiconductor layer and the crystalline oxide semiconductor that is the main component of the n − -type semiconductor layer are the same. may be different. The crystal structure of the crystalline oxide semiconductor is also not particularly limited as long as the object of the present invention is not hindered. The crystal structure of the crystalline oxide semiconductor includes, for example, a corundum structure, a β-gallia structure, a hexagonal structure (eg, ε-type structure, etc.), an orthogonal crystal structure (eg, κ-type structure, etc.), a cubic crystal structure, or A tetragonal crystal structure and the like can be mentioned. In an embodiment of the present invention, the crystalline oxide semiconductor preferably has a corundum structure, a β-gallia structure or a hexagonal crystal structure (eg, ε-type structure, etc.), and more preferably has a corundum structure. The “main component” means that the crystalline oxide semiconductor accounts for preferably 50% or more, more preferably 70% or more, and even more preferably 70% or more, in atomic ratio, of all components of the n-type semiconductor layer. It means that 90% or more is included, and that it may be 100%. The thickness of the n-type semiconductor layer is not particularly limited, and may be 1 μm or less or 1 μm or more. preferable. The area of the semiconductor film in plan view is not particularly limited, but may be 1 mm ² or more or 1 mm ² or less, preferably 10 mm ² to 300 cm ² , and 100 mm ² to 100 cm ² . is more preferable. Further, the semiconductor layer is usually single crystal, but may be polycrystal. The carrier density of the semiconductor layer can be appropriately set by adjusting the doping amount.

The n-type semiconductor layer may contain a dopant. The dopant is not particularly limited and may be a known one. In the embodiment of the present invention, particularly when the semiconductor layer is mainly composed of a crystalline oxide semiconductor containing gallium, preferred examples of the dopant include tin, germanium, silicon, titanium, zirconium, n-type dopants such as vanadium or niobium are included. In an embodiment of the present invention, said n-type dopant is preferably Sn, Ge or Si. The content of the dopant is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and more preferably 0.00001 atomic % to 10 atomic % in the composition of the semiconductor layer. is most preferred. More specifically, the dopant concentration may typically be about 1×10 ¹⁶ /cm ³ to 1×10 ²² /cm ³ , and the dopant concentration may be, for example, about 1×10 ¹⁷ /cm 3 . A low concentration of ³ or less may be used.

The high resistance layer is not particularly limited as long as at least part of the high resistance layer is embedded in the n-type semiconductor layer. The high resistance layer usually has a resistance of 1.0×10 ⁶ Ω·cm or more. In an embodiment of the present invention, the resistance of the high resistance layer is preferably 1.0×10 ¹⁰ Ω·cm or more, and the resistance of the high resistance layer is 1.0×10 ¹² Ω·cm or more. is more preferred. The resistance can be measured by forming an electrode for measurement on the high resistance layer and applying a current. The upper limit of the resistance is not particularly limited. The upper limit of the resistance is preferably 1.0×10 ¹⁵ Ω·cm, more preferably 1.0×10 ¹⁴ Ω·cm. The constituent material of the high resistance layer is not particularly limited as long as it does not hinder the object of the present invention. In an embodiment of the present invention, the high resistance layer is preferably an insulator layer. In this case, the constituent material of the high resistance layer includes, for example, SiO ₂ , phosphorus-added SiO ₂ (PSG), boron-added SiO ₂ , phosphorus-boron-added SiO ₂ (BPSG), and the like. Examples of means for forming the high resistance layer include CVD, atmospheric pressure CVD, plasma CVD, mist CVD, and the like. In an embodiment of the present invention, the means for forming the high resistance layer is preferably mist CVD or atmospheric pressure CVD. Further, in the embodiment of the present invention, it is also preferable that the main component of the high resistance layer is the crystalline oxide semiconductor. When the main component of the high resistance layer is the crystalline oxide semiconductor, the high resistance layer preferably contains a p-type dopant. Examples of the p-type dopant include magnesium, calcium, zinc and the like.

The distance between the bottom surface of the high resistance layer and the top surface of the n+ type semiconductor layer is not particularly limited as long as it is less than 1.5 μm. In an embodiment of the present invention, the distance between the bottom surface of the high resistance layer and the top surface of the n + -type semiconductor layer is preferably 1.0 μm or less, more preferably 0.5 μm or less. Further, in the embodiment of the present invention, the bottom surface of the high resistance layer is at the same height as the interface between the n+ type semiconductor layer and the n− type semiconductor layer, or the n+ type semiconductor layer and the n− type semiconductor layer have the same height. It may be positioned below the interface of the mold semiconductor layer. By adopting such a preferable configuration, the semiconductor device in which leakage current is further reduced can be realized. Further, as described above, the bottom surface of the high resistance layer is at the same height as the interface between the n + type semiconductor layer and the n − type semiconductor layer or lower than the interface between the n + type semiconductor layer and the n − type semiconductor layer. The semiconductor device can be further miniaturized by arranging it so as to be located on the side. Further, in the embodiment of the present invention, the high resistance layer has a first region l located inside the semiconductor layer and a second region located outside the semiconductor device, It is also preferable that the distance between the bottom surface of the region and the top surface of the n + -type semiconductor layer is less than 1.5 μm, and that the bottom surface of the second region is located above the bottom surface of the first region.

The n+ type semiconductor layer and the n− type semiconductor layer (hereinafter also simply referred to as “semiconductor layer” or “semiconductor film”) may be formed using known means. Examples of means for forming the semiconductor layer include CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulse growth, and ALD. In an embodiment of the present invention, the means for forming the semiconductor layer is preferably MOCVD, mist CVD, mist epitaxy or HVPE, preferably mist CVD or mist epitaxy. In the mist CVD method or mist epitaxy method, for example, the mist CVD apparatus shown in FIG. A semiconductor film containing a crystalline oxide semiconductor as a main component is formed on a substrate by transporting droplets onto a substrate with a carrier gas (transporting step) and then thermally reacting the atomized droplets in the vicinity of the substrate. (film formation step) to form the semiconductor layer.

(Atomization process)
The atomization step atomizes the raw material solution. The means for atomizing the raw material solution is not particularly limited as long as it can atomize the raw material solution, and may be any known means. In the embodiment of the present invention, atomizing means using ultrasonic waves is preferable. . Atomized droplets obtained using ultrasonic waves have an initial velocity of zero and are preferable because they float in the air. Since it is a possible mist, there is no damage due to collision energy, so it is very suitable. The droplet size is not particularly limited, and may be droplets of several millimeters, preferably 50 μm or less, more preferably 100 nm to 10 μm.

(raw material solution)
The raw material solution is not particularly limited as long as it contains a raw material capable of being atomized or dropletized and capable of forming a semiconductor film, and may be an inorganic material or an organic material. In an embodiment of the present invention, the raw material is preferably a metal or a metal compound, and one or two selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt and iridium. More preferably, it contains more than one species of metal.

In an embodiment of the present invention, as the raw material solution, a solution obtained by dissolving or dispersing the metal in the form of a complex or salt in an organic solvent or water can be preferably used. Examples of forms of the complex include acetylacetonate complexes, carbonyl complexes, ammine complexes, hydride complexes, and the like. Examples of the salt form include organic metal salts (e.g., metal acetates, metal oxalates, metal citrates, etc.), metal sulfide salts, metal nitrate salts, metal phosphate salts, metal halide salts (e.g., metal chlorides, salts, metal bromides, metal iodides, etc.).

Moreover, it is preferable to mix additives such as hydrohalic acid and an oxidizing agent into the raw material solution. Examples of the hydrohalic acid include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Among them, hydrobromic acid or Hydroiodic acid is preferred. Examples of the oxidizing agent include hydrogen peroxide (H ₂ O ₂ ), sodium peroxide (Na ₂ O ₂ ), barium peroxide (BaO ₂ ), benzoyl peroxide (C ₆ H ₅ CO) ₂ O ₂ and the like. , hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, and organic peroxides such as peracetic acid and nitrobenzene.

The raw material solution may contain a dopant. By including the dopant in the raw material solution, the doping can be performed well. The dopant is not particularly limited as long as it does not interfere with the object of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium or niobium, or Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba , Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N or P, and the like. The content of the dopant is appropriately set by using a calibration curve showing the relationship between the concentration of the dopant in the raw material and the desired carrier density.

The solvent of the raw material solution is not particularly limited, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In an embodiment of the present invention, the solvent preferably contains water, more preferably water or a mixed solvent of water and alcohol.

(Conveyance process)
In the transporting step, the atomized liquid droplets are transported into the film forming chamber using a carrier gas. The carrier gas is not particularly limited as long as it does not interfere with the object of the present invention. Suitable examples include oxygen, ozone, inert gases such as nitrogen and argon, and reducing gases such as hydrogen gas and forming gas. mentioned. In addition, although one type of carrier gas may be used, two or more types may be used, and a diluted gas with a reduced flow rate (for example, a 10-fold diluted gas, etc.) may be further used as a second carrier gas. good too. In addition, the carrier gas may be supplied at two or more locations instead of at one location. Although the flow rate of the carrier gas is not particularly limited, it is preferably 0.01 to 20 L/min, more preferably 1 to 10 L/min. In the case of diluent gas, the flow rate of diluent gas is preferably 0.001 to 2 L/min, more preferably 0.1 to 1 L/min.

(Film formation process)
In the film forming step, the semiconductor film is formed on the substrate by thermally reacting the atomized droplets in the vicinity of the substrate. The thermal reaction is not particularly limited as long as the atomized droplets react with heat, and the reaction conditions and the like are not particularly limited as long as they do not interfere with the object of the present invention. In this step, the thermal reaction is usually carried out at a temperature equal to or higher than the evaporation temperature of the solvent, preferably at a temperature that is not too high (for example, 1000° C.), more preferably 650° C. or less, most preferably from 300° C. to 650° C. preferable. In addition, the thermal reaction is carried out under vacuum, under a non-oxygen atmosphere (for example, under an inert gas atmosphere, etc.), under a reducing gas atmosphere, or under an oxygen atmosphere, as long as the object of the present invention is not hindered. However, it is preferably carried out under an inert gas atmosphere or an oxygen atmosphere. The reaction may be carried out under atmospheric pressure, increased pressure or reduced pressure, but is preferably carried out under atmospheric pressure in the embodiment of the present invention. Note that the film thickness can be set by adjusting the film formation time.

(substrate)
The substrate is not particularly limited as long as it can support the semiconductor film. The material of the substrate is also not particularly limited as long as it does not interfere with the object of the present invention, and may be a known substrate, an organic compound, or an inorganic compound. The shape of the substrate may be any shape, and is effective for all shapes. Cylindrical, helical, spherical, ring-shaped, etc. are mentioned, but in the embodiment of the present invention, the substrate is preferable. The thickness of the substrate is not particularly limited in embodiments of the present invention.

The substrate is not particularly limited as long as it has a plate shape and serves as a support for the semiconductor film. The substrate may be an insulator substrate, a semiconductor substrate, a metal substrate, or a conductive substrate. A substrate with a membrane is also preferred. As the substrate, for example, a base substrate containing a substrate material having a corundum structure as a main component, or a base substrate containing a substrate material having a β-gallia structure as a main component, a substrate material having a hexagonal crystal structure as a main component. A base substrate etc. are mentioned. Here, the “main component” means that the substrate material having the specific crystal structure accounts for preferably 50% or more, more preferably 70% or more, and even more preferably 90%, in atomic ratio, of all components of the substrate material. % or more, and may be 100%.

The substrate material is not particularly limited as long as it does not interfere with the object of the present invention, and may be any known material. The substrate material having the corundum structure, for example, α-Al ₂ O ₃ (sapphire substrate) or α-Ga ₂ O ₃ are preferably mentioned, a-plane sapphire substrate, m-plane sapphire substrate, r-plane sapphire substrate , a c-plane sapphire substrate, an α-type gallium oxide substrate (a-plane, m-plane, or r-plane) and the like are more preferable examples. The base substrate mainly composed of a substrate material having a β-Gallia structure is, for example, a β-Ga ₂ O ₃ substrate, or a substrate containing Ga ₂ O ₃ and Al ₂ O ₃ with more than 0 wt % of Al ₂ O ₃ and A mixed crystal substrate having a content of 60 wt % or less may be used. Examples of base substrates mainly composed of a substrate material having a hexagonal crystal structure include SiC substrates, ZnO substrates, and GaN substrates.

In an embodiment of the present invention, annealing may be performed after the film forming process. Annealing treatment temperature is not particularly limited as long as the object of the present invention is not impaired, and is usually 300°C to 650°C, preferably 350°C to 550°C. The annealing treatment time is usually 1 minute to 48 hours, preferably 10 minutes to 24 hours, more preferably 30 minutes to 12 hours. The annealing treatment may be performed under any atmosphere as long as the object of the present invention is not hindered. A non-oxygen atmosphere or an oxygen atmosphere may be used. The non-oxygen atmosphere includes, for example, an inert gas atmosphere (e.g., nitrogen atmosphere), a reducing gas atmosphere, etc. In the embodiment of the present invention, an inert gas atmosphere is preferable, and a nitrogen atmosphere Lower is more preferred.

Further, in the embodiment of the present invention, the semiconductor film may be directly provided on the substrate, or other layers such as a stress relaxation layer (for example, a buffer layer, an ELO layer, etc.), a peeling sacrificial layer, etc. may be formed on the substrate. The semiconductor film may be provided via the semiconductor film. The means for forming each layer is not particularly limited, and known means may be used. In the embodiment of the present invention, the mist CVD method is preferred.

In the embodiment of the present invention, the semiconductor film may be used as the semiconductor layer in the semiconductor device after using known means such as peeling from the substrate or the like, or may be used as the semiconductor layer in the semiconductor device as it is. may be used.

The Schottky electrode is not particularly limited as long as it can form a Schottky junction with the n-type semiconductor layer. The constituent material of the Schottky electrode may be a conductive inorganic material or a conductive organic material. In an embodiment of the present invention, the constituent material of the Schottky electrode is preferably metal. The metal preferably includes, for example, at least one metal selected from Groups 4 to 10 of the periodic table. Examples of metals belonging to Group 4 of the periodic table include titanium (Ti), zirconium (Zr), hafnium (Hf), and the like. Examples of metals of Group 5 of the periodic table include vanadium (V), niobium (Nb), and tantalum (Ta). Group 6 metals of the periodic table include, for example, chromium (Cr), molybdenum (Mo), and tungsten (W). Metals of Group 7 of the periodic table include, for example, manganese (Mn), technetium (Tc), and rhenium (Re). Metals of Group 8 of the periodic table include, for example, iron (Fe), ruthenium (Ru), and osmium (Os). Examples of metals of Group 9 of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals of Group 10 of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt). The thickness of the Schottky electrode is not particularly limited, but is preferably 0.1 nm to 10 μm, more preferably 5 nm to 500 nm, and most preferably 10 nm to 200 nm. In an embodiment of the present invention, the Schottky electrode comprises a first electrode layer provided on the n-type semiconductor layer and a second electrode layer provided on the first electrode layer. and may include In addition, in the embodiment of the present invention, it is preferable that the layer thickness of the first electrode layer is thinner than the layer thickness of the second electrode layer. Moreover, in the aspect of this invention, it is preferable that the work function of the said 1st electrode layer is larger than the work function of the said 2nd electrode layer. By making the first electrode layer have such a preferable structure, not only can a semiconductor device having better Schottky characteristics be obtained, but also the effect of improving the reverse breakdown voltage can be exhibited more satisfactorily. Further, in the embodiment of the present invention, the Schottky electrode may be a single layer, or may be composed of two or more metal layers.

A method for forming the Schottky electrode is not particularly limited, and may be a known method. Specific examples of means for forming the Schottky electrode include a dry method and a wet method. Dry methods include, for example, sputtering, vacuum deposition, and CVD. Wet methods include, for example, screen printing and die coating.

In an aspect of the present invention, the semiconductor device further includes an insulator layer formed on the n-type semiconductor layer, and an end portion of the Schottky electrode is positioned on the insulator layer. It is also preferable to have The constituent material of the insulator layer is not particularly limited as long as it does not interfere with the object of the present invention, and may be a known material. Examples of the insulator layer include a SiO ₂ film, a phosphorus-added SiO ₂ film (PSG film), a boron-added SiO ₂ film, a phosphorus-boron-added SiO ₂ film (BPSG film), and the like. Examples of means for forming the insulating layer include CVD, atmospheric pressure CVD, plasma CVD, mist CVD, and the like. In an embodiment of the present invention, the means for forming the insulating layer is preferably mist CVD or atmospheric pressure CVD. In an embodiment of the present invention, as shown in FIG. 17, the semiconductor device is provided with a passivation film covering the outer end portion of the Schottky electrode and at least a portion of the surface of the n-type semiconductor layer. It is also preferable to have With such a preferable configuration, leakage current of the semiconductor device can be suppressed more satisfactorily. The constituent material and formation means of the passivation film may be the same as those of the insulator layer.

The semiconductor device of the present invention is useful for various semiconductor elements, especially for power devices. In addition, the semiconductor element includes a horizontal element (horizontal device) in which an electrode is formed on one side of the semiconductor layer and current flows in the film thickness direction of the semiconductor layer and the in-plane direction of the film plane, and It can be classified into vertical devices (vertical devices), each of which has an electrode and in which a current flows in the film thickness direction of the semiconductor layer. Although it can be suitably used for devices, it is preferably used for vertical devices. Examples of the semiconductor element include Schottky barrier diodes (SBD), junction barrier Schottky diodes (JBS), metal semiconductor field effect transistors (MESFET), metal insulating film semiconductor field effect transistors (MISFET), and metal oxide semiconductor field effect transistors. A transistor (MOSFET), a high electron mobility transistor (HEMT), or a light emitting diode may be used. In an embodiment of the present invention, the semiconductor device is preferably a diode, more preferably a Schottky barrier diode (SBD).

Preferred examples of the semiconductor device will be described below with reference to the drawings, but the present invention is not limited to these embodiments. In the semiconductor devices exemplified below, other layers (for example, an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers, etc.), etc., as long as the object of the present invention is not hindered. It may be included, or a buffer layer (buffer layer) and the like may be omitted as appropriate.

FIG. 1 shows the main parts of a Schottky barrier diode (SBD), which is one of the preferred embodiments of the present invention. The SBD of FIG. 1 includes an ohmic electrode 102, an n+ type semiconductor layer 101b, an n− type semiconductor layer 101a, a high resistance layer 106, and a Schottky electrode 103. FIG.
In the semiconductor device of FIG. 1, the distance d between the bottom surface of the high resistance layer 106 and the top surface of the n+ type semiconductor layer 101b is less than 1.5 μm. With such a configuration, it is possible to satisfactorily reduce the leakage current of the semiconductor device. Further, in the embodiment of the present invention, at least part of the side surface of the high resistance layer 106 has a tapered shape in which the thickness decreases from the Schottky electrode 103 side toward the ohmic electrode 102 side. is also preferred. By adopting such a preferable structure, electric field concentration on the surface can be alleviated more satisfactorily. Further, examples of the constituent material of the Schottky electrode and/or the ohmic electrode include the metals exemplified above as the constituent material of the Schottky electrode. The means for forming each layer in FIG. 1 is not particularly limited as long as the object of the present invention is not hindered, and known means may be used. For example, after forming a film by a vacuum vapor deposition method, a CVD method, a sputtering method, or various coating techniques, a means for patterning by a photolithographic method, or a means for directly patterning using a printing technique or the like can be used.

A simulation simulating the semiconductor device shown in FIG. 1 was performed in order to confirm the effect of the embodiment of the present invention. A simulation was performed on the assumption that α-Ga ₂ O ₃ was used as the n + -type semiconductor layer and the n− -type semiconductor layer, and SiO ₂ was used as the high resistance layer. Potential distribution simulation results when the distance d between the bottom surface of the high resistance layer and the top surface of the n+ type semiconductor layer is 1.5 μm, 1.0 μm, 0.5 μm, and 0 μm (reverse voltage: 600 V) ( Equipotential lines are indicated by red lines, with an interval of 60 V) are shown in FIG. FIG. 7 shows simulation results of current densities when the distance d between the bottom surface of the high resistance layer and the top surface of the n+ type semiconductor layer is 1.5 μm, 1.0 μm, 0.5 μm and 0 μm. As is clear from FIGS. 6 and 7, when the distance d is less than 1.5 μm, the current density at the end of the Schottky electrode and the high resistance layer is significantly reduced. Further, it can be seen that when the distance d is 1.0 or less and when it is 0.5 or less, a more excellent leakage current reduction effect can be obtained.

When gallium oxide is used as the n-type semiconductor layer and when SiC or GaN is used as the n-type semiconductor layer, the interface between the side surface of the high resistance layer and the side surface of the n-type semiconductor layer Table 1 shows the results of calculation and comparison of defect currents caused by defects. Assuming that the current generated by defects in the side depletion layer is proportional to the intrinsic carrier density, the bandgap of each material was taken into account and the intrinsic carrier density ratio was obtained. Each numerical value in Table 1 indicates the magnitude of the defect current when the magnitude of the defect current in the case of 4H—SiC is set to 1. As is clear from Table 1, when gallium oxide is used as the n-type semiconductor layer, compared with the case of using SiC or GaN as the n-type semiconductor layer, the side surface of the high resistance layer It has been found that the defect current caused by the defect at the interface with the side surface of the n-type semiconductor layer is greatly reduced. That is, it can be seen that the structure in which the high-resistance layer is embedded in the n-type semiconductor layer as shown in FIG. 1 is particularly suitable for semiconductor devices using gallium oxide. In addition, compared to the case of using β-Ga ₂ O ₃ as the n-type semiconductor layer, when α-Ga ₂ O ₃ is used, the leak current caused by the defect at the interface is reduced. It has been found to be even more reduced.

※４Ｈ－ＳｉＣの場合の欠陥電流の大きさを１とした場合の欠陥電流の大きさを示す。

* Indicates the magnitude of the defect current when the magnitude of the defect current in the case of 4H-SiC is set to 1.

The present invention will now be described in more detail using a preferred example of manufacturing the semiconductor device of FIG.

FIG. 2(a) shows a stacked body in which an n+ type semiconductor layer 101b and an n− type semiconductor layer 101a are formed in this order on an ohmic electrode 102, and a trench is formed in the n− type semiconductor layer 101a. is shown. The trench is formed using a known etching method or the like. Here, when forming the trench, the trench is formed so that the distance between the bottom surface of the trench and the top surface of the n + -type semiconductor layer 101b is less than 1.5 μm. Next, a high resistance layer 106 is formed on the laminate shown in FIG. 2(a) to obtain the laminate shown in FIG. 2(b). Here, after forming the high resistance layer 106, the surface of the n-type semiconductor layer and/or the high resistance layer 106 may be polished using CMP or the like. Examples of the method for forming the high resistance layer 106 include sputtering, vacuum deposition, coating, CVD, atmospheric pressure CVD, plasma CVD, and mist CVD. Next, a Schottky electrode 103 is formed on the laminate shown in FIG. 2(b) by using the dry method or the wet method and photolithography to obtain the laminate shown in FIG. 2(c). In the semiconductor device obtained as described above, the distance between the bottom surface of the high resistance layer 106 and the top surface of the n− type semiconductor layer 101b is less than 1.5 μm. With such a configuration, it is possible to satisfactorily reduce the leakage current of the semiconductor device.

FIG. 3 shows the principal parts of a Schottky barrier diode (SBD), which is one of the other preferred embodiments of the present invention. The SBD of FIG. 3 further has an insulator layer 104, and differs from the SBD of FIG. With such a configuration, the withstand voltage characteristic of the semiconductor device can be made more excellent. The means for forming each layer in FIG. 3 is not particularly limited as long as the object of the present invention is not hindered, and known means may be used. For example, after forming a film by a vacuum vapor deposition method, a CVD method, a sputtering method, or various coating techniques, a means for patterning by a photolithographic method, or a means for directly patterning using a printing technique or the like can be used.

FIG. 4 shows the principal parts of a Schottky barrier diode (SBD), which is one of the other preferred embodiments of the present invention. In the SBD of FIG. 4, the high resistance layer 106 has a first region 106a located inside the semiconductor device and a second region 106b located outside the semiconductor device. The distance between the bottom surface of 106a and the n + -type semiconductor layer 101b is less than 1.5 μm (the same distance is drawn as zero in FIG. 4), and the bottom surface of the second region 106b is the second It is different from the SBD in FIG. 1 in that it is located above the bottom surface of the region 1 . The means for forming each layer in FIG. 4 is not particularly limited as long as the object of the present invention is not hindered, and known means may be used. For example, after forming a film by a vacuum vapor deposition method, a CVD method, a sputtering method, or various coating techniques, a means for patterning by a photolithographic method, or a means for directly patterning using a printing technique or the like can be used.

FIG. 12 shows the principal parts of a Schottky barrier diode (SBD), which is one of the other preferred embodiments of the present invention. The SBD of FIG. 12 differs from the SBD of FIG. 1 in that a high resistance layer 107 is formed between the high resistance layer 106 and the n− type semiconductor layer 101a. In the SBD of FIG. 12, for example, a high resistance layer obtained by doping an oxide semiconductor with impurities is used as the high resistance layer 106 . This oxide semiconductor is an epitaxial film formed based on the crystal structure of the n− layer semiconductor of 101a. With such a configuration, defects that tend to occur at the interface between the high-resistance layer and the n− semiconductor layer can be reduced, and the breakdown voltage of the semiconductor device can be further increased. The means for forming each layer other than the 107 layer in FIG. 12 is not particularly limited as long as it does not interfere with the object of the present invention, and may be known means. For example, after forming a film by a vacuum vapor deposition method, a CVD method, a sputtering method, or various coating techniques, a means for patterning by a photolithographic method, or a means for directly patterning using a printing technique or the like can be used. Also, FIG. 17 shows the main part of a Schottky barrier diode (SBD), which is one of the other preferred embodiments of the present invention. The SBD of FIG. 17 differs from the SBD of FIG. 1 in that a passivation film 108 covering at least part of the surface of the n− type semiconductor layer 101a and the outer edge of the Schottky electrode 103 is provided. By adopting such a preferable configuration, it is possible to further reduce leakage current when a reverse voltage is applied. In the embodiment of the present invention, the passivation film 108 preferably covers at least a portion of the high resistance layer 106 in plan view, and preferably covers the outer edge of the high resistance layer 106. more preferred. Further, in the embodiment of the present invention, it is more preferable that the passivation film 108 covers the surface of the semiconductor layer 101a up to the outer edge in plan view.

The semiconductor device is particularly useful for power devices. Examples of the semiconductor device include diodes (eg, PN diodes, Schottky barrier diodes, junction barrier Schottky diodes, etc.) and transistors (eg, MOSFETs, MESFETs, etc.).

The semiconductor device according to the embodiment of the present invention described above can be applied to power converters such as inverters and converters so as to exhibit the functions described above. More specifically, it can be applied as diodes built into inverters and converters, switching elements such as thyristors, power transistors, IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), and the like. can. FIG. 8 is a block diagram showing an example of a control system using a semiconductor device according to an embodiment of the present invention, and FIG. 9 is a circuit diagram of the same control system, which is particularly suitable for mounting on an electric vehicle. control system.

As shown in FIG. 8, the control system 500 has a battery (power source) 501, a boost converter 502, a step-down converter 503, an inverter 504, a motor (to be driven) 505, and a drive control section 506, which are mounted on an electric vehicle. It becomes The battery 501 is composed of a storage battery such as a nickel-metal hydride battery or a lithium-ion battery, and stores electric power by charging at a power supply station or regenerative energy during deceleration, and is necessary for the operation of the running system and electrical system of the electric vehicle. DC voltage can be output. The boost converter 502 is, for example, a voltage conversion device equipped with a chopper circuit, and boosts the DC voltage of, for example, 200 V supplied from the battery 501 to, for example, 650 V by the switching operation of the chopper circuit, and outputs it to a running system such as a motor. be able to. The step-down converter 503 is also a voltage converter equipped with a chopper circuit. It can be output to the electrical system including

Inverter 504 converts the DC voltage supplied from boost converter 502 into a three-phase AC voltage by switching operation, and outputs the three-phase AC voltage to motor 505 . A motor 505 is a three-phase AC motor that constitutes the driving system of the electric vehicle, and is rotationally driven by the three-phase AC voltage output from the inverter 504. The rotational driving force is transmitted to the wheels of the electric vehicle via a transmission or the like (not shown). to

On the other hand, various sensors (not shown) are used to measure actual values such as the number of revolutions and torque of the wheels and the amount of depression of the accelerator pedal (acceleration amount) from the running electric vehicle. is entered. At the same time, the output voltage value of inverter 504 is also input to drive control section 506 . The drive control unit 506 has the function of a controller including an operation unit such as a CPU (Central Processing Unit) and a data storage unit such as a memory. By outputting it as a feedback signal, the switching operation of the switching element is controlled. As a result, the AC voltage applied to the motor 505 by the inverter 504 is corrected instantaneously, so that the operation control of the electric vehicle can be accurately executed, and safe and comfortable operation of the electric vehicle is realized. It is also possible to control the output voltage to the inverter 504 by giving the feedback signal from the drive control unit 506 to the boost converter 502 .

FIG. 9 shows a circuit configuration excluding the step-down converter 503 in FIG. As shown in the figure, the semiconductor device of the present invention is employed as a Schottky barrier diode in a boost converter 502 and an inverter 504 for switching control. Boost converter 502 is incorporated in a chopper circuit to perform chopper control, and inverter 504 is incorporated in a switching circuit including IGBTs to perform switching control. An inductor (such as a coil) is interposed in the output of the battery 501 to stabilize the current. It is stabilizing the voltage.

Further, as indicated by a dotted line in FIG. 9, the drive control unit 506 is provided with an operation unit 507 made up of a CPU (Central Processing Unit) and a storage unit 508 made up of a non-volatile memory. A signal input to the drive control unit 506 is supplied to the calculation unit 507, and a feedback signal for each semiconductor element is generated by performing necessary calculations. Further, the storage unit 508 temporarily holds the calculation result by the calculation unit 507, accumulates physical constants and functions required for drive control in the form of a table, and outputs them to the calculation unit 507 as appropriate. The calculation unit 507 and the storage unit 508 can employ known configurations, and their processing capabilities can be arbitrarily selected.

As shown in FIGS. 8 and 9, in the control system 500, the switching operations of the boost converter 502, the step-down converter 503, and the inverter 504 use diodes and switching elements such as thyristors, power transistors, IGBTs, MOSFETs, and the like. . By using gallium oxide (Ga ₂ O ₃ ), especially corundum-type gallium oxide (α-Ga ₂ O ₃ ), as the material for these semiconductor elements, the switching characteristics are greatly improved. Furthermore, by applying the semiconductor device or the like according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be realized. That is, each of the boost converter 502, the step-down converter 503, and the inverter 504 can expect the effects of the present invention. The effect of the present invention can be expected in any of the above.
Note that the control system 500 described above can apply the semiconductor device of the present invention not only to the control system of an electric vehicle, but also to a control system for various purposes such as stepping up or stepping down power from a DC power supply or converting power from DC to AC. can be applied to It is also possible to use a power source such as a solar cell as the battery.

FIG. 10 is a block configuration diagram showing another example of a control system employing a semiconductor device according to an embodiment of the present invention, and FIG. 11 is a circuit diagram of the same control system, showing infrastructure equipment that operates on power from an AC power supply. This control system is suitable for installation in home appliances, etc.

As shown in FIG. 10, a control system 600 receives power supplied from an external, for example, a three-phase AC power supply (power supply) 601, and includes an AC/DC converter 602, an inverter 604, a motor (to be driven) 605, It has a drive control unit 606, which can be mounted on various devices (described later). The three-phase AC power supply 601 is, for example, a power generation facility of an electric power company (a thermal power plant, a hydroelectric power plant, a geothermal power plant, a nuclear power plant, etc.), and its output is stepped down via a substation and supplied as an AC voltage. be. In addition, for example, in the form of a private power generator or the like, it is installed in a building or in a nearby facility and supplied by a power cable. The AC/DC converter 602 is a voltage conversion device that converts AC voltage into DC voltage, and converts AC voltage of 100V or 200V supplied from the three-phase AC power supply 601 into a predetermined DC voltage. Specifically, the voltage is converted into a generally used desired DC voltage such as 3.3V, 5V, or 12V. When the object to be driven is a motor, conversion to 12V is performed. A single-phase AC power supply may be used instead of the three-phase AC power supply. In that case, the same system configuration can be achieved by using a single-phase input AC/DC converter.

Inverter 604 converts the DC voltage supplied from AC/DC converter 602 into a three-phase AC voltage by switching operation, and outputs the three-phase AC voltage to motor 605 . The form of the motor 604 differs depending on the object to be controlled. When the object to be controlled is a train, the motor 604 drives the wheels. It is a three-phase AC motor, and is rotationally driven by a three-phase AC voltage output from an inverter 604, and transmits its rotational driving force to a drive target (not shown).

For example, in home appliances, there are many objects to be driven that can be directly supplied with the DC voltage output from the AC/DC converter 602 (for example, personal computers, LED lighting equipment, video equipment, audio equipment, etc.). The control system 600 does not require the inverter 604, and as shown in FIG. 10, a DC voltage is supplied from the AC/DC converter 602 to the driven object. In this case, for example, a personal computer is supplied with a DC voltage of 3.3V, and an LED lighting device is supplied with a DC voltage of 5V.

On the other hand, various sensors (not shown) are used to measure actual values such as the rotational speed and torque of the driven object, or the temperature and flow rate of the surrounding environment of the driven object, and these measurement signals are input to the drive control unit 606. At the same time, the output voltage value of inverter 604 is also input to drive control section 606 . Based on these measurement signals, drive control section 606 gives a feedback signal to inverter 604 to control the switching operation of the switching element. As a result, the AC voltage applied to the motor 605 by the inverter 604 is corrected instantaneously, so that the operation control of the object to be driven can be accurately executed, and the object to be driven can be operated stably. Further, as described above, when the object to be driven can be driven with a DC voltage, it is possible to feedback-control the AC/DC converter 602 instead of the feedback to the inverter.

FIG. 11 shows the circuit configuration of FIG. As shown in the figure, the semiconductor device of the present invention is employed as a Schottky barrier diode in an AC/DC converter 602 and an inverter 604 for switching control. The AC/DC converter 602 uses, for example, a Schottky barrier diode circuit configured in a bridge shape, and performs DC conversion by converting and rectifying the negative voltage component of the input voltage into a positive voltage. Also, the inverter 604 is incorporated in the switching circuit in the IGBT to perform switching control. A capacitor (such as an electrolytic capacitor) is interposed between the AC/DC converter 602 and the inverter 604 to stabilize the voltage.

Further, as indicated by the dotted line in FIG. 11, the drive control unit 606 is provided with an operation unit 607 made up of a CPU and a storage unit 608 made up of a non-volatile memory. A signal input to the drive control unit 606 is supplied to the calculation unit 607, and a feedback signal for each semiconductor element is generated by performing necessary calculations. The storage unit 608 also temporarily stores the results of calculations by the calculation unit 607, accumulates physical constants and functions necessary for drive control in the form of a table, and outputs them to the calculation unit 607 as appropriate. The calculation unit 607 and the storage unit 608 can employ known configurations, and their processing capabilities can be arbitrarily selected.

In such a control system 600, like the control system 500 shown in FIGS. 8 and 9, the rectifying operation and switching operation of the AC/DC converter 602 and the inverter 604 are performed by diodes, switching elements such as thyristors and power transistors. , IGBT, MOSFET, etc. are used. Switching characteristics are improved by using gallium oxide (Ga ₂ O ₃ ), particularly corundum type gallium oxide (α-Ga ₂ O ₃ ), as the material for these semiconductor elements. Furthermore, by applying the semiconductor film and the semiconductor device according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be realized. That is, the AC/DC converter 602 and the inverter 604 can each be expected to have the effect of the present invention. can be expected.

10 and 11 illustrate the motor 605 as an object to be driven, the object to be driven is not necessarily limited to mechanically operating devices, and can be many devices that require AC voltage. In the control system 600, as long as the drive object is driven by inputting power from an AC power supply, it can be applied to infrastructure equipment (for example, power equipment such as buildings and factories, communication equipment, traffic control equipment, water and sewage treatment Equipment, system equipment, labor-saving equipment, trains, etc.) and home appliances (e.g., refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.). can.

(Example 1)
A Schottky barrier diode (SBD) having a structure similar to that shown in FIG. 1 was manufactured according to the manufacturing method described above, and IV measurement was performed. The distance between the bottom surface of the high resistance layer and the top surface of the n + -type semiconductor layer was set to 1.3 μm. FIG. 13 shows the result of observing the cross section of the obtained semiconductor device. As a result of IV measurement, the withstand voltage of the obtained semiconductor device was 850V. It has been found that, according to the embodiments of the present invention, a semiconductor device with a high withstand voltage can be obtained because the leak current is reduced. FIG. 15 shows the result of the IV measurement.

(Comparative example 1)
An SBD was fabricated in the same manner as in Example 1, except that the distance between the bottom surface of the high resistance layer and the top surface of the n + -type semiconductor layer was set to 1.9 μm. FIG. 14 shows the result of observing the cross section of the obtained semiconductor device. As a result of IV measurement, the withstand voltage of the obtained semiconductor device was 385V. FIG. 15 shows the result of the IV measurement.

(Example 2)
A semiconductor device was fabricated in the same manner as in Example 1, except that the high resistance layer was formed such that the distance between the bottom surface of the high resistance layer and the top surface of the n+ type semiconductor layer was 1.0 μm or less. IV measurement was performed in the same manner as in Example 1 for the obtained semiconductor device. Results of IV measurements are shown in FIG. As is clear from FIG. 16, it was found that the leak current was further reduced as compared with Example 1.

(Example 3)
As shown in FIG. 17, a semiconductor device was fabricated according to Example 1, except that a passivation film was formed in addition to the high resistance layer. For comparison, a sample in which only the high resistance layer was formed was also produced. FIG. 18A shows the result of IV measurement with the passivation film, and FIG. 18B shows the result of IV measurement without the passivation film (only the high resistance layer). As is clear from FIG. 18, the leakage current can be further reduced by using the passivation film in combination with the high resistance layer.

The semiconductor device of the present invention can be used in various fields such as semiconductors (for example, compound semiconductor electronic devices), electronic parts/electrical equipment parts, optical/electrophotographic equipment, industrial materials, etc., but it is particularly useful for power devices. be.

1 Film deposition equipment (mist CVD equipment)
2a Carrier gas source 2b Carrier gas (dilution) source 3a Flow control valve 3b Flow control valve 4 Mist generation source 4a Raw material solution 4b Raw fine particles 5 Container 5a Water 6 Ultrasonic oscillator 7 Film forming chamber 8 Hot plate 9 Supply pipe 10 Substrate 101 semiconductor layer 101a n− type semiconductor layer 101b n+ type semiconductor layer 102 ohmic electrode 103 Schottky electrode 104 insulator layer 106 high resistance layer 106a first region 106b second region 107 high resistance layer 108 passivation film 500 control system 501 battery (power supply)
502 Boost converter 503 Buck converter 504 Inverter 505 Motor (driven object)
506 drive control unit 507 calculation unit 508 storage unit 600 control system 601 three-phase AC power supply (power supply) s
602 AC/DC converter 604 Inverter 605 Motor (to be driven)
606 drive control unit 607 calculation unit 608 storage unit

Claims (14)

an n + type semiconductor layer, an n − type semiconductor layer disposed on the n + type semiconductor layer, a high resistance layer at least partially embedded in the n − type semiconductor layer, and the n − type semiconductor layer A semiconductor device comprising at least a Schottky electrode forming a Schottky junction,
The n+ type semiconductor layer and the n− type semiconductor layer each contain a crystalline oxide semiconductor as a main component, and the distance between the bottom surface of the high resistance layer and the top surface of the n+ type semiconductor layer is less than 1.5 μm. 1. A semiconductor device according to claim 1, wherein an end portion of said Schottky electrode is located on said high resistance layer. 2. The semiconductor device according to claim 1, wherein said crystalline oxide semiconductor contains one or more metals selected from aluminum, indium and gallium. 3. The semiconductor device according to claim 1, wherein said crystalline oxide semiconductor contains at least gallium. 4. The semiconductor device according to claim 1, wherein said crystalline oxide semiconductor has a corundum structure or a β-gallia structure. 5. The semiconductor device according to claim 1, wherein the distance between the bottom surface of said high resistance layer and the top surface of said n+ type semiconductor layer is 1.0 μm or less. The bottom surface of the high resistance layer is at the same height as the interface between the n+ type semiconductor layer and the n− type semiconductor layer, or is lower than the interface between the n+ type semiconductor layer and the n− type semiconductor layer. 6. The semiconductor device according to any one of claims 1 to 5, located at . 7. The semiconductor device according to claim 1, wherein said high resistance layer contains SiO ₂ . 8. The semiconductor device according to any one of claims 1 to 7, further comprising an insulator layer formed on said n-type semiconductor layer, wherein an end portion of said Schottky electrode is located on said insulator layer. semiconductor device. The high resistance layer has a first region located inside the semiconductor device and a second region located outside the semiconductor device, and the bottom surface of the first region and the n + type semiconductor layer are separated from each other. 9. The semiconductor device according to claim 1, wherein the distance from the top surface is less than 1.5 μm, and the bottom surface of said second region is located above the bottom surface of said first region. 11. The semiconductor device according to claim 1, further comprising a passivation film covering an outer edge of said Schottky electrode and at least a portion of said n- semiconductor layer surface. 11. The semiconductor device according to claim 1, which is a diode. 12. The semiconductor device according to claim 1, which is a power device. A power converter using the semiconductor device according to any one of claims 1 to 12. A control system using the semiconductor device according to any one of claims 1 to 12.

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