TW202211384A - Memory device - Google Patents

Abstract

A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.

Description

memory device

The present invention relates to memory devices, and in particular to memory devices having conductive pillars surrounded by tubular elements.

Since planar memory devices, such as two-dimensional (2-dimensional) memory devices, have reached the limit of capacity expansion and are difficult to meet market demands, the development of memory devices has shifted to 3-dimensional (3D) memory devices. However, the development of three-dimensional memory devices brings many challenges, such as high cost, difficult integration process, structural stability of memory devices, electrical performance of memory devices, and complex device design. In order to solve these problems, it is more and more important to develop new three-dimensional memory devices.

Therefore, there is a need to provide memory devices with improved layouts.

The present invention relates to memory devices.

According to an embodiment, a memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive column and a plurality of memory cells. The tubular element includes a dummy channel layer, and the tubular element penetrates the stack structure. The conductive pillars are surrounded by the tubular element, and the conductive pillars extend beyond the bottom surface of the dummy channel layer. A plurality of memory cells are in the stacked structure and are electrically connected to the conductive pillars.

In order to have a better understanding of the above and other aspects of the present invention, the following embodiments are given and described in detail in conjunction with the accompanying drawings as follows.

Relevant embodiments are provided below, and the memory device and the manufacturing method thereof provided by the present disclosure are described in detail in conjunction with the drawings. However, the present disclosure is not limited thereto. The descriptions in the embodiments, such as the detailed structure, the steps of the manufacturing method, and the material application, etc., are only for the purpose of illustration, and the scope of protection of the present disclosure is not limited to the above-mentioned aspects.

At the same time, it should be noted that the present disclosure does not show all possible embodiments. Those skilled in the relevant art can make changes and modifications to the structures and manufacturing methods of the embodiments to meet the needs of practical applications without departing from the spirit and scope of the present disclosure. Therefore, other implementation aspects not proposed in the present disclosure may also be applicable. Furthermore, the drawings are simplified for the purpose of clearly explaining the contents of the embodiments, and the dimension ratios in the drawings are not drawn according to the actual product scale. Therefore, the description and the drawings are only used to describe the embodiments, rather than to limit the protection scope of the present disclosure. The same or similar reference numerals are used to represent the same or similar elements.

FIG. 1 is a schematic perspective view of a memory device 10 according to an embodiment of the present invention. The memory device 10 may include three-dimensional non-volatile memory, such as NOR flash memory, NAND flash memory, or other types of memory. The memory device 10 may include a stacked structure S. The stack structure S may include a main stack structure 100 , a stepped structure 101 and an insulating stack structure 102 . The main stack structure 100 , the stepped structure 101 and the insulating stack structure 102 may be disposed adjacent to each other. The main stack structure 100 , the stepped structure 101 and the insulating stack structure 102 may be arranged not to overlap each other in a vertical direction, such as the Z direction. The main stack structure 100 and the stepped structure 101 may be disposed along the lateral direction, such as the Y direction, but the main stack structure 100 and the stepped structure 101 may not overlap each other in the longitudinal direction, such as the X direction. The main stack structure 100 and the insulating stack structure 102 may be disposed along the X direction, but the main stack structure 100 and the insulating stack structure 102 may not overlap each other in the Y direction. Similarly, the stepped structure 101 and the insulating stacked structure 102 may be disposed along the X direction, but the stepped structure 101 and the insulating stacked structure 102 may not overlap each other in the Y direction.

In one embodiment, as shown in FIG. 1, the memory device 10 may have four stepped structures 101/101A/101B/101C, the stepped structures 101 and 101A are disposed adjacent to each other, and the insulating strips 103 make the stepped structures The structure 101 is isolated from the stepped structure 101A. The stepped structure 101B and the stepped structure 101C are disposed adjacent to each other, and the insulating strip 103 isolates the stepped structure 101B from the stepped structure 101C. The stepped structure 101 and the stepped structure 101C are disposed on opposite sides of the main stack structure 100 . The stepped structure 101A and the stepped structure 101B are disposed on opposite sides of the main stack structure 100 . In one embodiment, the stepped structure 101 and the stepped structure 101C may be arranged symmetrically. In one embodiment, the stepped structure 101A and the stepped structure 101B may be arranged symmetrically. In one embodiment, the memory device 10 may have two insulating stack structures 102/102A disposed on opposite sides of the main stack structure 100; the stepped structures 101/101A/101B/101C and the insulating stack structures 102/102A are disposed on the main stack Different sides of structure 100. In one embodiment, the two insulating stack structures 102/102A may be arranged symmetrically.

The insulating strips 103 may extend along the Y direction to isolate the main stack structure 100 from the main stack structure 100A. According to different designs, the memory device 10 may have one or more main stacked structures 100/100A, one or more stepped structures 101/101A/101B/101C, and one or more insulating stacked structures 102/102A. As shown in FIG. 1 , the insulating strips 103 may extend along the Y direction to isolate the stepped structure 101 from the stepped structure 101A, the main stack structure 100 from the main stacked structure 100A, and the stepped structure 101B from the stepped structure 101C. In one embodiment, the insulating strips 103 may include insulating material.

FIG. 2A is a schematic perspective view of the memory device 10 , excluding the portion of the memory device 10 corresponding to the insulating stack structure 102 in FIG. 1 . Referring to FIG. 1 and FIG. 2A at the same time, the main stack structure 100 may include a plurality of conductive films 104 and a plurality of first insulating layers 105 stacked alternately along the Z direction. The plurality of conductive films 104 isolate the plurality of first insulating layers 105 from each other. In one embodiment, the conductive film 104 of the main stack structure 100 may include a conductive material, such as tungsten (W). The first insulating layer 105 of the main stack structure 100 may include an insulating material, and the insulating material includes an oxide, such as silicon oxide.

The stepped structure 101 may include a plurality of conductive stepped layers 106 and a plurality of insulating stepped layers 107 stacked alternately along the Z direction. The plurality of conductive stepped layers 106 isolate the plurality of insulating stepped layers 107 from each other. Each conductive step layer 106 has a different lateral area in the X-Y plane. For example, the lateral area of the conductive stepped layer 106 gradually decreases from the bottom surface 108 of the stepped structure 101 to the top surface 109 of the stepped structure 101 . For example, the lateral area of the conductive stepped layer 106 at the lower level (the level closer to the bottom surface 108 of the stepped structure 101 ) is larger than that of the conductive stepped layer at the higher level (the level farther from the bottom surface 108 of the stepped structure 101 ) Lateral area of layer 106 . In one embodiment, the conductive stepped layer 106 of the stepped structure 101 may include a conductive material, such as tungsten. The insulating stepped layer 107 of the stepped structure 101 may include an insulating material, and the insulating material includes an oxide, such as silicon oxide.

The insulating stack structure 102 may include a plurality of second insulating layers 110 and a plurality of third insulating layers 111 stacked alternately along the Z direction. The plurality of second insulating layers 110 isolate the plurality of third insulating layers 111 from each other. In one embodiment, the second insulating layer 110 of the insulating stack structure 102 may include an insulating material, and the insulating material includes a nitride, such as silicon nitride. The third insulating layer 111 of the insulating stack structure 102 may include an insulating material, and the insulating material includes an oxide, such as silicon oxide. In one embodiment, the second insulating layer 110 and the third insulating layer 111 may include different materials.

In one embodiment, the conductive film 104 of the main stack structure 100 may be electrically connected to the conductive stepped layer 106 of the stepped structure 101 . The insulating stack structure 102 may be electrically insulating. The conductive film 104 of the main stack structure 100 and the conductive stepped layer 106 of the stepped structure 101 can be used as the gate structure of the memory device 10 .

In one embodiment, the plurality of first insulating layers 105 of the main stacked structure 100 , the plurality of insulating stepped layers 107 of the stepped structure 101 and the plurality of third insulating layers 111 of the insulating stacked structure 102 have a one-to-one correspondence, in other words , a first insulating layer 105, an insulating step layer 107 corresponding to the first insulating layer 105, and a third insulating layer 111 corresponding to the first insulating layer 105 may have the same height (or level) in the Z direction .

The memory device 10 may include a plurality of pillar structures 112 that are distributed in the insulating stack structure 102 and the stepped structure 101 . The plurality of pillar structures 112 pass through the insulating stack structure 102 and the stepped structure 101 in the Z direction. Each column structure 112 includes a tubular element 113 and a conductive column 114 . The tubular element 113 penetrates the stacked structure S. Specifically, the conductive post 114 is surrounded by the tubular element 113 . In one embodiment, the column structure 112 may have a structure similar to a coaxial cable. The conductive pillars 114 and the tubular element 113 may extend along the Z direction and pass through the insulating stack structure 102 and the stepped structure 101 . The conductive pillars 114 may include a conductive material, such as tungsten.

In the insulating stack structure 102 , each column structure 112 passes through the same number of the second insulating layers 110 . In the stepped structure 101 , the plurality of pillar structures 112 pass through different numbers of conductive stepped layers 106 respectively. For example, the stepped structure 101 may include a plurality of stepped portions 115 (as shown in FIG. 2A ), the number of conductive stepped layers 106 included in each stepped portion 115 may be different, and the column structures 112 in the stepped structure 101 may be individually are disposed in different stepped portions 115 , specifically, a column structure 112 is disposed in one stepped portion 115 .

The memory device 10 may include a plurality of conductive plugs 116 disposed on the conductive stepped layer 106 of the stepped structure 101 . Specifically, each conductive plug 116 may be disposed on the conductive stepped layers 106 of different levels in the stepped structure 101 . A plurality of conductive plugs 116 may be individually arranged in different stepped portions 115 . The conductive plug 116 is electrically connected to a conductive stepped layer 106 disposed on the conductive plug 116 , and the tubular element 113 and the conductive column 114 pass through the conductive stepped layer 106 .

FIG. 2B shows one of the plurality of pillar structures 112 in the insulating stack structure 102 shown in FIG. 1 . FIG. 2C shows one of the plurality of column structures 112 in the stepped structure 101 shown in FIG. 1 .

Referring to FIGS. 1 and 2B-2C, in the insulating stack structure 102 and the stepped structure 101 , the tubular element 113 may include a memory film 117 , a dummy channel layer 118 and an insulating film 119 . The conductive pillars 114 are surrounded by the tubular element 113 and the conductive pillars 114 extend beyond the bottom surface 120 of the dummy channel layer 118 . In one embodiment, the bottom surface 120 of the dummy channel layer 118 may extend beyond the bottom surface 121 of the insulating stack structure 102 and the bottom surface 108 of the stepped structure 101 along the Z direction, and the conductive pillars 114 may extend beyond the insulating layer along the Z direction. The bottom surface 121 of the stacked structure 102 , the bottom surface 108 of the stepped structure 101 , and the bottom surface 120 of the dummy channel layer 118 .

The memory film 117 may include a multilayer structure known in the memory technology field, such as an ONO (oxide-nitride-oxide) structure, ONONO (oxide-nitride-oxide-nitride-oxide) ) structure, ONONONO (Oxide-Nitride-Oxide-Nitride-Oxide-Nitride-Oxide) structure, SONOS (Silicon-Silicon Oxide-Silicon Nitride-Silicon Oxide-Silicon) structure, BE-SONOS ( Band gap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, TANOS (tantalum nitride-alumina-silicon nitride-silicon oxide-silicon) structure, MA BE-SONOS (metal-high dielectric constant) Material energy band gap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure and its combination. The memory film 117 may have a tubular shape and surround the conductive pillars 114 .

In one embodiment, the memory layer of the memory device 10 may include a memory film 117 and a memory material, and the memory material is formed between the memory film 117 and the conductive film 104 of the main stack structure 100 . The memory layer may comprise any charge trapping structure known in the field of memory technology, such as ONO structure, ONONO structure, ONONONO structure, SONOS structure, BE-SONOS structure, TANOS structure, MA BE-SONOS structure and combinations thereof Wait. The charge trapping structure can use nitrides such as silicon nitride, or other similar high dielectric constant materials including metal oxides, such as aluminum oxide (alumina; Al ₂ O ₃ ), zirconium oxide (hafnium dioxide; HfO ₂ ) Wait. Memory cells can be defined in memory layers. For example, when the memory layer includes a memory film 117 and a memory material, the memory film 117 can be understood as a tunneling oxide layer, and the memory film 117 can include silicon dioxide (SiO ₂ ) or Only silicon dioxide is included; and the memory material may include multi-layer memory materials known in the field of memory technology, such as aluminum oxide, titanium nitride (TiN), ONO structure, ONONO structure, ONONONO structure, SONOS structure , BE-SONOS structure, TANOS structure, MA BE-SONOS structure and combinations thereof, etc.

The dummy channel layer 118 is disposed between the memory film 117 and the conductive pillar 114 . The dummy channel layer 118 may include a semiconductor material, such as a doped semiconductor material or an undoped semiconductor material. In one embodiment, the dummy channel layer 118 may comprise polysilicon, such as doped polysilicon or undoped polysilicon. The dummy channel layer 118 may have a tubular shape and surround the conductive pillars 114 . In one embodiment, the dummy channel layer 118 may refer to the dummy channel layer 118 without a driving circuit. In one embodiment, the dummy channel layer 118 can be understood as an element that is electrically floating.

The insulating film 119 is disposed between the conductive pillar 114 and the dummy channel layer 118 . The insulating film 119 may have a tubular shape and surround the conductive post 114 . The insulating film 119 may include a dielectric material including an oxide (eg, silicon oxide).

FIG. 3 is a schematic top view of the main stack structure 100 according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 3 at the same time, the memory device 10 may include a plurality of column elements 122 , which are distributed in the main stack structure 100 . The pillar elements 122 extend along the Z direction and pass through the main stack structure 100 .

The pillar element 122 may include a memory film 117 , a channel layer 118A, a source/drain pillar 123 , a source/drain pillar 124 , an insulating pillar 125 and an insulating film 119 . The insulating pillar 125 is disposed between the source/drain pillar 123 and the source/drain pillar 124 . The insulating pillars 125 isolate the source/drain pillars 123 from the source/drain pillars 124 from each other. One of the source/drain posts 123 and the source/drain posts 124 is a source, and the other is a drain. The insulating film 119 is disposed between the channel layer 118A and the source/drain pillars 123 , the source/drain pillars 124 and the insulating pillars 125 . The channel layer 118A is provided between the insulating film 119 and the memory film 117 . The channel layer 118A may have a tubular shape and surround the source/drain pillars 123 , the source/drain pillars 124 , the insulating film 119 and the insulating pillars 125 . The memory film 117 may have a tubular shape and surround the channel layer 118A. The memory film 117 of the column element 122 may be similar to the memory film 117 of the tubular element 113 . Source/drain pillars 123 and source/drain pillars 124 may comprise doped semiconductor material, such as N+ polysilicon, or may comprise undoped semiconductor material. The insulating pillars 125 may include insulating materials including nitrides, such as silicon nitride.

The memory device 10 may include a plurality of memory cells disposed in the main stack structure 100 and the main stack structure 100A. The memory cells may be defined in the memory film 117 where the conductive film 104 and the channel layer 118A of the column element 122 intersect. The column element 122 can be understood as an active column element. In one embodiment, the main stack structure 100 may be disposed in an array region, and the stair structure 101 may be disposed in a staircase region.

The dummy channel layer 118 of the tubular element 113 differs from the channel layer 118A of the pillar element 122 in that the dummy channel layer 118 is not used to provide a channel for electrons or holes when a voltage is applied to the memory device 10 .

FIG. 4 is a schematic perspective view of the column element 122A in the main stack structure 100 according to another embodiment of the present invention. The difference between the pillar element 122A shown in FIG. 4 and the pillar element 122 shown in FIG. 3 is described below. The pillar element 122A includes a channel layer 118B, a source/drain pillar 123 , a source/drain pillar 124 and an insulating film 119 . The insulating film 119 isolates the source/drain posts 123 from the source/drain posts 124 . The difference between the channel layer 118B shown in FIG. 4 and the channel layer 118A shown in FIG. 3 is that the channel layer 118B has an open-loop shape, and the channel layer 118B has opposite ends electrically connected to the source/drain, respectively The pole 123 and the source/drain pole 124 . The difference between the memory film 417 shown in FIG. 4 and the memory film 117 shown in FIG. 3 is that the memory film 417 is disposed on the upper surface and the lower surface of the conductive film 104 of the main stack structure 100 and can extend over the column element between the outer sidewall of 122A and the conductive film 104 .

In one embodiment, in the schematic three-dimensional view of the main stack structure 100 , the memory film 117 shown in FIG. 3 can be disposed on the upper surface and the lower surface of the conductive film 104 , and can extend on the outer sidewall and the conductive film of the column element 122 . Between the membranes 104, the arrangement of the memory membrane 417 shown in FIG. 4 is similar.

Referring to FIG. 1 again, the memory device 10 may include a poly semiconductor layer 126 located under the main stack structure 100 , the stepped structure 101 and the insulating stack structure 102 . In other words, the polycrystalline semiconductor layer 126 is located under the memory cells. The tubular element 113 , the conductive pillar 114 and the pillar element 122 pass through the polycrystalline semiconductor layer 126 . The polycrystalline semiconductor layer 126 may comprise a doped semiconductor material, such as P+ polysilicon, or an undoped semiconductor material. The conductive post 114 may have an upper conductive post end portion 127 and a lower conductive post end portion 128 opposite to the upper conductive post end portion 127 . The ends 127 of the conductive pillars on the conductive pillars 114 are located above the insulating stack structure 102 and the stepped structure 101 . The ends 128 of the conductive pillars below the conductive pillars 114 are located below the polycrystalline semiconductor layer 126 .

The memory device 10 may include a transistor 161 , a lower conductive structure 163 and a lower conductive structure 165 . The lower conductive structure 163 is electrically connected between the end portion 128 of the conductive column below the conductive column 114 and one of the drain electrode and the source electrode of the transistor 161 . The lower conductive structure 165 is electrically connected between the end portion 128 of the conductive column below the conductive column 114 and the other of the drain electrode and the source electrode of the transistor 161 .

FIG. 5 is a schematic top view of a memory device 10 according to an embodiment of the present invention. The difference between FIG. 1 and FIG. 5 is that the memory device 10 shown in FIG. 5 includes more main stack structures 100/100A/100B/100C and more stepped structures 101/101A/101B/101C /101D/101E/101F/101G, FIG. 5 does not show the insulating stack structure 102/102A. Please refer to FIG. 1 and FIG. 5 simultaneously, the memory device 10 may include a conductive layer 130 . The conductive layer 130 may be disposed above the main stack structure 100 , the stepped structure 101 and the insulating stack structure 102 . The conductive layer 130 may include an upper conductive structure 171 , an upper conductive structure 173 , an upper conductive structure 181 , an upper conductive structure 183 and an upper conductive structure 191 , and is disposed above the column element 122 and/or the column structure 112 .

The upper conductive structure 173 can be electrically connected to a conductive column 114 of a column structure 112 in the insulating stack structure 102 . The upper conductive structure 171 can be electrically connected to the plurality of conductive pillars 114 of the other plurality of pillar structures 112 in the insulating stack structure 102 . The upper conductive structure 171 is electrically connected between one of the source electrode or the drain electrode of the column element 122 and the conductive column 114 . The upper conductive structure 171 is electrically connected between the memory cells and the upper conductive column ends 127 of the conductive columns 114 in the insulating stack structure 102 . A conductive column 114 of a column structure 112 in the insulating stack structure 102 is electrically connected between the lower conductive structure 165 and the upper conductive structure 173 . The conductive pillars 114 of the other pillar structures 112 in the insulating stack structure 102 are electrically connected between the lower conductive structure 163 and the upper conductive structure 171 .

The upper conductive structure 183 can be electrically connected to a conductive column 114 of a column structure 112 in the insulating stack structure 102A. The upper conductive structure 181 can be electrically connected to the plurality of conductive pillars 114 of the other plurality of pillar structures 112 in the insulating stack structure 102A. The upper conductive structure 181 is electrically connected between the other of the source electrode or the drain electrode of the pillar element 122 (eg, the one electrically connected relative to the upper conductive structure 171 ) and the conductive pillar 114 . The upper conductive structure 181 is electrically connected between the memory cell and the upper conductive column end 127 of the conductive column 114 in the insulating stack structure 102A. A conductive column 114 of a column structure 112 in the insulating stack structure 102A is electrically connected between the lower conductive structure 165 and the upper conductive structure 183 . The conductive pillars 114 of the other pillar structures 112 in the insulating stack structure 102A are electrically connected between the lower conductive structure 163 and the upper conductive structure 181 .

In one embodiment, for example, the source of the column element 122 is electrically connected to the upper conductive structure 171 , the conductive column 114 in the insulating stack structure 102 , the upper conductive structure 173 , the lower conductive structure 163 , the transistor 161 and the lower conductive structure 165 . . The upper conductive structure 171 , the conductive pillars 114 in the insulating stack structure 102 , the upper conductive structure 173 , and a plurality of lower portions of the plurality of conductive pillars 114 (ie, effective conductive pillars or active conductive pillars) electrically connected to the insulating stacked structure 102 . The lower conductive structure 163 and the lower conductive structure 165 between the ends 128 of the conductive pillars can be used as source lines. For example, the upper conductive structure 173 can be used as a global source line or a common source line. Transistor 161 (switch) can be used as a source line transistor (source line switch). The conductive pillars 114 in the insulating stack structure 102 can be used as source line contact structures for the memory cells.

In one embodiment, for example, the drain of the column element 122 is electrically connected to the upper conductive structure 181 , the conductive column 114 in the insulating stack structure 102A, the upper conductive structure 183 , the lower conductive structure 163 , the transistor 161 and the lower conductive structure 165 . . The upper conductive structure 181 , the conductive pillars 114 in the insulating stack structure 102A, the upper conductive structure 183 , and a plurality of lower ones electrically connected to the plurality of conductive pillars 114 (ie, the active conductive pillars or the active conductive pillars) in the insulating stacked structure 102A The lower conductive structure 163 and the lower conductive structure 165 between the ends of the conductive pillars 128 can be used as bit lines. For example, the upper conductive structure 181 can be used as a local bit line, the upper conductive structure 183 can be used as a global bit line or a common bit line, a local bit line The plurality of conductive pillars 114 , the lower conductive structure 163 , the transistor 161 and the lower conductive structure 165 in the insulating stack structure 102A are electrically connected to the global bit line. Transistor 161 (switch) may function as a bitline transistor (bitline switch). The conductive pillars 114 in the insulating stack structure 102A can serve as bit line contact structures for the memory cells.

The upper conductive structure 191 can be electrically connected between the conductive plug 116 and the conductive column end 127 on the conductive column 114 of the column structure 112 in the stepped structure 101 . The semiconductor device 129 may include a transistor 192 and a lower conductive structure 194 . The lower conductive structure 194 is electrically connected to the transistor 192 . The lower conductive structure 194 is electrically connected between the transistor 192 and the bottom conductive column end 128 of the conductive column 114 of the column structure 112 in the stepped structure 101 . In various embodiments, the conductive pillars 114 (ie, the effective conductive pillars or active conductive pillars), the upper conductive structures 191 , the conductive plugs 116 , and the lower conductive structures 194 of the pillar structures 112 in the stepped structure 101 can be used as characters Wire. Transistor 192 (switch) may act as a wordline transistor (wordline switch). The conductive pillars 114 in the stepped structure 101 can be used as word line contacts for the memory cells.

A portion of the conductive pillars 114 of the plurality of pillar structures 112 in the stepped structure 101 may be electrically floating and are thus called dummy conductive pillars. For example, as shown in FIG. 5, the conductive pillars 114 of the plurality of pillar structures 112 in the ladder structure 101, the ladder structure 101B, the ladder structure 101D and the ladder structure 101F are electrically floating, and the ladder structure 101A, the ladder structure The conductive pillars 114 of the plurality of pillar structures 112 in the stair structure 101C, the stair structure 101E and the stair structure 101G.

The decoder may be disposed below the main stack structure 100 and the ladder structure 101 . The bit line transistors and the source line transistors may be disposed on a substrate (not shown) adjacent to a peripheral region of the memory device 10 . In one embodiment, the bit line transistors and the source line transistors may be disposed on the substrate and located in the region directly below the memory device 10 to form a structure (CMOS under array) in which the driving circuits are placed under the array.

In one embodiment, the lower conductive structure 163 and the lower conductive structure 165 may include, but are not limited to, a first lower metal layer ( BM1 ), a second lower metal layer ( BM2 ), a third lower metal layer ( BM3 ), and are disposed in multiple A plurality of lower vias (vias) are provided between the lower metal layers and provide electrical connections between the plurality of lower metal layers.

In one embodiment, the conductive layer 130 may include a first upper metal layer ( TM1 ) and/or a second upper metal layer ( TM2 ).

The tubular elements 113 in the stepped structure 101 and the insulating stack structure 102 may have the same lateral cross-sectional dimension (eg, diameter), eg, cross-sectional dimension (eg, diameter) in the X-Y plane. The transverse cross-sectional dimension of the tubular element 113 may be larger than the transverse cross-sectional dimension of the column element 122 .

6-15 are exemplary illustrations of a method for fabricating the memory device 10 according to one embodiment of the present invention.

Referring to FIG. 6 , a semiconductor device 129 is provided under the polycrystalline semiconductor layer 126 . The semiconductor device 129 may have the structure as described above (refer to FIG. 1). In one embodiment, the semiconductor device 129 may include, but is not limited to, a first lower metal layer ( BM1 ), a second lower metal layer ( BM2 ), a third lower metal layer ( BM3 ) and disposed between the plurality of lower metal layers And a plurality of lower vias for electrical connection between the plurality of lower metal layers are provided. Semiconductor device 129 may include other conductive traces formed in or on inter-layer dielectric layers. This disclosure does not limit this. In one embodiment, the semiconductor device 129 is formed on a substrate (not shown) in a front-end-of-line (FEOL) process.

The semiconductor device may include a dielectric layer 136 (upper dielectric layer). In one embodiment, the dielectric layer 136 may be formed on the third lower metal layer (BM3). The dielectric layer 136 may include a dielectric material including an oxide, such as silicon oxide. Then, the polycrystalline semiconductor layer 126 is formed on the dielectric layer 136 . The polycrystalline semiconductor layer 126 may comprise a doped semiconductor material, such as P+ polysilicon, or an undoped semiconductor material. In one embodiment, the dielectric layer 136 and the polycrystalline semiconductor layer 126 may be formed by a deposition process, such as by chemical vapor deposition (CVD).

The insulating stack structure 102' is formed on the polycrystalline semiconductor layer 126. The insulating stack structure 102' may include a plurality of second insulating layers 110' and a plurality of third insulating layers 111' stacked alternately, for example, along the Z direction. The plurality of second insulating layers 110' isolate the plurality of third insulating layers 111' from each other. In one embodiment, the second insulating layer 110' may include an insulating material, and the insulating material includes a nitride, such as silicon nitride. The third insulating layer 111' may include an insulating material including an oxide, such as silicon oxide. In one embodiment, the second insulating layer 110' and the third insulating layer 111' include different materials. In one embodiment, the insulating stack structure 102' may be formed by sequentially depositing the third insulating layer 111' and the second insulating layer 110'.

Referring to FIG. 7 , the insulating stack structure 102 ′ is patterned, for example, by photolithography, to form the first hole 137 , the second hole 138 and the third hole in the insulating stack structure 102 ′. hole 139. The first hole 137 , the second hole 138 and the third hole 139 pass through the insulating stacked structure 102 ′ and the polycrystalline semiconductor layer 126 in the Z direction. The first hole 137 , the second hole 138 and the third hole 139 expose the sidewalls of the insulating stack structure 102 ′ and the polycrystalline semiconductor layer 126 . In one embodiment, the first hole 137 , the second hole 138 and the third hole 139 can be formed by etching the insulating stack structure 102 ′, such as wet etching or dry etching. (dry etching), and then stop etching when the etching process slightly exceeds the bottom surface 140 of the polycrystalline semiconductor layer 126 . In one embodiment, the polycrystalline semiconductor layer 126 may be regarded as an etch stop layer. The etching process may stop in the dielectric layer 136 . In one embodiment, the first hole 137 , the second hole 138 and the third hole 139 may be gradually narrowed along the Z direction from the top surface 141 of the insulating stack structure 102 ′ to the bottom surface 140 of the polycrystalline semiconductor layer 126 . In one embodiment, each of the first hole 137 , the second hole 138 and the third hole 139 may have a direction along the Z direction from the top surface 141 of the insulating stack structure 102 ′ to the bottom surface of the polycrystalline semiconductor layer 126 140 Tapered transverse cross-sectional dimension (eg, transverse cross-sectional dimension in the X-Y plane). In one embodiment, on any X-Y plane (this X-Y plane intersects with the first hole 137 , the second hole 138 and the third hole 139 ), the transverse cross-sectional dimension of the first hole 137 is smaller than the transverse cross-section of the second hole 138 The transverse cross-sectional dimension of the first hole 137 is smaller than that of the third hole 139 , and the transverse cross-sectional dimension of the second hole 138 is approximately the same as the transverse cross-sectional dimension of the third hole 139 .

Referring to FIG. 8, the memory film 117 and the channel layer 118' are formed on the insulating stack structure 102' and are lined in the first hole 137, the second hole 138 and the third hole. In the first hole 137, the second hole 138 and the third hole, the memory film 117 and the channel layer 118' are formed on the inner sidewall and bottom of the first hole 137, the second hole 138 and the third hole. In one embodiment, the memory film 117 and the channel layer 118' may be formed by a deposition process, such as by chemical vapor deposition. In one example, the memory film 117 and the channel layer 118' are formed in a furnace.

The memory film 117 may include a multi-layer structure known in the field of memory technology, such as ONO structure, ONONO structure, ONONONO structure, SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, BE-SONOS structure, TANOS structure Structure, MA BE-SONOS structure and combinations thereof. The channel layer 118' may comprise a semiconductor material, such as a doped semiconductor material or an undoped semiconductor material. In one embodiment, the channel layer 118' may comprise polysilicon, such as doped polysilicon or undoped polysilicon.

Referring to FIG. 9, the memory film 117 and the channel layer 118' on the insulating stack structure 102' are removed to expose the top of the insulating stack structure 102' and form a flat top surface on the X-Y plane. The channel layer 118' may include a dummy channel layer 118, a channel layer 118A, etc. as shown in FIG. 1 . At this stage of processing, the channel layer 118' and the memory film 117 at the bottom of the first hole 137, the second hole 138 and the third hole 139 are removed to expose the dielectric layer 136. In other words, the channel layers 118/118A at the bottoms of the first hole 137, the second hole 138 and the third hole 139 are not connected to avoid a current leakage path. The channel layer 118/118A may have a tubular shape and have two open ends. In one embodiment, the memory film 117 on the insulating stack structure 102', the channel layer 118' on the insulating stack structure 102', and the channel layer 118' at the bottom of the first hole 137, the second hole 138 and the third hole 139, The removal of the memory film 117 may be performed by an etching-back process.

Referring to FIG. 10 , the insulating film 119 is formed in the first hole 137 , the second hole 138 and the third hole 139 . The insulating film 119 may include a dielectric material including an oxide such as silicon oxide. In one embodiment, the insulating film 119 may be formed by the following steps: depositing the insulating film 119 on the insulating stack structure 102' and filling the first hole 137, the second hole 138 and the third hole 139; removing the insulating stack The insulating film 119 on the structure 102' to expose the top surface 141 of the insulating stacked structure 102', for example, by chemical-mechanical planarization or etch-back; the first opening 142, the second opening 143 and the third opening 144 are respectively formed in the insulating film 119 in the first hole 137, the second hole 138 and the third hole 139, for example, by wet etching or dry etching. The first opening 142 , the second opening 143 and the third opening 144 extend along the Z direction and expose the sidewalls of the insulating film 119 in the first opening 137 , the second opening 138 and the third opening 139 . In one embodiment, the etching process for forming the first opening 142 , the second opening 143 and the third opening 144 may stop at the insulating film 119 . In one embodiment, the first opening 142 , the second opening 143 and the third opening 144 may be located at the center of the first hole 137 , the second hole 138 and the third hole 139 , respectively.

In one embodiment, on any X-Y plane (this X-Y plane intersects with the first opening 142, the second opening 143 and the third opening 144), the transverse cross-sectional dimension of the first opening 142 is smaller than that of the second opening. The transverse cross-sectional dimension of the hole 143 , the transverse cross-sectional dimension of the first opening 142 is smaller than that of the third opening 144 , and the transverse cross-sectional dimension of the second opening 143 is approximately the same as that of the third opening 144 .

Referring to FIG. 11 , the insulating pillars 125 are respectively formed in the first opening 142 , the second opening 143 and the third opening 144 . The insulating pillars 125 may include insulating materials including nitrides, such as silicon nitride. The insulating pillars 125 may be formed by a deposition process, such as by chemical vapor deposition.

Referring to FIG. 12 , the source/drain pillars 123 and the source/drain pillars 124 are formed on opposite sides of the insulating pillars 125 in the first openings 142 . The insulating pillars 125 isolate the source/drain pillars 123 from the source/drain pillars 124 from each other. The source/drain pillars 123 and the source/drain pillars 124 may be formed by forming two narrow openings on opposite sides of the insulating pillars 125 in the first openings 142, the narrow openings allowing the channel The sidewalls of the layer 118A, and/or the sidewalls of the insulating pillars 125 are exposed; the source/drain pillars 123 and the source/drain pillars 124 are respectively formed in the narrow openings to fill the narrow openings. In one embodiment, the narrow openings may be formed by an etching process, such as by wet etching or dry etching. The narrow openings may not overlap each other. In one embodiment, the source/drain pillars 123 and the source/drain pillars 124 may be formed by a deposition process, such as by a chemical vapor deposition process. Source/drain pillars 123 and source/drain pillars 124 may comprise doped semiconductor material, such as N+ polysilicon, or may comprise undoped semiconductor material. Disposing the insulating pillars 125 between the source/drain pillars 123 and the source/drain pillars 124 helps to improve the process window to avoid PLG-to-PLG punch.

Referring to FIG. 13, trenches 145 are formed in the insulating stack structure 102'. Trench 145 passes through insulating stack 102' in the Z direction. The trenches 145 expose the sidewalls of the insulating stack structure 102' and the polycrystalline semiconductor layer 126. In one embodiment, the insulating stack structure 102 ′ may be etched, such as by wet etching or dry etching, to form the trenches 145 and stop the etching process at the polycrystalline semiconductor layer 126 .

Referring to FIG. 14, etching is performed through the trench 145 to remove part of the second insulating layer 110' (ie, the second insulating layer 110' around the first hole 137 and the second hole 138) to form a third insulating layer space between layers 111'. In one embodiment, the etching process may use hot phosphoric acid (phosphoric acid; H ₃ PO ₄ ). By controlling the etching time, part of the second insulating layer 110 ′ (ie, the second insulating layer 110 ′ around the first hole 137 and the second hole 138 ) can be removed, while remaining part of the second insulating layer layer 110' (ie, the second insulating layer 110' around the third hole 139). In other words, the second insulating layer 110' around the third hole 139 is not removed in the etching process. Then, a dielectric film 146 may be lined in the space between the third insulating layers 111'. A conductive material 147 , such as tungsten, may be formed to fill the space between the third insulating layers 111 ′ to form the conductive film 104 and the conductive stepped layer 106 as shown in FIG. 1 . The dielectric film 146 may include a storage layer and a barrier layer (not shown). The dielectric film 146 may include a high dielectric constant (high-k) material. In one embodiment, the conductive film 104 can be used as a gate. In one embodiment, the dielectric film 146 and the conductive film 104 may be formed by an HKMG (High-k Metal Gate) process. The process included in FIG. 14 may be understood as a gate replacement process.

In one embodiment, the memory layer of the memory device 10 may include the memory film 117 and the dielectric film 146 shown in FIG. 14 . That is, the dielectric film 146 may serve as a memory material. The memory layer may include any charge trapping structure known in the memory technology field, such as ONO structure, ONONO structure, ONONONO structure, SONOS structure, BE-SONOS structure, TANOS structure, MA BE-SONOS structure and combinations thereof. The charge trapping structure may use nitrides such as silicon nitride, or other similar high dielectric constant materials including metal oxides such as aluminum oxide (Al ₂ O ₃ ), zirconium oxide (HfO ₂ ), and the like. Memory cells can be defined in memory layers. For example, when the memory layer includes the memory film 117 and the dielectric film 146, the memory film 117 can be understood as a tunnel oxide layer, and the memory film 117 can include silicon dioxide (SiO ₂ ) or only silicon dioxide; The dielectric film 146 can be used as a memory material, and the dielectric film 146 can include multilayer memory materials known in the field of memory technology, such as aluminum oxide, titanium nitride (TiN), ONO structure, ONONO structure, ONONONO structure , SONOS structure, BE-SONOS structure, TANOS structure, MA BE-SONOS structure and combinations thereof, etc.

Then, insulating strips 103 are formed to fill trenches 145, eg, by a deposition process.

Referring to FIG. 15 , the conductive pillars 114 are formed in the insulating film 119 in the second hole 138 and the third hole 139 . The conductive pillars 114 extend along the Z direction, pass through the dielectric layer 136, and contact the semiconductor device 129, eg, the third lower metal layer (BM3). The conductive pillars 114 may include a conductive material, such as tungsten. In one embodiment, the conductive pillars 114 may be formed by the following steps: removing the conductive pillars 114 formed in the second openings 143 and the third openings 144 by an etching process, such as wet etching or dry etching 10-11); the etching process can be stopped at the bottom surface 148 of the dielectric layer 136; deep openings are formed by the etching process; the conductive posts 114 are respectively formed in the deep The openings are processed, for example, by chemical vapor deposition. The conductive pillar 114 is electrically connected to the semiconductor device 129 . In this processing stage, the conductive pillars 114 formed in the second holes 138 can be understood as the conductive pillars 114 in the stepped structure 101 shown in FIG. 1 , and the conductive pillars 114 formed in the third holes 139 can be understood as The conductive pillars 114 in the insulating stack structure 102A shown in FIG. 1 .

The present disclosure provides memory devices having bit line contacts, source line contacts, and/or word line contacts surrounded by dummy channel layers, and the bit line contacts, source line contacts, and/or word line contacts can be Tubular element protection and electrical insulation. With such a configuration, additional isolation regions for electrically insulating bit line contacts, source line contacts and/or word line contacts in the memory device can be omitted, which can improve the space efficiency of the memory device and reduce production cost, can improve the design freedom of memory devices, and can improve the degree of process integration. In addition, the present disclosure provides a memory device having a polycrystalline semiconductor layer used as an etch stop layer, the polycrystalline semiconductor layer helps to improve the uniformity of holes for pillar elements, and at the same time can improve the efficiency of the etching process controllability.

It should be noted that the above-mentioned diagrams, structures and steps are used to describe some embodiments or application examples of the present disclosure, and the present disclosure is not limited to the scope and application of the above-mentioned structures and steps. Other embodiments with different structural aspects, such as known components of different internal components, can be applied, and the exemplary structures and steps can be adjusted according to the needs of practical applications. Therefore, the structures in the drawings are only used to illustrate, but not to limit the present invention. Those skilled in the art should know that the related structures and steps in the application of the present disclosure, such as the arrangement or configuration of the related elements and layers in the semiconductor structure, or the details of the manufacturing steps, etc., may be required according to the actual application. Adjustments and changes accordingly.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

10: Memory device S: Stacked structure 100, 100A, 100B, 100C: Main stack structure 101, 101A, 101B, 101C, 101D, 101E, 101F, 101G: Ladder structure 102, 102A, 102': Insulating stack structure 103: Insulation strip 104: Conductive film 105: first insulating layer 106: Conductive step layer 107: Insulation step layer 108, 120, 121, 140, 148: Bottom surface 109,141: Top Surface 110, 110': Second insulating layer 111,111': Third insulating layer 112: Cylinder structure 113: Tubular elements 114: Conductive column 115: Steps 116: Conductive plug 117,417: Memory Film 118: Dummy channel layer 118A, 118B, 118': channel layer 119: insulating film 122, 122A: Column elements 123, 124: source/drain posts 125: Insulation column 126: polycrystalline semiconductor layer 127: Upper conductive column end 128: Lower conductive column end 129: Semiconductor Devices 130: Conductive layer 136: Dielectric layer 137: The first hole 138: Second hole 139: Third hole 142: The first opening 143: Second opening 144: The third opening 145: Groove 146: Dielectric film 147: Conductive Materials 161,192: Transistor 163, 165, 194: Lower Conductive Structures 171, 173, 181, 183, 191: Upper Conductive Structures X,Y,Z: direction

FIG. 1 is a schematic perspective view of a memory device according to an embodiment of the present invention; 2A is a schematic perspective view of a memory device according to an embodiment of the present invention; FIG. 2B shows one of a plurality of pillar structures in the insulating stack structure shown in FIG. 1; FIG. 2C shows one of a plurality of column structures in the stepped structure shown in FIG. 1; FIG. 3 is a schematic top view of a main stack structure according to an embodiment of the present invention; FIG. 4 is a schematic perspective view of a memory device according to an embodiment of the present invention; FIG. 5 is a schematic top view of a memory device according to an embodiment of the present invention; and 6-15 are exemplary illustrations of a method for fabricating a memory device according to an embodiment of the present invention.

10: Memory device

S: Stacked structure

100, 100A: Main stack structure

101, 101A, 101B, 101C: Ladder structure

102, 102A: Insulating Stacked Structures

103: Insulation strip

106: Conductive step layer

107: Insulation step layer

121: Bottom surface

110: Second insulating layer

111: The third insulating layer

112: Cylinder structure

113: Tubular elements

114: Conductive column

116: Conductive plug

122: Column element

126: polycrystalline semiconductor layer

127: Upper conductive column end

129: Semiconductor Devices

130: Conductive layer

161,192: Transistor

163, 165, 194: Lower Conductive Structures

171, 173, 181, 183, 191: Upper Conductive Structures

X,Y,Z: direction

Claims (10)

A memory device comprising: a stack structure; a tubular element including a dummy channel layer, and the tubular element penetrates the stacked structure; a conductive column surrounded by the tubular element, and the conductive column extends beyond a bottom surface of the dummy channel layer; and A plurality of memory cells are in the stacked structure and are electrically connected to the conductive column. The memory device of claim 1, wherein the dummy channel layer has a tubular shape, and the tubular element further comprises: a memory film, wherein the dummy channel layer is between the memory film and the conductive pillar, wherein the memory film has a tubular shape; and an insulating film, the insulating film is interposed between the conductive pillar and the dummy channel layer, Wherein the insulating film has a tubular shape. The memory device of claim 1, wherein the conductive pillar serves as a bit line contact, a source line contact or a word line contact for the memory cells. The memory device of claim 1, further comprising a semiconductor device located below, and the semiconductor device is electrically connected to an end of a lower conductive column of the conductive column, wherein the semiconductor device includes a bit line switch (switch) or a source line switch. The memory device as claimed in claim 1, wherein the stacking structure comprises an insulating stacking structure, the tubular element and the conductive column pass through the insulating stacking structure, and the memory device further comprises an upper conductive layer electrically connected to the between the memory cell and the end of one of the conductive columns on the conductive column, wherein the conductive column is used as a bit line contact structure or a source line contact structure. The memory device of claim 5, wherein the conductive layer comprises a local bit line and a global bit line, the local bit line passing through the insulating stack structure The conductive column is electrically connected to the global bit line. The memory device of claim 1, wherein the stacked structure comprises an insulating stacked structure, the memory device further comprises a lower conductive structure and a plurality of pillar structures, the lower conductive structure is located under the insulating stacked structure, the pillars Each of the body structures includes the tubular element and the conductive post, and each of the post structures passes through the insulating stack structure, and lower conductive post ends of the conductive posts are electrically conductive by the lower The structures are electrically connected to each other. The memory device of claim 1, wherein the stacked structure includes a stepped structure, the stepped structure includes a plurality of conductive stepped layers, the memory device further includes a conductive plug, the conductive plug is electrically connected and disposed on the on one of the conductive stepped layers, wherein the tubular element passes through the one of the conductive stepped layers. The memory device of claim 8, wherein the tubular element and the conductive column further pass through another conductive layer, and the other conductive layer is located below the one conductive layer. The memory device of claim 8, further comprising a conductive layer located above, and the conductive layer is electrically connected between the conductive plug and the conductive column.

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