TWI832643B - Memory device and method for manufacturing the same - Google Patents

Abstract

A memory device is provided. The memory device includes a stacked structure having an array region and a staircase region adjacent to the array region, a lower isolation structure in the stacked structure, two memory strings in the array region of the stacked structure and at least one lower support member in the staircase region of the stacked structure. The stacked structure includes conductive layers. The lower isolation structure has an upper surface in a lower portion of the stacked structure. The lower isolation structure extends from the array region to the staircase region. The lower isolation structure separates at least one conductive layer of the conductive layers into a first conductive strip and a second conductive strip. The first conductive strip and the second conductive strip are electrically isolated from each other. Two memory strings are electrically connected to the first conductive strip and the second conductive strip respectively. A material of the lower support member is the same as a material of the lower isolation structure, and a height of the lower support member is the same as a height of the lower isolation structure.

Description

Memory device and method of manufacturing same

The present invention relates to a memory device and a manufacturing method thereof, and in particular to a three-dimensional memory device and a manufacturing method thereof.

Recently, as the demand for better memory devices has gradually increased, various three-dimensional (3D) memory devices have been provided, such as three-dimensional NAND (3D NAND) memory devices having a multi-layer stacked structure. This type of three-dimensional memory device can achieve higher storage capacity and have better electrical properties, such as good data storage reliability and operation speed.

However, as the storage density and integration of three-dimensional memory devices increase, the manufacturing process of the memory devices becomes more difficult, resulting in a decrease in yield. Therefore, there is a need to propose an improved memory device and a manufacturing method thereof, which can increase the yield of the memory device in the manufacturing process.

The present invention relates to a memory device including a lower support member and a manufacturing method thereof, so as to improve the problem of insufficient support force of the memory device during the manufacturing process, thereby increasing the yield rate of the manufacturing process.

According to an embodiment of the present invention, a memory device is provided. The memory device includes a stacked structure having an array area and a stepped area adjacent to the array area, a lower isolation structure arranged in the stacked structure, two memory cell series arranged in the array area of the stacked structure, and a stepped area arranged in the stacked structure At least one support piece in the The stacked structure contains multiple conductive layers. The lower isolation structure has a surface above the lower portion of the stacked structure. The lower isolation structure extends from the array area to the step area. The lower isolation structure separates at least one conductive layer among the plurality of conductive layers into a first conductive strip and a second conductive strip, and the first conductive strip and the second conductive strip are electrically isolated from each other. The two memory cell series are electrically connected to the first conductive strip and the second conductive strip respectively.

According to another embodiment of the present invention, a method of manufacturing a memory device is provided. The method includes the following steps. A layer stack is formed on a base plate along a first direction, wherein the layer stack includes an array area and a step area adjacent to the array area. A lower isolation structure and at least a lower support member are formed in the layer stack, and the lower isolation structure and the lower support member extend downward toward the bottom plate, wherein the lower isolation structure extends from the array area to the step along a second direction different from the first direction. area, the lower support member is formed in the step area, the material of the lower support member is the same as the material of the lower isolation structure, and the height of the lower support member is the same as the height of the lower isolation structure. An insulation stack structure is formed on the layer stack, wherein the lower isolation structure and the lower support member are located under the insulation stack structure.

In order to have a better understanding of the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings.

Relevant embodiments are presented below, and the memory device and the manufacturing method thereof proposed in the present disclosure are described in detail along with the drawings. However, this disclosure is not limited thereto. The descriptions in the embodiments, such as detailed structures, steps of manufacturing methods and material applications, are only for illustrative purposes, and the scope of protection of the present disclosure is not limited to the described aspects. Those in the relevant technical field can change and modify the structures and manufacturing methods of the embodiments to meet the needs of practical applications without departing from the spirit and scope of the present disclosure. Therefore, other implementation aspects not proposed in this disclosure may also be applicable. Furthermore, the drawings are simplified to facilitate clear explanation of the contents of the embodiments, and the dimensional proportions in the drawings are not drawn to the same proportions as the actual product. Therefore, the description and drawings are only used to describe the embodiments and are not used to limit the scope of the present disclosure. The same or similar component symbols are used to represent the same or similar components.

The ordinal numbers used in the specification and the scope of the patent application, such as "first", "second", "third", etc., are used to modify the elements. They do not imply or represent that the element has any previous ordinal numbers, nor does it mean that the element has any previous ordinal numbers. Represents the order of a certain component with another component, or the order of the manufacturing method. The use of these serial numbers is only used to clearly distinguish one component with a certain name from another component with the same name.

Various embodiments of the present invention can be applied to a variety of different three-dimensional (3D) stacked memory structures. For example, embodiments may be applied to, but are not limited to, three-dimensional NAND flash memory devices.

Figure 1 is a schematic top view of a memory device 10 according to an embodiment of the present invention. As shown in FIG. 1 , the stacked structure S of the memory device 10 (shown in FIGS. 2A to 2B and 2D to 2E) has an array area AR and a step area SR adjacent to the array area AR. Figures 2A~2C are mainly used to illustrate the array area AR. Figures 2D~2G are mainly used to illustrate the step region SR.

Please refer to FIG. 1 and FIG. 2A at the same time. FIG. 2A is a schematic cross-sectional view of the memory device 10 along the sectional line P1 in FIG. 1 . The memory device 10 may include a base plate 100, a stacked structure S, a plurality of pillar elements 103, at least one upper isolation structure 104, at least a lower isolation structure 105, and a plurality of isolation elements 106.

The stacked structure S is arranged on the base plate 100 . The stacked structure S may include a plurality of insulating layers 101 and a plurality of conductive layers 102 staggeredly stacked along the first direction D1. The first direction D1, the second direction D2 and the third direction D3 may be perpendicular to each other. The first direction D1 may be the normal direction of the upper surface of the bottom plate 100 . The first direction D1 may be, for example, the Z direction, the second direction D2 may be, for example, the X direction, and the third direction D3 may be, for example, the Y direction. The plurality of insulating layers 101 isolate the plurality of conductive layers 102 from each other. For the sake of simplicity, FIG. 2A does not show all the layers of the stacked structure S. The number of layers in the stacked structure S can be adjusted according to needs. In one embodiment, the conductive layer 102 in the stacked structure S has a thickness T1 in the first direction D1, and the thickness T1 is about 200~350 angstrom; ).

A plurality of column elements 103 are dispersedly arranged in the stacked structure S. The pillar element 103 may extend through the stacked structure S along the first direction D1. The pillar component 103 may include a memory layer 121, a channel layer 122, an insulating pillar 123 and a pad 124. Memory layer 121 may surround channel layer 122. The memory layer 121 may have a tubular shape, such as a tubular shape with one end open and the other end closed. The channel layer 122 may be disposed between the memory layer 121 and the insulating pillar 123 and surround the insulating pillar 123 . The channel layer 122 may have a tubular shape, such as a tubular shape with one end open and the other end closed. The lower portion of the memory layer 121 is removed to expose a portion of the channel layer 122 . The exposed portion of the channel layer 122 is electrically connected to the base plate 100 . In another example, the memory layer 121 may have a tube shape with both ends open. The bottom of the memory layer 121 is removed to expose a portion of the channel layer 122 . The exposed portion of the channel layer 122 is electrically connected to the base plate 100 . The pads 124 can be disposed on the channel layer 122 and the insulating pillars 123 and are surrounded by the memory layer 121 . The pads 124 can be electrically connected to the channel layer 122 .

At least one upper isolation structure 104 is configured in the stacked structure S. The upper isolation structure 104 may extend along the first direction D1 and penetrate one or more insulating layers 101 and/or one or more conductive layers 102 in the stacked structure S. For example, in the embodiment shown in FIG. 2A , the upper isolation structure 104 can be disposed on the upper part of the stacked structure S, and can penetrate the four insulating layers 101 and the three conductive layers 102 located on the upper part of the stacked structure S. Specifically, the upper isolation structure 104 penetrates the three conductive layers 102 farthest from the bottom plate 100 among the plurality of conductive layers 102, and causes each of the three conductive layers 102 to be separated into conductive strips 133, 134, 135, 136. The conductive strips 133, 134, 135 and 136 are electrically isolated from each other. In one embodiment, the upper isolation structure 104 can separate at least three conductive layers 102 located on the upper portion of the stacked structure S. For example, the upper isolation structure 104 can separate 3 to 7 conductive layers 102 located on the upper part of the stacked structure S.

At least one isolation structure 105 is configured in the stack structure S. The lower isolation structure 105 may extend along the first direction D1 and penetrate one or more insulation layers 101 and/or one or more conductive layers 102 in the stack structure S. For example, in the embodiment shown in FIG. 2A , the lower isolation structure 105 can be disposed at the lower part of the stacked structure S, and penetrates the four insulating layers 101 and the three conductive layers 102 located at the lower part of the stacked structure S. The upper surface 105u of the lower isolation structure 105 may be located at the lower part of the stacked structure S. In one example, the lower isolation structure 105 may extend from the upper surface 105u to the base plate 100 . The lower isolation structure 105 penetrates at least three conductive layers 102 closest to the base plate 100 among the plurality of conductive layers 102, and separates each of the at least three conductive layers 102 into conductive strips 131, 132. The conductive strips 131 (eg, the first conductive strips) and the conductive strips 132 (eg, the second conductive strips) may be located on opposite sides of the lower isolation structure 105 respectively. The conductive strips 131 and 132 are electrically isolated from each other. In one embodiment, the lower isolation structure 105 can separate at least three conductive layers 102 located at the lower part of the stacked structure S. For example, the lower isolation structure 105 can separate 3 to 10 conductive layers 102 located at the lower part of the stacked structure S.

In this embodiment, the number of the upper isolation structures 104 is greater than the number of the lower isolation structures 105 , and an upper isolation structure 104 among the plurality of upper isolation structures 104 may at least partially overlap with the lower isolation structure 105 in the first direction D1 . In one embodiment, on a plane including the second direction D2 and the third direction D3, the projected position of the lower isolation structure 105 in the array area AR may be substantially aligned with an upper isolation structure 104 among the plurality of upper isolation structures 104. The projected position (for example, the lower isolation structure 105 generally aligned with an upper isolation structure 104 is represented by a dotted line in Figure 1).

A plurality of isolation elements 106 are dispersedly arranged in the stacked structure S. As shown in FIG. 1 , the isolation element 106 may be a strip extending along the second direction D2. As shown in FIG. 2B, the isolation element 106 may extend through the stacked structure S along the first direction D1. The isolation element 106 may include an isolation film 141 and a conductive film 142. The isolation film 141 may be disposed between the conductive film 142 and the stacked structure S. The isolation film 141 can be used to electrically isolate the conductive film 142 from the plurality of conductive layers 102 . The bottom of the isolation film 141 is removed to expose a portion of the conductive film 142 . The exposed portion of the conductive film 142 is electrically connected to the base plate 100 . The isolation element 106 may serve as a source line, such as a common source line.

The memory device 10 may also include a plurality of memory cell series arranged in the array area AR of the stacked structure S. Each memory cell series may include a plurality of memory cells arranged along the first direction D1, and the memory cells may be defined in the memory layer 121 at the intersection of the conductive layer 102 and the channel layer 122 of the pillar element 103. For the sake of simplicity, only four memory cell series M1, M2, M3, and M4 are marked in Figures 1 and 2A. However, in practice, the memory device may include more memory cell series. The memory cell string M1 can share the channel layer 122 of the pillar element 103 where it is located. The conductive strips 131 and 133 can electrically control the memory cell series M1. The memory cell series M2 can share the channel layer 122 of the pillar element 103 where it is located, and the conductive strips 131 and 134 can electrically control the memory cell series M2. . The memory cell series M3 can share the channel layer 122 of the pillar element 103 where it is located, and the conductive strips 132 and 135 can electrically control the memory cell series M3. The memory cell series M4 can share the channel layer 122 of the pillar element 103 where it is located, and the conductive strips 132 and 136 can electrically control the memory cell series M4.

In one embodiment, the memory device 10 may include at least one string selection line and at least one ground selection line electrically connected to opposite ends of the memory cell string. For example, the three conductive layers 102 (conductive strips 133 , 134 , 135 , 136 ) in the memory device 10 that are farthest from the base plate 100 can serve as string selection lines for the memory cell string. The memory cells defined in the memory layer 121 at the intersection of the conductive strips 133, 134, 135, 136 and the channel layer 122 of the pillar element 103 can serve as series selection transistors. The three conductive layers 102 (conductive strips 131, 132) of the memory device 10 closest to the base plate 100 can serve as ground selection lines for the memory cell strings. The memory cells defined in the memory layer 121 at the intersection of the conductive strips 131 and 132 and the channel layer 122 of the pillar element 103 can serve as ground selection transistors. Other conductive layers 102 in the memory device 10 (eg, the conductive layer 102 that is not separated by the upper isolation structure 104 and the lower isolation structure 105 ) may serve as word lines. In the memory device 10 , the conductive layer 102 serving as the series selection line is divided into conductive strips 133 , 134 , 135 , and 136 by the upper isolation structure 104 . The conductive strips 133, 134, 135, 136 are electrically isolated from each other. Therefore, the series selection transistors electrically connected to the memory cell series M1, M2, M3, and M4 respectively can be independently controlled through different series selection lines. In the memory device 10 , the conductive layer 102 serving as the ground selection line is divided into conductive strips 131 and 132 by the lower isolation structure 105 . The conductive strips 131, 132 are electrically isolated from each other. Therefore, the ground selection transistors electrically connected to the memory cell series M1 and M2 respectively can be controlled through a common ground selection line. The ground selection transistors electrically connected to the memory cell series M3 and M4 respectively can be controlled through another common ground selection line.

The memory device 10 may also include at least a first upper conductive structure 107 and at least a second upper conductive structure 108 . At least one first upper conductive structure 107 and at least one second upper conductive structure 108 may be disposed above the stacked structure S. The first upper conductive structure 107 and the second upper conductive structure 108 can be electrically connected to the channel layer 122 and the pad 124 of different pillar elements 103 respectively. In this embodiment, the first upper conductive structure 107 and the second upper conductive structure 108 are disposed above the eight pillar elements 103 arranged along the third direction D3 (as shown in FIG. 1 ). The first upper conductive structure 107 is electrically connected to the channel layer 122 (as shown in FIG. 2A ) of four pillar elements 103 among the eight pillar elements 103 and the memory cell series M1, M2, M3, M4. The second upper conductive structure 108 is electrically connected to the channel layers 122 (shown with dotted lines in FIG. 2A ) of the other four pillar elements 103 among the eight pillar elements 103 and other memory cells in series. The first upper conductive structure 107 and the second upper conductive structure 108 can serve as bit lines.

In one embodiment, the memory device 10 may include multiple blocks, and multiple isolation elements 106 isolate the multiple blocks from each other. Each block may include multiple sub-blocks, and multiple upper isolation structures 104 isolate the multiple sub-blocks from each other. The memory device 10 can be operated on a sub-block basis, such as a read operation or an erase operation.

Figure 2B is a schematic cross-sectional view of the memory device 10 along the section line P1-1 in Figure 1. In one embodiment, the memory device 10 may further include a plurality of tubular elements 109 dispersedly arranged in the stack structure S. The tubular element 109 may extend through the stack structure S along the first direction D1 and be disposed under the upper isolation structure 104 . Furthermore, part of the tubular element 109 may pass through the lower isolation structure 105 along the first direction D1, so that the lower isolation structure 105 extends discontinuously in the array area AR along the second direction D2. The tubular component 109 may include a memory layer 151 , a dummy channel layer 152 and an insulating pillar 153 . Memory layer 151 may surround dummy channel layer 152. The memory layer 151 may have a tubular shape, such as a tubular shape with one end open and the other end closed. The dummy channel layer 152 may be disposed between the memory layer 151 and the insulating pillar 153 and surround the insulating pillar 153 . The dummy channel layer 152 may have a tubular shape, such as a tubular shape with one end open and the other end closed. The memory layer 151 of the tubular element 109 may be similar to the memory layer 121 of the pillar element 103 . The insulating posts 153 of the tubular element 109 may be similar to the insulating posts 123 of the post element 103 . In one embodiment, the dummy channel layer 152 may refer to a channel layer without a driving circuit. In one embodiment, the dummy channel layer 152 can be understood as an electrically floating component.

In this embodiment, the memory device 10 may further include a circuit board 100M. The circuit board 100M is disposed under the array area AR, where the circuit board 100M may include a control circuit MT (shown in Figure 2D) (such as a CMOS logic circuit) to form a structure in which the control circuit is placed under the array (CMOS under array). ; CuA). However, the present invention is not limited to this. In one embodiment, the control circuit (for example, a CMOS logic circuit) can be disposed in a peripheral region of the array region AR to form a structure in which the control circuit is placed near the array (CMOS next to array; CnA). In one embodiment, a control circuit (such as a CMOS logic circuit) may be bonded to the array area AR to form a control circuit bonded array (CMOS bonded array; CbA).

Please refer to Figure 2C. FIG. 2C is an equivalent circuit diagram of the memory cell series M1 , M2 , M3 , and M4 in the memory device 10 shown in FIG. 2A . In Figure 2A, each memory cell series M1, M2, M3, M4 is electrically connected to three respective series selection lines. The memory cell series M1 and M2 are connected to three ground selection lines. Memory cell series M3 and M4 are connected to three other ground selection lines. However, for the sake of simplicity, Figure 2C only shows that one end of each memory cell series (M1, M2, M3, M4) is connected to a series selection line. The other ends of the memory cell series M1 and M2 are connected to a ground selection line. The other ends of the memory cell series M3 and M4 are connected to another ground selection line.

A plurality of word lines WL (for example, the conductive layer 102) are electrically connected to the memory cell series M1, M2, M3, and M4. The memory cell series M1, M2, M3, and M4 are electrically connected between the bit line BL (for example, the first upper conductive structure 107) and the source line SL.

The series selection line SSL1 (for example, the conductive strip 133) and the ground selection line GSL1 (for example, the conductive strip 131) are electrically connected to opposite ends of the memory cell series M1. The series selection line SSL1 is electrically connected between the bit line BL and the memory cell series M1. The intersection of the series selection line SSL1 and the memory cell series M1 can be defined as the series selection transistor 161. The ground selection line GSL1 is electrically connected between the source line SL and the memory cell series M1 . The intersection of the ground selection line GSL1 and the memory cell series M1 can be defined as the ground selection transistor 165 . The series selection line SSL2 (for example, the conductive strip 134) and the ground selection line GSL1 (for example, the conductive strip 131) are electrically connected to opposite ends of the memory cell series M2. The series selection line SSL2 is electrically connected between the bit line BL and the memory cell series M2. The intersection of the series selection line SSL2 and the memory cell series M2 can be defined as the series selection transistor 162. The ground selection line GSL1 is electrically connected between the source line SL and the memory cell series M2. The intersection of the ground selection line GSL1 and the memory cell series M2 can be defined as the ground selection transistor 166. The series selection line SSL3 (for example, the conductive strip 135) and the ground selection line GSL2 (for example, the conductive strip 132) are electrically connected to opposite ends of the memory cell series M3. The series selection line SSL3 is electrically connected between the bit line BL and the memory cell series M3. The intersection of the series selection line SSL3 and the memory cell series M3 can be defined as the series selection transistor 163. The ground selection line GSL2 is electrically connected between the source line SL and the memory cell series M3. The intersection of the ground selection line GSL2 and the memory cell series M3 can be defined as the ground selection transistor 167. The series selection line SSL4 (such as the conductive strip 136) and the ground selection line GSL2 (such as the conductive strip 132) are electrically connected to opposite ends of the memory cell series M4. The series selection line SSL4 is electrically connected between the bit line BL and the memory cell series M4. The intersection of the series selection line SSL4 and the memory cell series M4 can be defined as the series selection transistor 164. The ground selection line GSL2 is electrically connected between the source line SL and the memory cell series M4. The intersection of the ground selection line GSL2 and the memory cell series M4 can be defined as the ground selection transistor 168.

When the memory device 10 shown in FIG. 2C is in a read operation, for example, a read operation is performed on a selected memory cell in the memory cell series M1, and the series selection of the series electrically connected to the memory cell series M1 is performed. A voltage is applied to line SSL1 to turn on the series selection transistor 161 electrically connected to the series selection line SSL1, and a voltage is applied to the ground selection line GSL1 electrically connected to the memory cell series M1 to turn on the ground selection line GSL1. The ground selector transistor 165. Since the memory cell series M1 and the memory cell series M2 are both electrically connected to the ground selection line GSL1, the ground selection transistor 166 electrically connected to the memory cell series M2 will also be turned on during this read operation.

In this read operation, the memory cell series M3 and the memory cell series M4 are not electrically connected to the ground selection line GSL1, and the memory cell series M3 and the memory cell series M4 are electrically connected to the ground selection transistor 167 and the ground selection line. The transistor 168 can remain turned off, and no capacitance is generated in the channel layer 122 electrically connecting the memory cell series M3 and the memory cell series M4. In one embodiment, the channel layer 122 electrically connecting the memory cell series M3 and the memory cell series M4 may be in an electrically floating state.

Please refer back to FIG. 1 , the upper isolation structure 104 , the lower isolation structure 105 and the isolation element 106 can extend from the array area AR to the step area SR along the second direction D2 . In one implementation, the lower isolation structure 105 and the isolation element 106 can extend to the end of the step region SR (ie, the end of the step region SR that is farthest from the array area AR), and the upper isolation structure 104 extends to a part of the step region SR. stop. The step area SR includes a first area R1, a second area R2 and a third area R3. The second area R2 is disposed between the first area R1 and the third area R3, and is compared with the first area R1. , the third area R3 is closer to the array area AR. The upper isolation structure 104 extends from the array area AR along the second direction D2, passes through the third area R3 of the step area SR, and stays in the second area R2 without passing through the second area R2. The lower isolation structure 105 and the isolation element 106 pass through the first region R1, the second region R2, and the third region R3. That is, the length of the lower isolation structure 105 and the isolation element 106 in the second direction D2 is greater than the length of the upper isolation structure 104 in the second direction D2. According to an embodiment, in the step region SR, a part of the lower isolation structure 105 may overlap the corresponding upper isolation structure 104 in the first direction D1, and another part of the lower isolation structure 105 may not overlap the corresponding upper isolation structure 104 in the first direction D1. of the upper isolation structure 104 (i.e., separate from the upper isolation structure 104).

Please also refer to Figures 1 and 2D~2E. Figure 2D is a schematic cross-sectional view of the memory device 10 along the X-X' section line in Figure 1 . Figure 2E is a schematic cross-sectional view of the memory device 10 along the Y-Y' section line in Figure 1 . The memory device 10 may further include at least a lower support member 205 and a plurality of vertical support members PIC. The lower supporting members 205 are dispersedly arranged in the step region SR of the stacked structure S, wherein the material of the lower supporting members 205 is the same as the material of the lower isolation structure 105 . As shown in FIG. 2E , the height of the lower support member 205 is the same as the height of the lower isolation structure 105 . For example, the top surface of the lower support member 205 may be coplanar with the top surface of the lower isolation structure 105 (for example, the plane formed by the second direction D2 and the third direction D3). In this embodiment, the lower support member 205 has a rectangular cross-section on the plane formed by the second direction D2 and the third direction D3. However, the present invention is not limited thereto. The cross-section of the lower support member 205 may be circular or oval. , triangle or other suitable shape.

As shown in Figures 1 and 2D~2E, the vertical supports PIC are dispersedly provided in the step area SR and pass through the stacked structure S along the first direction D1. Each vertical support member PIC may include a conductive pillar C2 and an insulating inner pad C1 surrounding the conductive pillar C2. The vertical support PIC may include a functional support PIC1 and a dummy support PIC2. In detail, part of the vertical support member PIC passes through the base plate 100 and is electrically connected to the corresponding control circuit MT in the circuit board 100M to form a functional support member PIC1; the bottom of the other part of the vertical support member PIC stops at the base plate 100. It does not pass through the bottom plate 100 and forms a plurality of dummy supports PIC2. In other words, the dummy support PIC2 is electrically floating. Some holes 100h corresponding to the functional supporter PIC1 may pass through the base plate 100, and an insulating material may be formed in the holes 100h and surround the functional supporter PIC1.

In this embodiment, the number of lower supporting members 205 may be plural, and the lower supporting members 205 are disposed between the vertical supporting members PIC. The length of the lower support member 205 in the second direction D2 is smaller than the length of the lower isolation structure 105 in the second direction D2. During the gate replacement process (detailed below) to form the memory device 10, multiple spaces will be formed between the multiple insulating layers 101, making the overall structure of the memory device relatively fragile. The lower support member 205 and the vertical support member PIC The lower isolation structure 105 can provide support for the overall structure in the step region SR, preventing the insulating layer 101 from deforming or collapsing, thereby preventing the subsequent filling of character lines from deforming, and effectively improving the yield of the process. In the comparative example without the lower support member 205, the gaps between the vertical support members PIC are still large, especially the closer to the bottom plate 100, the larger the gap is. Simply relying on the vertical support members PIC to provide support may still be insufficient. . In this embodiment, since the step area SR is also provided with a lower support member 205, the lower support member 205 can be distributed in the gaps between the vertical support members PIC. Therefore, compared with the comparative example in which the lower support member 205 is not provided, It can provide more supporting force, prevent deformation or collapse of the insulating layer 101 and the character lines, and improve the yield of the process. In addition, since the lower support member 205 and the lower isolation structure 105 can be formed in the same process, there is no need to perform additional process steps to improve the support force, which greatly saves time and cost.

Please also refer to Figures 1 and 2F~2G. Figure 2F is a schematic cross-sectional view of the memory device 10 along the Y1-Y1' section line in Figure 1. Figure 2G is a schematic cross-sectional view of the memory device 10 along the Y2-Y2' section line in Figure 1. The memory device 10 may further include a plurality of contacts COA. The contact COA is electrically connected to the conductive layer 102 of the array area AR corresponding to the conductive layer 102 of the step area SR. The contact COA is, for example, disposed on the corresponding landing area of the conductive layer 102 exposed in the step area SR. The contact COA can also be understood as being in contact with the word lines of the array area AR. Wherein, the projected area of the contact COA disposed in the second region R2 and the third region R3 in the first direction D1 may partially overlap with the lower support member 205 disposed in the second region R2 and the third region R3 in the first direction D1 . The projected area in one direction D1. The projected area of the contact COA disposed in the first region R1 in the first direction D1 does not overlap (i.e., is separated from) the projected area of the lower support 205 disposed in the first region R1 in the first direction D1 . That is, in the first region R1, the lower support member 205 is not provided in the lower area of the vertical projection of the contact member COA. In one embodiment, the bottom of the contact COA is electrically connected to the corresponding conductive layer 102 in the conductive layer 102 , and the top of the contact COA is electrically connected to the corresponding functional support PIC1 through other wires. As shown in FIG. 2F, in the second region R2, the conductive layer 102 under the contact COA can serve as a word line and a ground selection line. For example, the conductive layer 102 serving as the word line may be disposed between the contact COA and the conductive layer 102 serving as the ground selection line, wherein the bottom conductive layer (ie, the conductive layer serving as the ground selection line) 102 may surround the lower support 205 . As shown in Figure 2G, in the first region R1, the conductive layer 102 under the contact COA can serve as a ground selection line.

Figures 3 to 11 illustrate a method for manufacturing a memory device according to an embodiment of the present invention. Among them, Figures 3, 4A, 5 and 7 to 11 illustrate the steps of forming the cross section formed by the section line P1 in Figure 1; Figure 4B illustrates the formation steps formed by the XX' connection line in Figure 1 Section formation steps. Figures 6A to 6E illustrate the steps of forming the cross section formed by the line X1-X1' in Figure 1.

Please refer to Figure 3. Supplied with base plate 100. The layer stack S3 is formed on the base plate 100 along the first direction D1. The layer stack S3 may include a plurality of insulating layers 101 and a plurality of dielectric layers 302 staggeredly stacked along the first direction D1. For example, the layer stack S3 can be formed by sequentially depositing the insulating layer 101 and the dielectric layer 302 . The backplane 100 may include doped or undoped semiconductor materials, such as silicon. However, the present invention is not limited to this. The insulating layer 101 may include an oxide such as silicon oxide, or other suitable dielectric materials. Dielectric layer 302 may include nitride, such as silicon nitride, or other suitable dielectric materials. In one embodiment, the insulating layer 101 and the dielectric layer 302 include different materials. The layer stack S3 may include an array region AR and a step region SR adjacent to each other.

According to some embodiments, a circuit board 100M may be formed below the base plate 100 . The circuit board 100M may include a control circuit MT (such as a CMOS logic circuit) to form a structure in which the control circuit is placed under the array (CMOS under array; CuA), but the invention is not limited thereto.

Please refer to Figures 4A and 4B. A lower isolation structure 105 (shown in FIG. 4A) and a lower support 205 (shown in FIG. 4B) are formed in the layer stack S3. The lower isolation structure 105 and the lower support member 205 may extend downward toward the base plate 100 . For example, the lower isolation structure 105 and the lower support member 205 pass through the layer stack S3 along the first direction D1 and contact the base plate 100 . The lower isolation structure 105 may extend along the first direction D1 and the second direction D2, and separate at least one insulation layer 101 and at least one dielectric layer 302 in the layer stack S3 into two parts isolated from each other. Furthermore, the lower isolation structure 105 may extend from the array area AR to the step area SR along the second direction D2. The lower supports 205 are dispersedly formed in a plurality of predetermined positions in the step region SR. For example, the layer stack S3 may be etched, such as wet etching or dry etching, to remove part of the layer stack S3 and form a plurality of trenches 401 and 402 . ; The trenches 401 and 402 extend downward along the first direction D1 and stop on the upper surface 100u of the base plate 100 ; the trenches 401 and 402 expose the sidewalls of the layer stack S3 (also serving as the sidewalls of the trenches 401 and 402 ) , and expose part of the upper surface 100u of the base plate 100 (also serving as the bottom of the trenches 401 and 402); then, the lower isolation structure 105 is formed in the trench 401 through a deposition process, and the lower support member 205 can be formed in trench 402. Lower isolation structure 105 may include a dielectric material, such as an oxide. The lower support member 205 may be formed in the same process as the lower isolation structure 105 , and the material of the lower support member 205 may be the same as the material of the lower isolation structure 105 . That is, the lower support 205 may include a dielectric material, such as an oxide.

In some embodiments, a plurality of holes 100h passing through the base plate 100 may be formed in the stepped region SR before forming the layer stack S3, as shown in FIGS. 4B and 6A. The holes 100h may correspond to a plurality of predetermined positions where vertical supports PIC (ie, functional supports PIC1) are to be formed that are electrically connected to the control circuit MT in the circuit board 100M. Insulating material may be included in the hole 100h.

Please refer to Figure 5. An insulation stack structure S4 is formed on the layer stack S3. The insulation stack structure S4 may cover the upper surface 105u of the lower isolation structure 105, the upper surface of the lower support 205 (not shown in FIG. 5), and the upper surface 501u of the layer stack S3. The lower isolation structure 105, the lower support 205 (not shown in FIG. 5) and the layer stack S3 may be located under the insulation stack structure S4. The insulation stack structure S4 may include a plurality of insulation layers 101 and a plurality of dielectric layers 302 staggeredly stacked along the first direction D1. For example, the insulating stack structure S4 can be formed by sequentially depositing the insulating layer 101 and the dielectric layer 302 . In one embodiment, the number of layers in the insulation stack S4 may be greater than the number of layers in the layer stack S3.

Figures 6A to 6E illustrate some process steps performed on the step region SR.

Please refer to Figure 6A. After the lower support 205 is formed in the step region SR and the insulation stack structure S4 is formed, the insulation stack structure S4 and the layer stack S3 in the step region SR may be patterned to form a ladder-like structure. Thereafter, insulating filler 201 can be deposited on the stepped structure.

Please refer to Figure 6B. A plurality of vertical openings PICh are formed. The vertical openings PICh are arranged in the step region SR, and the lower support 205 is provided between the vertical openings PICh. The vertical opening PICh extends along the first direction D1 and passes through the corresponding layer stack S3 or/and the insulation stack structure S4. A part of the vertical opening PICh extends along the first direction D1, passes through the base plate 100 and exposes the corresponding control circuit MT in the circuit board 100M for forming the subsequent functional support PIC1; the other part of the vertical opening PICh extends along the first direction D1. One direction extends in the direction D1, stops at the base plate 100 and exposes the base plate 100 without penetrating the base plate 100 for forming the subsequent dummy support PIC2. For example, the vertical opening PICh can be formed through an etching process.

Please refer to Figures 6C~6D. An insulating inner pad C1 is formed in the vertical opening PICh. For example, the insulating material can be conformally formed in the vertical opening PICh through a deposition process, as shown in FIG. 6C. Thereafter, the insulating material outside the vertical opening PICh is removed through an etching process, and the insulating material at the bottom of the vertical opening PICh is removed to expose the base plate 100 or the corresponding control circuit MT, and form an insulating inner pad C1, as shown in 6D As shown in the figure. In this embodiment, the material of the insulating inner pad C1 may include low temperature oxide material (LTO).

Referring to Figure 6E, conductive pillars C2 are formed in the vertical openings PICh. For example, the conductive material can be filled in the vertical opening PICh (ie, the space surrounded by the insulating inner pad C1) through a deposition process. In this way, a vertical support PIC is formed including the conductive pillar C2 and the insulating inner pad C1 surrounding the conductive pillar C2. Vertical supports PIC are formed in the step region SR, and lower supports 205 are formed between the vertical supports PIC. Among them, the vertical support PIC includes a functional support PIC1 and a dummy support PIC2. A part of the vertical support PIC (ie, the functional support PIC1) passes through the layer stack S3 and the base plate 100 and is electrically connected to the corresponding control circuit MT in the circuit board 100M. Another part of the vertical support PIC (ie, the dummy support PIC2 ) passes through the layer stack S3 and stops at the base plate 100 . According to some embodiments, a chemical-mechanical planarization (CMP) process may be performed after the step of forming the vertical supporter PIC, so that the top surface of the vertical supporter PIC may be coplanar with the top surface of the insulation stack structure S4. Thereafter, a covering layer 203 may be formed over the vertical support PIC and the insulation stack structure S4, and the material of the covering layer 203 may include oxide.

According to an embodiment, the steps shown in Figure 7 can be continued from the steps shown in Figure 6A. After completing the steps shown in Figure 7, the steps shown in Figures 6B~6E can be performed. Steps 8~ The steps shown in Figure 11 can be continued from the steps shown in Figure 6E, but the invention is not limited thereto.

Please refer to Figure 7. After completing the steps shown in FIG. 6A (that is, after forming the ladder-like structure), a plurality of pillar elements 103 are formed in the array area AR. The plurality of pillar elements 103 may be dispersedly configured in the insulation stack structure S4 and the layer stack S3. A plurality of pillar elements 103 may be disposed on opposite sides of the lower isolation structure 105 . The pillar element 103 may extend along the first direction D1 through the insulation stack structure S4 and the layer stack S3. In one embodiment, forming the pillar element 103 may include the following steps. The insulating stack structure S4 and the layer stack S3 are patterned to form a plurality of holes 601 that are isolated from each other. For example, the insulating stack structure S4 and the layer stack S3 can be patterned by a photolithography process. The hole 601 extends downward along the first direction D1 and stops at the base plate 100; the hole 601 exposes the side walls of the insulation stack structure S4 and the layer stack S3 (also serving as the side walls of the hole 601), and exposes the base plate 100 (also serves as the side wall of the hole 601). The bottom of hole 601) is exposed. Then, the memory layer 121 can be lined in the hole 601 by a deposition process, and the bottom of the memory layer 121 can be removed by an etching process. The channel layer 122 may be deposited on the sidewalls of the memory layer 121 and contact the base plate 100 through the exposed bottom of the memory layer 121 . The insulating pillars 123 can fill the remaining space in the holes 601 through a deposition process. Then, part of the channel layer 122 and part of the insulating pillar 123 may be removed through an etching back process and/or a chemical mechanical planarization (CMP) process, and part of the sidewalls of the memory layer 121 may be exposed. Next, the pads 124 can be formed on the channel layer 122 and the insulating pillar 123 through a deposition process. By performing the steps described above in FIG. 7 , pillar elements 103 can be formed in the insulation stack structure S4 and the layer stack S3 .

The memory layer 121 may include a multilayer structure. For example, the memory layer 121 may include a tunnel layer disposed on the outer wall of the channel layer 122, and a storage layer disposed on the outer wall of the tunnel layer. storage layer), and a blocking layer disposed on the outer wall of the storage layer. In one embodiment, the memory layer 121 may include a multi-layer structure known in the field of memory technology, such as an ONO (Oxide-Nitride-Oxide) structure, ONONO (Oxide-Nitride-Oxide-Nitride- oxide) structure, ONONONO (oxide-nitride-oxide-nitride-oxide-nitride-oxide) structure, SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, BE- SONOS (bandgap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, TANOS (tantalum nitride-aluminum oxide-silicon nitride-silicon oxide-silicon) structure, MA BE-SONOS (metal-high dielectric Electric constant material energy band gap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure and its combination. Channel layer 122 may include a semiconductor material, such as a doped or undoped semiconductor material. In one embodiment, the channel layer 122 may include polysilicon, such as doped polysilicon or undoped polysilicon. Insulating pillars 123 may include oxides such as silicon oxide, or other suitable dielectric materials. The pad 124 may include a semiconductor material, such as a metal silicide, a doped semiconductor material, or an undoped semiconductor material. In one embodiment, the pads 124 may include polycrystalline silicon, such as doped polycrystalline silicon or undoped polycrystalline silicon.

Please refer to Figure 8. A plurality of slits 701 are formed in the insulation stack structure S4 and the layer stack S3. For example, the insulating stack structure S4 and the layer stack S3 may be etched to remove part of the insulating stack structure S4 and part of the layer stack S3 to form a slit 701 extending along the first direction D1. The etching is stopped when the etching process proceeds slightly beyond the lower surface 702b of layer stack S3. The slit 701 exposes the sidewalls of the insulation stack structure S4 and the layer stack S3 (also serving as the sidewalls of the slit 701 ), and exposes the base plate 100 (also serving as the bottom of the slit 701 ).

Please refer to Figure 9. The plurality of dielectric layers 302 in the insulating stack structure S4 and the layer stack S3 are replaced with conductive layers 102 . For example, an etching process may be performed through the slits 701 to remove the dielectric layers 302 in the insulation stack structure S4 and the layer stack S3 , thereby forming spaces between the insulation layers 101 . Afterwards, isolation element 106 is formed in slit 701 . It should be understood that although the step region SR is not shown in FIG. 9, the dielectric layer 302 and the slits 701 can continuously extend from the array region AR to the step region SR along the second direction D2. The dielectric layer 302 in the region SR is all replaced with the conductive layer 102 at the same time (that is, under the same process), as shown in Figures 2D to 2E.

The etching process used to remove the dielectric layer 302 does not remove the lower isolation structure 105 and the lower support 205 . In order to ensure that the lower isolation structure 105 and the lower support 205 are not removed during this etching process, the etch selectivity of the material of the lower isolation structure 105 and the lower support 205 may be different from the etch selectivity of the material of the dielectric layer 302 For example, in an etching process, the etching rate of the material of the dielectric layer 302 can be higher than the etching rate of the material of the lower isolation structure 105 and the lower support 205 ; by controlling the time during which the etching process is performed, the dielectric layer can be removed 302 and retain the lower isolation structure 105 and the lower support 205. In one embodiment, the lower isolation structure 105 separates the layer stack S3 into two parts that are isolated from each other. The layer stack S3 can be removed by etching through a plurality of slits 701 disposed on opposite sides of the lower isolation structure 105 . Dielectric layers 302 located on both sides of the lower isolation structure 105 .

Furthermore, after the dielectric layer 302 is removed, the spaces between the plurality of insulating layers 101 are filled with conductive material to form the conductive layer 102 between the plurality of insulating layers 101 . The dielectric layer 302 formed on the opposite sides of the lower isolation structure 105 (ie, the dielectric layer 302 in the layer stack S3) is replaced by a conductive material to form the conductive layer 102. The lower isolation structure 105 separates these conductive layers 102 to be electrically connected to each other. Sexually isolated conductive strips 131, 132. The conductive layer 102 may include conductive materials such as polysilicon or metal. In one embodiment, the conductive layer 102 may include tungsten (W). In one embodiment, at least part of the conductive layer 102 on the lower isolation structure 105 may serve as a gate. The above steps included in Figure 9 can be understood as a gate replacement process. After the conductive layer 102 is formed, a stacked structure S including a plurality of insulating layers 101 and a plurality of conductive layers 102 is formed.

After the conductive layer 102 is formed, the isolation film 141 is formed on the sidewall of the slit 701 , and the remaining space in the slit 701 is filled with the conductive film 142 . The isolation film 141 and the conductive film 142 may be formed by, for example, a deposition process. The isolation film 141 may include a dielectric material such as silicon dioxide. The conductive film 142 may include conductive materials such as polysilicon or metal. In one embodiment, the conductive film 142 may include tungsten.

During the gate replacement process, in the step region SR, since the lower support member 205 and the vertical support member PIC can still provide supporting force after forming the spaces between the plurality of insulating layers 101, the overall structure is not prone to collapse. In particular, compared with the comparative example without a lower support member, since the plurality of lower support members 205 of this embodiment are disposed in the gaps between the vertical support members PIC, more sufficient support force can be provided, corresponding to The insulating layer 101 in the gap between the vertical supports PIC and the subsequently replaced conductive layer 102 are less likely to deform.

Please refer to Figure 10. A plurality of upper isolation structures 104 are formed in the stacked structure S. The upper isolation structure 104 may be formed above the stacked structure S and passes through one or more insulating layers 101 and/or one or more conductive layers 102 in the stacked structure S along the first direction D1. For example, the stacked structure S can be etched to remove part of the stacked structure S to form a trench 901. The trench 901 extends downward along the first direction D1 and passes through one or more conductive layers 102 (for example, 3~3). 7 conductive layers 102) and then stop in the insulating layer 101. The trench 901 exposes part of the sidewalls of the stacked structure S (also serving as the sidewalls of the trench 901), and exposes the insulating layer 101 (also serving as the bottom of the trench 901); then, the upper isolation structure is exposed through a deposition process 104 is formed in trench 901. Upper isolation structure 104 may include oxide, or other suitable dielectric material. In the step region SR, the length of the upper isolation structure 104 in the second direction D2 is smaller than the length of the lower isolation structure 105 in the second direction D2, as shown in FIG. 1 .

Please refer to Figure 11. At least one first upper conductive structure 107 and at least one second upper conductive structure 108 are formed on the stacked structure S. The first upper conductive structure 107 and the second upper conductive structure 108 may extend along the third direction D3 and be staggered on the stacked structure S. The first upper conductive structure 107 and the second upper conductive structure 108 may include conductive materials such as metal.

In one embodiment, the manufacturing method may further include forming a plurality of tubular elements 109 . The formation of the tubular element 109 is illustrated below (not shown). More pillar elements 103 are formed in the step shown in Figure 7, some of which may be processed to form tubular elements 109 in the step shown in Figure 10. The post element 103 used to form the tubular element 109 may be formed where the upper isolation structure 104 is intended to be formed. In the steps shown in FIG. 10 , the formation of the upper isolation structure 104 may include etching the pillar element 103 used to form the tubular element 109 to remove the upper part of the pillar element 103 to form the tubular element 109 ; and then by The deposition process forms upper isolation structure 104 on tubular element 109 . The memory layer 151 of the tubular element 109 may comprise similar materials as the memory layer 121 of the pillar element 103 . The dummy channel layer 152 of the tubular element 109 may comprise similar materials as the channel layer 122 of the column element 103 . The insulating posts 153 of the tubular element 109 may comprise similar materials as the insulating posts 123 of the post element 103 .

In one embodiment, the memory device 10 as shown in Figures 1, 2A-2B, and 2D-2H can be obtained by performing the methods illustrated in Figures 3-11.

As shown in Figures 1 and 2A, the memory device 10 includes three upper isolation structures 104 and a lower isolation structure 105 between two isolation elements 106. However, the present invention is not limited thereto. The technology provided by the present invention The solution can be applied to memory devices including more or fewer upper isolation structures and/or lower isolation structures and/or pillar elements. Similarly, the number of lower supporting members 205 in this case is not limited to the number shown in FIG. 1 , but can be applied to a memory device including more or fewer lower supporting members.

The present invention provides a memory device including a lower support member and a manufacturing method thereof. Since the lower support members are provided in the stepped area of the memory device, the lower support members can be distributed in the gaps between the vertical support members. Therefore, compared with the comparative example without a lower support member, more supporting force can be provided. It can also prevent the insulating layer and the conductive layer from deforming or collapsing, so it can improve the yield of the process. In addition, since the lower support member and the lower isolation structure can be formed in the same process, there is no need to perform additional process steps to improve the support force, which greatly saves time and cost.

In summary, although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.

10,20,40,50: memory device 100: base plate 100u, 105u, 205u, 501u: upper surface 101:Insulation layer 102,202:Conductive layer 103: Column element 104: Upper isolation structure 105,205,1905,2005: Lower isolation structure 106:Isolation components 107: First upper conductive structure 108: Second upper conductive structure 109: Tubular components 121,151:Memory layer 122: Channel layer 123,153: Insulation column 124:pad 131,132,133,134,135,136,231,232,233,234: conductive strips 141:Isolation film 142:Conductive film 152: Dummy channel layer 161,162,163,164: Series selection transistor 165,166,167,168,265,266,267,268: Ground selection transistor 201: Insulating filler 203: Covering layer 205:Lower support 302: Dielectric layer 401,402,901,1201,1701:Trench 601,1401,100h: Hole 701,1501: slit 702b,1502b: Lower surface BL: bit line D1: first direction D2: second direction D3: Third direction GSL1, GSL2, GSL3, GSL4: Ground selection line M1, M2, M3, M4: memory cell series P1,P1-1,P2: Section line S, S2, S8, S9: stacked structure S3, S6: layer stacking S4, S7: Insulation stack structure SL: source line SSL1, SSL2, SSL3, SSL4: serial select line T1, T2: thickness WL: word line 100M: circuit board MT: control circuit C1: Insulating inner pad C2: conductive pillar PIC1: Functional support PIC2: Dummy support PICh: Vertical opening AR: array area COA: contact parts PIC: vertical support R1: The first area R2: Second area R3:The third area SR: Staircase area X,X’,X1,X1’,Y,Y’,Y1,Y1’,Y2,Y2’: hatch line endpoint

Figure 1 is a schematic top view of a memory device according to an embodiment of the present invention; Figure 2A is a schematic cross-sectional view of the memory device along the section line P1 in Figure 1; Figure 2B is a schematic cross-sectional view of the memory device along the section line P1-1 in Figure 1; Figure 2C is an equivalent circuit diagram of a memory device according to an embodiment of the present invention; Figure 2D is a schematic cross-sectional view of the memory device along the X-X’ section line in Figure 1; Figure 2E is a schematic cross-sectional view of the memory device along the Y-Y’ section line in Figure 1; Figure 2F is a schematic cross-sectional view of the memory device along the Y1-Y1' section line in Figure 1; Figure 2G is a schematic cross-sectional view of the memory device along the Y2-Y2’ section line in Figure 1; and Figures 3 to 11 illustrate a method for manufacturing a memory device according to an embodiment of the present invention.

10:Memory device

103: Column element

104: Upper isolation structure

105:Lower isolation structure

106:Isolation components

107: First upper conductive structure

108: Second upper conductive structure

109: Tubular components

205:Lower support

AR: array area

COA: contact parts

D1: first direction

D2: second direction

D3: Third direction

M1, M2, M3, M4: memory cell series

P1, P1-1: Section line

PIC: vertical support

R1: The first area

R2:Second area

R3: The third area

SR: Staircase area

X,X’,X1,X1’,Y,Y’,Y1,Y1’,Y2,Y2’: hatch line endpoint

Claims (10)

A memory device containing: A stacked structure including a plurality of conductive layers, wherein the stacked structure has an array area and a step area adjacent to the array area; A lower isolation structure is arranged in the stacked structure and has an upper surface located at the lower part of the stacked structure, wherein the lower isolation structure extends from the array area to the step area, and the lower isolation structure makes the conductive layers At least one conductive layer is separated into a first conductive strip and a second conductive strip, and the first conductive strip and the second conductive strip are electrically isolated from each other; Two memory cell series are arranged in the array area of the stacked structure and are electrically connected to the first conductive strip and the second conductive strip respectively; and At least one lower support member is disposed in the stepped area of the stacked structure, wherein the material of the at least one lower support member is the same as the material of the lower isolation structure, and the height of the at least one lower support member is the same as the height of the lower isolation structure. The memory device as described in claim 1 further includes: a base plate on which the stacking structure is disposed; a circuit board disposed under the base plate; and A plurality of vertical supports are arranged in the step area and pass through the stacked structure. A part of the vertical supports passes through the bottom plate and is electrically connected to the corresponding control circuit in the circuit board to form a plurality of functional Support members; the bottoms of the other part of the vertical support members stop at the bottom plate to form a plurality of dummy support members. The memory device of claim 2, wherein the number of the at least lower supporting members is plural, and the lower supporting members are disposed between the vertical supporting members. The memory device according to claim 2, further comprising a plurality of contacts arranged in the step area, the bottoms of the contacts are electrically connected to corresponding conductive layers of the conductive layers, and the contacts The top is electrically connected to the corresponding functional support member among the functional support members. The memory device of claim 1, further comprising an upper isolation structure disposed in the stacked structure, wherein the upper isolation structure extends along a first direction and makes at least one conductive layer disposed on the upper part of the stacked structure Separately, the upper isolation structure and the lower isolation structure at least partially overlap in the first direction. The memory device as claimed in claim 5, wherein the stepped area includes a first area, a second area and a third area, and the second area is disposed between the first area and the third area, and is adjacent to the first area. The third area is closer to the array area than the first area; The upper isolation structure extends from the array area along a second direction different from the first direction, passes through the third area of the step area and stays in the second area of the step area. The memory device of claim 6, further comprising a plurality of contacts arranged in the step area, the contacts being electrically connected to corresponding conductive layers of the conductive layers, wherein the at least one support member The number is a plurality, and the projected areas in the first direction of the contacts provided in the second area and the third area partially overlap with those provided in the second area and the third area. The projected area of the lower support member in the first direction; the projected area of the contact members disposed in the first region in the first direction is separated from the lower support members disposed in the first region The projected area in the first direction. The memory device of claim 6, wherein the lower isolation structure extends from the array area along the second direction and passes through the third area, the second area and the first area of the step area. A method of manufacturing a memory device, including: Forming a layer stack on a base plate along a first direction, wherein the layer stack includes an array area and a step area adjacent to the array area; A lower isolation structure and at least a lower support member are formed in the layer stack, and the lower isolation structure and the at least lower support member extend downward toward the base plate, wherein the lower isolation structure extends from the array area along a direction different from the first direction. A second direction extends to the step area, the at least lower support member is formed in the step area, the material of the at least lower support member is the same as the material of the lower isolation structure, and the height of the at least lower support member is the same as the lower isolation structure. the height of the lower isolation structure; and An insulation stack structure is formed on the layer stack, wherein the lower isolation structure and the at least lower support member are located under the insulation stack structure. The method of manufacturing a memory device as claimed in claim 9, wherein the step of forming a stack on a base plate further includes: Forming a plurality of insulating layers and a plurality of dielectric layers that are staggered and stacked along the first direction; The lower isolation structure separates at least one of the insulating layers and at least one of the dielectric layers into two parts that are isolated from each other.