TWI790122B - Semiconductor structure - Google Patents

Abstract

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a conductive pillar having a sidewall and a multi-layer isolation structure on the sidewall of the conductive pillar. The multi-layer isolation structure includes a first isolation layer and a second isolation layer. The first isolation layer is between the conductive pillar and the second isolation layer. The first isolation layer includes protrusions extending toward the second isolation layer. A density of the first isolation layer is different from that of the second isolation layer.

Description

semiconductor structure

The present invention relates to semiconductor structures and methods of fabrication thereof, and more particularly to semiconductor structures including multilayer isolation structures and methods of fabrication thereof.

With the advancement of semiconductor technology, the size of semiconductor structures has been gradually reduced in recent years. However, shrinking the size of the semiconductor structure will lead to increased interference between devices in the semiconductor structure, and may degrade the electrical performance of the semiconductor structure. Therefore, in order to meet the market demand for high-performance, economical and reliable semiconductor structures, it is very important to reduce the size of semiconductor structures while maintaining their electrical properties.

The invention relates to a semiconductor structure and a manufacturing method thereof.

According to one aspect of the present invention, a semiconductor structure is provided, which includes a conductive column having a sidewall, and a multi-layer isolation structure disposed on the sidewall of the conductive column. The multi-layer isolation structure includes a first isolation layer and a second isolation layer. The first isolation layer is between the conductive column and the second isolation layer. The first isolation layer includes a plurality of protrusions extending toward the second isolation layer. The density of the first isolation layer is different from the density of the second isolation layer.

According to another aspect of the present invention, a semiconductor structure is provided, which includes a conductive pillar having a sidewall, and a multi-layer isolation structure disposed on the sidewall of the conductive pillar. The multi-layer isolation structure includes N isolation layers, where N is one of positive integers greater than 3. The N isolation layers include a first isolation layer to an Nth isolation layer arranged in sequence in a direction away from the conductive pillar. The density of the first isolation layer is smaller than that of other isolation layers among the isolation layers.

According to yet another aspect of the present invention, a method for fabricating a semiconductor structure is provided, which includes the following steps. form a stacked structure. A multi-layer isolation structure is formed in a stacked structure. The step of forming a multi-layer isolation structure in the stack structure includes: forming a second isolation layer in the stack structure through deposition and etching steps; and forming a first isolation layer on the second isolation layer through another deposition process.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given in detail with the accompanying drawings as follows:

10:Semiconductor structure

100:Stack structure

101: Conductive layer

102: Insulation layer

103: Semiconductor layer

104:Semiconductor device

105: column element

106: Channel structure

106b: end of lower channel

107: protective layer

115: Conductive column

115s: side wall

116,216: Multi-layer isolation structure

117: memory film

118: vertical channel membrane

119: Insulation column

120: Pad

121: Upper conductive part

122: lower conductive part

122a: upper end

122b: lower end

123,223: first isolation layer

123b: bottom surface

123p: convex part

124,224: second isolation layer

124b: bottom surface

124r: alcove

205: column element

225: The third isolation layer

300: insulation stack structure

301: sacrificial layer

310: Semiconductor Material Stacking

311: the first semiconductor material layer

312: The first interlayer insulating layer

313: second semiconductor material layer

314: The second interlayer insulating layer

315: the third semiconductor material layer

320: Groove

330: opening

411, 412, 413: insulating film

520: slit

611: the fourth semiconductor material layer

920: space

1020: Groove

1020r, 1120r: alcove

1124: isolation material layer

1224: dense isolation material layer

X, Y, Z: direction

Figure 1 shows a semiconductor structure according to an embodiment of the present invention; Figure 2 shows a semiconductor structure according to another embodiment of the present invention; and Figures 3 to 16 show a semiconductor structure according to an embodiment of the present invention A method for fabricating a semiconductor structure.

The relevant embodiments are provided below, and the semiconductor structure and its manufacturing method proposed by the present invention are described in detail in conjunction with the drawings. However, the present invention is not limited thereto. The descriptions in the embodiments, such as the detailed structure, steps of the manufacturing method and application of materials, etc., are for illustration purposes only, and the protection scope of the present invention is not limited to the above-mentioned aspects.

At the same time, it should be noted that not all possible embodiments of the present invention are presented. Those skilled in the art may change and modify the structures and manufacturing methods of the embodiments without departing from the spirit and scope of the present invention, so as to meet the needs of practical applications. Therefore, other implementation aspects not proposed in the present invention may also be applicable. Furthermore, the drawings are simplified to clearly illustrate the content of the embodiments, and the size ratios in the drawings are not drawn according to the proportion of the actual product. In the drawings, the same or similar element symbols are used to represent the same or similar elements.

Furthermore, the ordinal numbers used in the specification and claims, such as "first", "second", and "third", are used to modify elements, which do not imply and represent that the element has any previous ordinal numbers. , nor does it represent the order of a certain element with another element, or the order of the manufacturing method. clearly distinguish.

Embodiments of the present invention are applicable to various three-dimensional (3D) stacked semiconductor structures. For example, the embodiments can be applied to three-dimensional vertical channel (VC) NAND memory devices, or other types of memory devices.

Please refer to Figure 1. FIG. 1 schematically illustrates a semiconductor structure 10 according to an embodiment of the present invention. The semiconductor structure 10 may include a stack structure 100 , a semiconductor layer 103 , a semiconductor device 104 , at least one pillar element 105 , and at least one channel structure 106 .

The stack structure 100 may include a plurality of conductive layers 101 and a plurality of insulating layers 102 stacked alternately along the Z direction. The conductive layer 101 and the insulating layer 102 may extend in the X direction and/or the Y direction, and the X direction, the Y direction and the Z direction may be perpendicular to each other. The plurality of conductive layers 101 isolates the plurality of insulating layers 102 from each other.

The semiconductor layer 103 may be located under the stack structure 100 . The semiconductor device 104 can be located under the semiconductor layer 103 . In an embodiment, the stacked structure 100 , the semiconductor layer 103 and the semiconductor device 104 may overlap each other in the Z direction. The semiconductor device 104 may include active devices and/or passive devices. Active devices may, for example, include transistors, diodes, and the like. Transistors may, for example, include N-type metal-oxide-semiconductor field-Effect transistors (N-type metal-oxide-semiconductor field-Effect transistors; NMOS), P-type metal-oxide-semiconductor field-effect transistors (P-type metal-oxide- semiconductor field-effect transistor (PMOS), complementary metal-oxide-semiconductor field-effect transistor (complementary metal-oxide-semiconductor field-effect transistor; CMOS), bipolar junction transistor (bipolar junction transistor; BJT), etc. Passive devices may include resistors, capacitors and/or inductors.

At least one column element 105 and at least one channel structure 106 are dispersedly disposed in the stack structure 100 and the semiconductor layer 103 . Column element 105 may contain a The conductive pillar 115 on the sidewall 115s, and the multi-layer isolation structure 116 disposed on the sidewall 115s of the conductive pillar 115 . The conductive pillar 115 can extend along the Z direction and penetrate through the stack structure 100 . The conductive pillar 115 can be electrically connected to the semiconductor layer 103 .

The conductive column 115 may include an upper conductive portion 121 and a lower conductive portion 122 below the upper conductive portion 121 . In an embodiment, the upper conductive portion 121 may gradually narrow downward along the Z direction. In one embodiment, the upper conductive portion 121 may have a transverse cross-sectional dimension (such as a transverse cross-sectional dimension on the X-Y plane) that gradually decreases from the top surface of the upper conductive portion 121 to the bottom surface of the upper conductive portion 121 along the Z direction. . However, the present disclosure is not limited thereto, and the upper conductive portion 121 may also have other suitable shapes. The lower conductive portion 122 may extend along the Z direction and penetrate through the stack structure 100 . The lower conductive portion 122 may have an upper end portion 122 a connected to the upper conductive portion 121 and a lower end portion 122 b opposite to the upper end portion 122 a. The upper end portion 122 a of the lower conductive portion 122 may be located in the stack structure 100 . The lower end portion 122 b of the lower conductive portion 122 may be located below the stacked structure 100 and located in the semiconductor layer 103 .

The multilayer isolation structure 116 may penetrate the stacked structure 100 . The multi-layer isolation structure 116 may include a first isolation layer 123 and a second isolation layer 124 . The first isolation layer 123 is interposed between the conductive pillar 115 and the second isolation layer 124 . The lower end 122b of the lower conductive portion 122 may be located below the bottom surface 124b of the second isolation layer 124 . The bottom surface 124b of the second isolation layer 124 may be located below the bottom surface 123b of the first isolation layer 123 . The first isolation layer 123 may include a plurality of protrusions 123p disposed at intervals and extending laterally toward the second isolation layer 124 . The plurality of protrusions 123p may be respectively disposed between the plurality of insulating layers 102 in the stack structure 100 . The plurality of protrusions 123p may correspond to stacked junctions A plurality of conductive layers 101 in the structure 100 are provided. For example, positions (eg, heights) of the plurality of protrusions 123p in the Z direction may respectively correspond to the plurality of conductive layers 101 , and each protrusion 123p extends laterally toward the corresponding conductive layer 101 .

In one embodiment, the density of the first isolation layer 123 may be different from the density of the second isolation layer 124 . For example, the density of the first isolation layer 123 may be smaller than that of the second isolation layer 124 .

The channel structure 106 can extend along the Z direction and penetrate through the stack structure 100 . The channel structure 106 may have a lower channel end 106b. The lower channel end 106 b of the channel structure 106 may be below the bottom surface 124 b of the second isolation layer 124 and/or the lower end 122 b of the lower conductive portion 122 . The channel structure 106 may include a memory film 117 , a vertical channel film 118 , insulating pillars 119 and pads 120 . The memory film 117 may surround the vertical channel film 118 . In one embodiment, the memory film 117 may surround a portion of the vertical channel film 118 . For example, as shown in FIG. 1 , in the semiconductor layer 103 , a portion of the vertical channel film 118 may not be surrounded by the memory film 117 , through which current can flow between the channel structure 106 and the semiconductor layer 103 . The channel structure 106 can be electrically connected to the semiconductor layer 103 and electrically connected to the conductive pillar 115 . The vertical channel film 118 is disposed between the memory film 117 and the insulating pillar 119 . The vertical channel film 118 may have a tubular shape and surround the insulating post 119 . In one embodiment, the vertical channel membrane 118 may have a tube shape with one end closed and one end open. The pad 120 is disposed on the vertical channel film 118 and the insulating column 119 and can be surrounded by the memory film 117 . The vertical channel film 118 can be used to provide a channel for electrons or holes when a voltage is applied to the semiconductor structure 10 .

The semiconductor structure 10 may include a plurality of memory cells disposed in the stack structure 100 . The memory cells can be defined in the memory film 117 where the conductive layer 101 intersects with the vertical channel film 118 of the channel structure 106 .

The semiconductor structure 10 may further include a passivation layer 107 disposed between the multilayer isolation structure 116 and the semiconductor layer 103 .

In one embodiment, the conductive layer 101 may serve as a word line (WL), and the conductive pillar 115 may serve as a source line (SL), such as a common source line (SL).

As shown in Figure 1, the semiconductor structure 10 includes two isolation layers (the first isolation layer 123 and the second isolation layer 124), but the present invention is not limited thereto, and the technical solution provided by the present invention can be applied to include two The semiconductor structure of the isolation layer above. In one embodiment, the technical solution provided by the present invention can be applied to a semiconductor structure including three isolation layers, and the formed semiconductor structure 20 can be as shown in FIG. 2 .

Please refer to Figure 2. The semiconductor structure 20 can include at least one pillar element 205 disposed in the stack structure 100 . The post element 205 may include a conductive post 115 and a multi-layer isolation structure 216 disposed on the sidewall 115 s of the conductive post 115 . The multi-layer isolation structure 216 may include a first isolation layer 223 , a second isolation layer 224 and a third isolation layer 225 . The first isolation layer 223 is interposed between the conductive pillar 115 and the second isolation layer 224 . The second isolation layer 224 is interposed between the first isolation layer 223 and the third isolation layer 225 . The first isolation layer 223 may be similar to the first isolation layer 123 of the semiconductor structure 10 . The second isolation layer 224 may be similar to the second isolation layer 124 of the semiconductor structure 10 . In one embodiment, the density of the first isolation layer 223 may be different from the density of the second isolation layer 224 degree and/or the density of the third isolation layer 225. For example, the density of the first isolation layer 223 may be less than that of the second isolation layer 224 , and/or the density of the first isolation layer 223 may be less than that of the third isolation layer 225 .

3 to 16 schematically illustrate a method for fabricating a semiconductor structure according to an embodiment of the present invention.

Please refer to Figure 3. An insulating stack structure 300 , a semiconductor material stack 310 and a semiconductor device 104 are provided. The insulating stack structure 300 may be formed on a semiconductor material stack 310 . A semiconductor material stack 310 may be formed on the semiconductor device 104 .

The semiconductor material stack 310 may include a first semiconductor material layer 311, a first interlayer insulating layer 312, a second semiconductor material layer 313, a second interlayer insulating layer 314, and a third semiconductor material layer stacked from bottom to top along the Z direction. material layer 315 . In one embodiment, the first semiconductor material layer 311, the second semiconductor material layer 313, and the third semiconductor material layer 315 may include doped or undoped semiconductor materials, such as doped or undoped Undoped polysilicon (polysilicon). The first interlayer insulating layer 312 and the second interlayer insulating layer 314 may include insulating materials, and the insulating materials include oxides, such as silicon oxide. In one embodiment, the first semiconductor material layer 311, the first interlayer insulating layer 312, the second semiconductor material layer 313, the second interlayer insulating layer 314, and the third semiconductor material layer 315 can be sequentially deposited to form a semiconductor device. A semiconductor material stack 310 is formed on 104, for example, by chemical vapor deposition (CVD).

The insulating stack structure 300 may include a plurality of sacrificial layers 301 and a plurality of insulating layers 102 stacked alternately along the Z direction. The sacrificial layer 301 and the insulating layer 102 can extend in the X direction and/or the Y direction. The plurality of sacrificial layers 301 isolates the plurality of insulating layers 102 from each other. In one embodiment, the sacrificial layer 301 of the insulating stack structure 300 may include an insulating material, and the insulating material includes nitride, such as silicon nitride. The insulating layer 102 of the insulating stack structure 300 may include an insulating material, and the insulating material includes an oxide, such as silicon oxide. In one embodiment, the sacrificial layer 301 and the insulating layer 102 may comprise different materials. In one embodiment, the insulating stack structure 300 can be formed on the semiconductor material stack 310 by sequentially depositing the insulating layer 102 and the sacrificial layer 301 .

At least one channel structure 106 can be formed in the insulating stack structure 300 . The channel structure 106 can extend along the Z direction and penetrate through the insulating stack structure 300 , the third semiconductor material layer 315 , the second interlayer insulating layer 314 , the second semiconductor material layer 313 and the first interlayer insulating layer 312 . The lower channel end 106b of the channel structure 106 may be located in the first semiconductor material layer 311 . The channel structure 106 may include a memory film 117 , a vertical channel film 118 , insulating pillars 119 and pads 120 .

The memory film 117 may comprise a multilayer structure (multilayer structure) known in the field of memory technology, such as ONO (oxide-nitride-oxide) structure, ONONO (oxide-nitride-oxide-nitride-oxide ) structure, ONONONO (oxide-nitride-oxide-nitride-oxide-nitride-oxide) structure, SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, BE-SONOS ( Band gap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, TANOS (tantalum nitride-alumina-silicon nitride-silicon oxide-silicon) structure, MA BE-SONOS (gold Genus-high dielectric constant material energy bandgap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure and its combination.

The vertical channel film 118 may include doped or undoped semiconductor material, such as doped polysilicon or undoped polysilicon. The insulating pillar 119 may include a dielectric material including an oxide (eg, silicon oxide). The pad 120 may include doped or undoped semiconductor material, such as doped polysilicon or undoped polysilicon.

In one embodiment, the formation of the channel structure 106 may include the following steps: performing a patterning process on the insulating stack structure 300 to form at least one opening 330 in the insulating stack structure 300 . For example, the insulating stack structure 300 can be patterned by a photolithography process. The opening 330 can extend downward along the Z direction, through the insulating stack structure 300 , the third semiconductor material layer 315 , the second interlayer insulating layer 314 , the second semiconductor material layer 313 and the first interlayer insulating layer 312 , and stop at In the first semiconductor material layer 311; the first semiconductor material layer 311 can be regarded as an etch stop layer. Next, the memory film 117 , the vertical channel film 118 , the insulating column 119 and the pad 120 are sequentially deposited in the opening 330 to form the channel structure 106 .

A patterning process is performed on the insulating stack structure 300 to form at least one trench 320 in the insulating stack structure 300 . For example, the insulating stack structure 300 can be patterned by a lithography process. The trench 320 may extend downward along the Z direction, pass through the insulating stack structure 300 and stop at the second interlayer insulating layer 314 . The trench 320 makes the sidewall of the insulating stack structure 300 and the sidewall of the third semiconductor material layer 315 (same as Also as the sidewall of the trench 320 ), and part of the upper surface of the second interlayer insulating layer 314 (also as the bottom of the trench 320 ) is exposed. In one embodiment, the trench 320 can be formed by two etching steps with different etching selectivities; for example, the first etching step with a lower etching selectivity can be performed first to form the trench 320 in the insulating stack structure 300 At this time, the trench 320 extends downward along the Z direction, penetrates the insulating stack structure 300 and stops at the third semiconductor material layer 315, and the third semiconductor material layer 315 can be regarded as an etch stop layer. At this time, the trench 320 The bottom part of the third semiconductor material layer 315 is partially exposed; then, a second etching step with higher etching selectivity is performed so that the trench 320 extends downward along the Z direction, and part of the third semiconductor material layer is removed. After 315, part of the upper surface of the second interlayer insulating layer 314 is exposed to form the trench 320 as shown in FIG. In this embodiment, two etching steps with different etch selectivities are used to form the trench 320 to help precisely control the profile of the trench 320 and ensure that the trench 320 stops at a desired position.

Please refer to Figure 4. An insulating film 411 , an insulating film 412 and an insulating film 413 are formed on the sidewalls of the trench 320 shown in FIG. 3 and the upper surface of the insulating stack structure 300 . For example, the insulating film 411 may be formed on the upper surface of the insulating stacked structure 300 and lined in the trench 320 by a deposition process, and then part of the insulating film on the bottom of the trench 320 may be removed by an etching step. 411; then, an insulating film 412 may be formed on the insulating film 411 by a deposition process, and then part of the insulating film 412 on the bottom of the trench 320 may be removed by an etching step; then, an insulating film 413 may be formed by a deposition process On the insulating film 412, the groove is removed by an etching step Part of the insulating film 413 on the bottom of the trench 320 , at this time, the bottom of the trench 320 can expose part of the second interlayer insulating layer 314 . The insulating film 411 may include an insulating material, and the insulating material includes nitride, such as silicon nitride. The insulating film 412 may include an insulating material, and the insulating material includes an oxide, such as silicon oxide. The insulating film 413 may include an insulating material, and the insulating material includes nitride, such as silicon nitride.

Please refer to Figure 5. An etching step may be performed to remove part of the second interlayer insulating layer 314 and the second semiconductor material layer 313 through the trench 320 to form the slit 520 . The slit 520 is between the first insulating interlayer 312 and the second insulating interlayer 314 . This etching step can substantially remove the second semiconductor material layer 313 without removing the first semiconductor material layer 311 below the first interlayer insulating layer 312 and the third semiconductor material layer 315 above the second interlayer insulating layer 314 . The slit 520 exposes a portion of the sidewall of the channel structure 106 . Specifically, the slit 520 exposes part of the sidewall of the memory film 117 of the channel structure 106 .

Please refer to Figure 6. One or more etching steps may be performed to remove the first insulating interlayer 312 , the second insulating interlayer 314 , the insulating film 412 and the insulating film 413 . In one embodiment, the one or more etching steps may remove a portion of the memory film 117 of the channel structure 106 . In one embodiment, part of the insulating film 411 on the insulating stack structure 300 may be removed, and part of the insulating film 411 on the sidewall of the trench 320 may be retained. For example, a portion of the insulating film 411 on the insulating stack structure 300 can be removed by chemical-mechanical planarization and/or etching.

Please refer to Figure 7. The fourth semiconductor material layer 611 may be formed between the first semiconductor material layer 311 and the third semiconductor material layer 315 by a deposition process. In one embodiment, the fourth semiconductor material layer 611 can connect or contact the memory film 117 , the vertical channel film 118 , the first semiconductor material layer 311 and the third semiconductor material layer 315 . In one embodiment, the fourth semiconductor material layer 611 may include doped or undoped semiconductor material, such as doped or undoped polysilicon. The first semiconductor material layer 311 , the fourth semiconductor material layer 611 and the third semiconductor material layer 315 can form the semiconductor layer 103 . The semiconductor layer 103 may include doped or undoped semiconductor material, such as doped or undoped polysilicon.

Please refer to Figure 8. An etching step may be performed to remove the remaining insulating film 411 and form the protective layer 107 on the bottom and part of the sidewalls of the trench 320 . The passivation layer 107 can cover the semiconductor layer 103 exposed by the trench 320 . In one embodiment, the passivation layer 107 can cover the sidewall of the bottommost insulating layer 102 in the insulating stack structure 300 . In one embodiment, the passivation layer 107 may include an insulating material, and the insulating material includes oxide, such as silicon oxide.

Please refer to Figure 9. An etching step may be performed through the trenches 320 to remove the sacrificial layer 301 of the insulating stack structure 300 to form a plurality of spaces 920 between the insulating layers 102 . During this etching step, the protection layer 107 can protect the semiconductor layer 103 to prevent the semiconductor layer 103 from being removed during the etching step. In one embodiment, the etching step may include wet etching, such as using phosphoric acid (H ₃ PO ₄ ) or other suitable chemicals.

Please refer to Figure 10. The plurality of spaces 920 are filled with conductive material to form a plurality of conductive layers 101 between the plurality of insulating layers 102 . In this way, the stack structure 100 and the trench 1020 in the stack structure 100 are formed. The trench 1020 may include a plurality of recesses 1020r between the insulating layers 102 extending into the conductive layer 101 along the X-direction and/or the Y-direction.

In one embodiment, the steps included in FIGS. 9-10 can be understood as a gate replacement process. In one embodiment, the conductive layer 101 may include a conductive material, such as tungsten (W).

Please refer to Figure 11. The trench 1020 may be lined with a layer of isolation material 1124 by a deposition process. The isolation material layer 1124 may be deposited along the sidewalls of the alcove 1020r to form a plurality of alcoves 1120r respectively corresponding to the alcoves 1020r. The isolation material layer 1124 can cover the sidewalls of the conductive layer 101 and the insulating layer 102 of the stack structure 100 exposed by the trench 1020 . In one embodiment, the isolation material layer 1124 may include oxide, such as low temperature oxide (LTO).

Please refer to Figure 12. A heat treatment step is performed on the isolation material layer 1124 of FIG. 11 to densify the isolation material layer 1124 . After the heat treatment step, the layer of isolation material 1124 is transformed into a layer of dense isolation material 1224 . In one embodiment, the heat treatment step may be a rapid thermal process (RTP), and is performed at 800-900° C. for about 25-35 seconds. In one embodiment, the rapid thermal processing step may be performed at about 850° C. for about 30 seconds. The heat treatment step can also be understood as a densification treatment, through which the isolation material layer 1124 can be made denser. dense septum The layer of release material 1224 may be denser than the layer of isolation material 1124 . The density of the dense isolation material layer 1224 may be greater than the density of the isolation material layer 1124 .

Please refer to Figure 13. An etching step is performed on the dense isolation material layer 1224 to form the second isolation layer 124 penetrating through the stack structure 100 . In one embodiment, the etching step can remove part of the dense isolation material layer 1224 along the sidewall of the trench 1020 , so that the thickness of the dense isolation material layer 1224 is reduced. The etching step will also remove part of the dense isolation material layer 1224 in the recess 1020r, thereby forming a second isolation layer 124 comprising a plurality of recesses 124r (it can also be understood that the etching step makes the recess 1120r in Figure 12 larger become alcove 124r). The plurality of alcoves 124 r of the second isolation layer 124 correspond to the plurality of conductive layers 101 of the stacked structure 100 . Each alcove 124r can extend laterally toward the corresponding conductive layer 101 . In one embodiment, the second isolation layer 124 may include oxide, such as low temperature oxide. In one embodiment, the second isolation layer 124 may include dense low temperature oxide.

In one embodiment, performing the heat treatment step before the etching step helps to reduce the etching rate of the etching step to improve the etching controllability and obtain a more accurate etching profile. However, in another embodiment, the heat treatment step on the isolation material layer 1124 can be omitted, and the second isolation layer 124 can be formed by performing an etching step on the isolation material layer 1124 . Whether to perform the heat treatment step on the isolation material layer 1124 may depend on the material properties of the isolation material layer 1124 and/or the design of the semiconductor structure. For example, in the case that the isolation material layer 1124 includes a dense material, or the etching rate of the isolation material layer 1124 is low, the heat treatment step for the isolation material layer 1124 may be omitted.

Please refer to Figure 14. A deposition process may be performed to form the first isolation layer 123 penetrating through the stack structure 100 on the second isolation layer 124 .

Please refer to Figure 15. An etching step may be performed to remove portions of the first isolation layer 123 , the second isolation layer 124 and the protective layer 107 at the bottom of the trench 1020 and expose the semiconductor layer 103 . In this way, the multi-layer isolation structure 116 including the first isolation layer 123 and the second isolation layer 124 is formed. The first isolation layer 123 may include a plurality of protrusions 123p. The protrusions 123p of the first isolation layer 123 are formed in the plurality of recesses 124r of the second isolation layer 124 . The density of the first isolation layer 123 may be different from that of the second isolation layer 124 , so that an interface is formed between the first isolation layer 123 and the second isolation layer 124 . For example, the density of the first isolation layer 123 may be smaller than that of the second isolation layer 124 . In one embodiment, the formation of the second isolation layer 124 includes a heat treatment step (as shown in FIG. 12 ), and the heat treatment step makes the second isolation layer 124 denser than the first isolation layer 123 . In one embodiment, the first isolation layer 123 may include oxide, such as low temperature oxide.

Please refer to Figure 16. Conductive pillars 115 are formed to fill trenches 1020 . The formation of the conductive pillar 115 may include, for example, performing a deposition process to form the lower conductive portion 122 on the sidewall of the first isolation layer 123 , and performing another deposition process to form the upper conductive portion 121 on the lower conductive portion 122 . In one embodiment, the formation of the conductive pillar 115 may further include removing part of the first isolation layer 123, part of the second isolation layer 124, and/or part of the uppermost insulating layer 102 in the stacked structure 100, so as to The upper conductive portion 121 is gradually narrowed downward along the Z direction. In one embodiment, the upper conductive portion 121 may include metal material such as tungsten; the lower conductive portion 122 may include doped or undoped semiconductor Bulk materials such as doped or undoped polysilicon. In another embodiment, both the upper conductive portion 121 and the lower conductive portion 122 may include a metal material, such as tungsten. In one embodiment, the semiconductor structure 10 as shown in FIG. 1 can be obtained by implementing the methods exemplarily shown in FIGS. 3-16 .

As shown in Figures 3-16, the method for manufacturing a semiconductor structure provided by the present invention can be applied to form a semiconductor structure comprising two isolation layers, but the present invention is not limited thereto, and the technical solution provided by the present invention can also be Applied to the formation of semiconductor structures including more than two isolation layers. In one embodiment, the technical solution provided by the present invention can be applied to a semiconductor structure including N isolation layers (that is, the multilayer isolation structure of the semiconductor structure includes N isolation layers), where N is one of positive integers greater than or equal to 2 .

When N is 2, the multilayer isolation structure of the semiconductor structure includes two isolation layers, and its manufacturing method and formed semiconductor structure can be shown in FIGS. 3-16.

When N is 3, the multilayer isolation structure of the semiconductor structure comprises three isolation layers, and the difference between the manufacturing method and the manufacturing method used to manufacture the semiconductor structure comprising two isolation layers is that the method further includes before forming the second isolation layer , forming a third isolation layer between the second isolation layer and the stack structure; wherein the forming step of the third isolation layer can be similar to the forming step of the second isolation layer. That is, the formation of the third isolation layer may include depositing an isolation material layer, and performing a heat treatment step and an etching step on the isolation material layer (the heat treatment step is optional). The formed third isolation layer may be similar to the second isolation layer. The density of the first isolation layer may be less than that of the second isolation layer, and/or the density of the first isolation layer may be less than that of the third isolation layer. density. The density of the second isolation layer may be the same as or different from that of the third isolation layer. The third isolation layer may include oxide, such as low temperature oxide or dense low temperature oxide. The semiconductor structure formed by this manufacturing method can be the semiconductor structure 20 shown in FIG. 2 .

When N is one of the positive integers greater than or equal to 3, the multilayer isolation structure of the semiconductor structure includes N isolation layers, and the N isolation layers include a first isolation layer and a second isolation layer arranged in sequence in a direction away from the conductive pillar , ..., the Nth isolation layer, wherein the density of the first isolation layer is smaller than that of other isolation layers (ie, the second isolation layer to the Nth isolation layer) among the isolation layers. The method for manufacturing a semiconductor structure may include: sequentially forming an Nth isolation layer, an N-1th isolation layer, ..., a second isolation layer, and a first isolation layer in a stacked structure, wherein the The formation steps of the isolation layer other than the isolation layer can be similar to the formation steps of the second isolation layer 124 described in Figures 11-13, and the formation steps of the first isolation layer can be similar to the first isolation layer described in Figure 14 123 formation steps.

In a comparative example, a single-layer isolation structure is used to isolate the conductive pillars and stacked structures in the semiconductor structure. The material filling property of the single-layer isolation structure is poor, and multiple voids are likely to be generated during the formation process. Voids in the isolation structure reduce the isolation effect of the conductive pillars and stack structures, and degrade the electrical performance of the semiconductor structure. Specifically, the material of the conductive layer will infiltrate into multiple pores of the single-layer isolation structure, thereby forming a leak path between the conductive pillar and the conductive layer of the stacked structure, and the leak path will interfere with the operation of the semiconductor structure, resulting in Ion current is difficult to detect and degrades the electrical performance of semiconductor structures.

The semiconductor structure provided by the present invention includes a multi-layer isolation structure between the conductive pillar and the stack structure. Compared with the semiconductor structure including the single-layer isolation structure of the comparative example, the multi-layer isolation structure of the present invention has better filling property and fewer pores. Through such a configuration, the leakage problem caused by the material of the conductive layer penetrating into the pores can be reduced or solved, the ion flow can be detected, and the electrical performance of the semiconductor structure can be improved and the yield can be improved. In addition, in the multi-layer isolation structure provided by the present invention, the properties (such as density) and profiles of the plurality of isolation layers (eg, the first isolation layer includes a plurality of protrusions extending toward the corresponding conductive layer, and/or the second isolation layer layer comprising a plurality of cavities extending towards the corresponding conductive layer) also helps to further improve the fillability. Furthermore, in the manufacturing method of the semiconductor structure provided by the present invention, the formation of the multilayer isolation structure includes the steps of deposition, etching, and redeposition, which help to form a good profile of the isolation layer and reduce the number of pores in the isolation layer.

It should be noted that the above-mentioned drawings, structures and steps are used to describe some embodiments or application examples of the present invention, and the present invention is not limited to the scope and application of the above-mentioned structures and steps. Other embodiments with different structural forms, such as known components of different internal components, can be used, and the structure and steps of the example can be adjusted according to the actual application requirements. Therefore, the structures in the drawings are only used for illustration rather than to limit the present invention. Those with ordinary knowledge should know that the relevant structures and steps of the application of the present invention, such as the arrangement or configuration of the relevant elements and layers in the semiconductor structure, or the details of the manufacturing steps, etc., may vary according to the requirements of the actual application. Adjust and change accordingly.

To sum up, although the present invention has been disclosed by the above embodiments, they are not intended to limit the present invention. Those skilled in the technical field of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

10:Semiconductor structure

100:Stack structure

101: Conductive layer

102: Insulation layer

103: Semiconductor layer

104:Semiconductor device

105: column element

106: Channel structure

107: protective layer

115: Conductive column

115s: side wall

116: Multi-layer isolation structure

117: memory film

118: vertical channel membrane

119: Insulation column

120: Pad

121: Upper conductive part

122: lower conductive part

122a: upper end

122b: lower end

123: The first isolation layer

123b: bottom surface

123p: convex part

124: second isolation layer

124b: bottom surface

X, Y, Z: direction

Claims (6)

A semiconductor structure, comprising: a conductive pillar with a sidewall; and a multilayer isolation structure disposed on the sidewall of the conductive pillar, the multilayer isolation structure includes a first isolation layer and a second isolation layer, wherein the first isolation layer An isolation layer is interposed between the conductive column and the second isolation layer, the first isolation layer includes a plurality of protrusions extending toward the second isolation layer, and the density of the first isolation layer is smaller than that of the second isolation layer. The density of the isolation layer. The semiconductor structure of claim 1, wherein the first isolation layer and the second isolation layer comprise low temperature oxide. The semiconductor structure as described in Claim 1 further includes a stack structure, the multi-layer isolation structure is disposed in the stack structure, the stack structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately, wherein the first isolation layer The protrusions correspond to the conductive layers. The semiconductor structure as described in claim 3, further comprising a channel structure and a semiconductor layer, the channel structure is disposed in the stack structure, the semiconductor layer is located below the stack structure, wherein the channel structure is electrically connected through the semiconductor layer on the conductive column. The semiconductor structure according to claim 1, wherein the conductive column includes an upper conductive portion and a lower conductive portion below the upper conductive portion, the upper conductive portion includes a metal material, and the lower conductive portion includes a semiconductor material. A semiconductor structure comprising: A conductive column with a side wall; and a multilayer isolation structure disposed on the side wall of the conductive column, the multilayer isolation structure includes N isolation layers, wherein N is one of positive integers greater than 3, and the isolation layers It includes a first isolation layer to an Nth isolation layer sequentially arranged in a direction away from the conductive column, and the density of the first isolation layer is smaller than that of other isolation layers in the isolation layers.

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