TW202228249A - Memory device and method for manufacturing the same - Google Patents

Abstract

A method for manufacturing a memory device is provided. The method includes: providing a stack structure; forming a dielectric layer on the stack structure; forming a slit passing through the dielectric layer; forming a spacer on a sidewall of the slit. The stack structure includes first insulating layers and second insulating layers arranged alternately. The materials of the first insulating layers are different from the materials of the second insulating layers. A bottom of the slit exposes a first insulating layer disposed at the top of the first insulating layers.

Description

Memory device and method of making the same

The present disclosure relates to memory devices and methods of fabricating the same, and more particularly, to memory devices having a dielectric layer disposed on a stacked structure and methods of fabricating the same.

In a memory device, especially a three-dimensional memory device, a bit line (BL) and a memory cell array (array) are usually electrically connected through a contact structure. Stress from the stacked structure or the metal gate can cause the memory cell array to bend, making it difficult for the contact structures to align with the memory cell array. Therefore, the contact structure of the misaligned memory cell array may extend to the position of the string select line (SSL), causing a short risk between the bit line and the string select line (short risk), affecting the memory Device yield and yield.

Therefore, it is very important to avoid the short circuit problem between the bit line and the string select line.

The present disclosure relates to memory devices and methods of making the same.

According to an aspect of the present disclosure, a method for manufacturing a memory device is provided. The manufacturing method of the memory device includes the following steps. A stack structure is provided. The stack structure includes a plurality of first insulating layers and a plurality of second insulating layers stacked alternately, and the material of the first insulating layer is different from that of the second insulating layer. A dielectric layer is formed on the stacked structure. A slit is formed through the dielectric layer, and the bottom of the slit exposes the insulating layer disposed on top of the plurality of insulating layers. A spacer layer is formed on the side wall of the slit.

According to another aspect of the present disclosure, a memory device is provided. The memory device includes a stack structure, a dielectric layer disposed above the stack structure, a conductive film penetrating the stack structure and the dielectric layer, and a spacer layer disposed between the conductive film and the dielectric layer. The stacked structure includes a plurality of insulating layers and a plurality of conductive layers that are alternately stacked. The material of the dielectric layer is different from that of the insulating layer.

In order to have a better understanding of the above and other aspects of the present invention, the following embodiments are given and described in detail in conjunction with the accompanying drawings as follows.

In an embodiment of the present disclosure, a memory device and a manufacturing method of the memory device are provided. According to the embodiment of the manufacturing method, a memory device, such as a memory device including a dielectric layer disposed on a stacked structure, can be obtained, thereby improving the short circuit problem between the bit line and the string select line, and improving the performance of the memory device. rate and output.

In practical applications, the embodiments of the present disclosure can be implemented as a variety of different memory devices. For example, the embodiment may be applied to a three-dimensional vertical channel type memory device, but the present disclosure is not limited to this application. Relevant embodiments are provided below, and the memory device and the manufacturing method thereof provided by the present disclosure are described in detail in conjunction with the drawings. However, the present disclosure is not limited thereto. The descriptions in the embodiments, such as the detailed structure, the steps of the manufacturing method, and the material application, etc., are only for the purpose of illustration, and the scope of protection of the present disclosure is not limited to the above-mentioned aspects.

Meanwhile, it should be noted that the present disclosure does not show all possible embodiments. Those skilled in the relevant art can make changes and modifications to the structures and manufacturing methods of the embodiments to meet the needs of practical applications without departing from the spirit and scope of the present disclosure. Therefore, other implementation aspects not proposed in the present disclosure may also be applicable. Furthermore, the drawings are simplified for the purpose of clearly explaining the contents of the embodiments, and the dimension ratios in the drawings are not drawn according to the actual product scale. Therefore, the description and the drawings are only used to describe the embodiments, rather than to limit the protection scope of the present disclosure. In the following, the same/similar symbols are used to represent the same/similar elements for description.

Furthermore, the ordinal numbers such as "first", "second", "third" and other terms used in the description and the scope of the patent application are intended to modify the elements of the claim, and do not imply and represent the claim. Elements have any previous ordinal numbers, and they do not represent the order of a requested element and another requested element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a request with a certain name. An element can be clearly distinguished from another requested element with the same name.

1 to 15 are cross-sectional views illustrating a method of manufacturing the memory device 10 according to an embodiment. The manufacturing method of the memory device 10 includes the following steps:

Please refer to Figure 1. A substrate 101 is provided. The substrate 101 may comprise a semiconductor substrate, such as a semiconductor substrate comprising p-doped, n-doped or undoped polysilicon, germanium, or other suitable semiconductor materials. A stack structure 110 is formed on the upper surface 101U of the substrate 101 . The stack structure 110 includes a plurality of first insulating layers 111 , 112 , 113 , 114 , 115 , 116 , 117 , 118 and a plurality of second insulating layers 121 , 122 , 123 , 124 , 125 , 126 , 127 , which are alternately stacked along the Z-axis direction. Different from the material of the second insulating layers 121 - 127 . In one embodiment, the first insulating layers 111 - 118 may include oxides, such as silicon oxide; the second insulating layers 121 - 127 may include nitrides, such as silicon nitride. Next, a dielectric layer 130 and a first insulating film 131 are sequentially formed on the stacked structure 110 along the Z-axis direction, and the first insulating film 131 is formed on the dielectric layer 130 . The material of the dielectric layer 130 is different from the material of the first insulating layers 111 - 118 . Specifically, in the same etching process, the material of the dielectric layer 130 is different from the material of the first insulating layers 111 - 118 , so that the etching rate of the dielectric layer 130 is different from that of the first insulating layers 111 - 118 . In one embodiment, the dielectric layer 130 may include nitride, such as silicon nitride; the first insulating film 131 may include oxide, such as silicon dioxide.

In this embodiment, the first insulating layer 111 is located at the bottom of the stacked structure 110 and is in direct contact with the substrate 101 , and the first insulating layer 118 is located at the top of the stacked structure 110 and is in direct contact with the dielectric layer 130 . Among the first insulating layers 111 to 118 , the thickness of the first insulating layer 112 closest to the first insulating layer 111 may be different from that of the other first insulating layers 111 , 113 , 114 , 115 , 116 , 117 , and 118 . An insulating layer 113-118, but the invention is not limited to this. In one embodiment, the first insulating layers 111 - 118 and the second insulating layers 121 - 127 may be formed by a deposition process, such as a chemical vapor deposition (CVD) process.

Please refer to Figure 2. Holes 132 are formed in the stacked structure 110 , the dielectric layer 130 and the first insulating film 131 . For example, the stacked structure 110 , the dielectric layer 130 and the first insulating film 131 are patterned by an exposure photolithography process to Holes 132 are formed. The hole 132 extends downward along the Z-axis and penetrates through the stacked structure 110 , the dielectric layer 130 and the first insulating film 131 , so that the upper surface 101U of the substrate 101 and a part of the first insulating layer 111 used as the sidewall of the hole 132 ~118 and the second insulating layers 121~127 are exposed. On the plane formed by the X axis and the Y axis intersecting, the hole 132 may have a substantially circular or elliptical cross-sectional shape, but the present disclosure is not limited thereto.

Please refer to Figure 3. Next, lower plugs 133 are formed in the holes 132 , for example, by a selective deposition process, so as to form the lower plugs 133 at the bottoms of the holes 132 . In one embodiment, the lower plug 133 may be a monocrystalline or polycrystalline silicon layer or any combination thereof formed by selective epitaxial growth (SEG), or may be undoped or n-type or p-type doped epitaxial growth layer.

In this embodiment, the upper surface 133U of the lower plug 133 is interposed between the second insulating layer 121 and the second insulating layer 122 . More specifically, the upper surface 133U of the lower plug 133 is higher than the upper surface 121U of the second insulating layer 121 and lower than the lower surface 122B of the second insulating layer 122 . However, this disclosure is not limited to this.

Please refer to Figure 4. Next, a vertical channel structure 134 is formed on the inner sidewall of the hole 132 , and the vertical channel structure 134 extends through the stack structure 110 , the dielectric layer 130 and the first insulating film 131 along the Z axis. The vertical channel structures 134 may fill the holes 132 . The vertical channel structure 134 may be formed on the upper surface 133U of the lower plug 133 . The vertical channel structure 134 includes a memory layer 135 , a channel layer 136 , an insulating column 137 and an upper plug 138 . Forming the vertical channel structure 134 may, for example, include the following steps:

First, the memory layer 135 is formed on the inner sidewall of the hole 132 , the upper surface 133U of the lower plug 133 and the upper surface 131U of the first insulating film 131 , for example, by a deposition process. The memory layer 135 may include a multilayer structure known in the field of memory technology, such as ONO (oxide-nitride-oxide) structure, ONONO (oxide-nitride-oxide-nitride-oxide) ) structure, ONONONO (Oxide-Nitride-Oxide-Nitride-Oxide-Nitride-Oxide) structure, SONOS (Silicon-Silicon Oxide-Silicon Nitride-Silicon Oxide-Silicon) structure, BE-SONOS ( Band gap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, TANOS (tantalum nitride-alumina-silicon nitride-silicon oxide-silicon) structure, MA BE-SONOS (metal-high dielectric constant) Material energy band gap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure and its combination.

Next, the memory layer 135 formed on the upper surface 131U of the first insulating film 131 is removed by an etching process, and part of the memory layer 135 formed on the upper surface 133U of the lower plug 133 is removed, so that the lower plug 133 A part of the upper surface 133U is exposed.

Next, a channel layer 136 is formed on the inner sidewall of the memory layer 135 and the exposed upper surface 133U of the lower plug 133, for example, by a deposition process. The channel layer 136 may also cover the upper surface 131U of the first insulating film 131 and the upper surface 135U of the memory layer 135 which is substantially coplanar with the upper surface 131U. The channel layer 136 formed on the upper surface 131U of the first insulating film 131 and the upper surface 135U of the memory layer 135 is removed by an etching process to expose the upper surface 131U of the first insulating film 131 and the upper surface 135U of the memory layer 135 . The channel layer 136 may include a semiconductor material, such as a doped semiconductor material or an undoped semiconductor material. In one embodiment, the channel layer 136 may comprise polysilicon, such as doped polysilicon or undoped polysilicon.

Next, insulating pillars 137 are formed on inner sidewalls of the channel layer 136 . More specifically, insulating pillars 137 are formed by deposition to fill the holes 132 . The insulating pillars 137 may include a dielectric material including an oxide (eg, silicon oxide). After an etch back process is performed on the insulating pillars 137 , the upper plugs 138 are formed on the insulating pillars 137 , for example, by a deposition process to form the upper plugs 138 . The upper plug 138 may include a semiconductor material, such as a silicide, a doped semiconductor material, or an undoped semiconductor material. In one embodiment, the upper plug 138 may comprise polysilicon, such as doped polysilicon or undoped polysilicon. The upper plug 138 may be electrically connected to the channel layer 136 .

As shown in FIG. 4 , the channel layer 136 of the vertical channel structure 134 is disposed between the memory layer 135 and the insulating column 137 , and between the memory layer 135 and the upper plug 138 . The memory layer 135 can also be understood as being disposed on the outer sidewall of the channel layer 136 . The side surfaces of the vertical channel structure 134 are in contact with the dielectric layer 130 .

In one embodiment, the height of the dielectric layer 130 in the Z-axis direction is smaller than the height of the upper plug 138 in the Z-axis direction. For example, in the Z-axis direction, the upper surface 130U of the dielectric layer 130 may be lower than the upper surface 138U of the upper plug 138 , and the lower surface 130B of the dielectric layer 130 may be higher than the lower surface 138B of the upper plug 138 . However, this disclosure is not limited to this.

After the vertical channel structure 134 is formed, a second insulating film 139 is formed to cover the upper surface 131U of the first insulating film 131 and the vertical channel structure 134 (as shown in FIG. 4 ), for example, by a deposition process. In one embodiment, the second insulating film 139 may include oxide, such as silicon dioxide.

Please refer to Figure 5. Next, a slit 140 is formed in the stacked structure 110 , the dielectric layer 130 , the first insulating film 131 and the second insulating film 139 , for example, the slit 140 is formed by an etching process. The slit 140 extends through the second insulating film 139 , the first insulating film 131 and the dielectric layer 130 along the Z axis, so as to be used as a part of the first insulating layer 118 , the dielectric layer 130 , and the first insulating layer 118 , the The insulating film 131 and the second insulating film 139 are exposed. In this embodiment, the etching process for forming the slits 140 is stopped when etching slightly beyond the lower surface 130B of the dielectric layer 130 , so that the bottoms of the slits 140 are disposed on the lower surface 130B of the dielectric layer 130 and the second insulating layer Between the upper surfaces 127U of the second insulating layers 127 disposed at the top of the layers 121 - 127 , the bottom of the slit 140 exposes the first insulating layer 118 disposed at the top of the first insulating layers 111 - 118 . However, the present disclosure is not limited thereto, and the bottoms of the slits 140 may also be disposed in other layers.

In this embodiment, the slit 140 is shown as having a cross-sectional shape that is wide at the top and narrow at the bottom on a plane formed by the Y-axis and the Z-axis alternately, but the present disclosure is not limited to this.

Please refer to Figure 6. Next, a spacer layer 141 is formed on the inner sidewall of the slit 140 , the bottom of the slit 140 and the upper surface 139U of the second insulating film 139 , for example, the spacer layer 141 is formed by a deposition process. The spacer layer 141 may include a semiconductor material, such as silicon.

Please refer to Figure 7. Next, an etch back process is performed to remove the spacer layer 141 formed on the upper surface 139U of the second insulating film 139, and to remove part of the spacer layer 141 formed at the bottom of the slit 140, so that the first insulating layer 111~ The first insulating layer 118 disposed on the top of the 118 is exposed.

Please refer to Figure 8. Next, an etching process is performed on the stacked structure 110 from the bottom of the slit 140 toward the substrate 101 to form the trench 142 . The trenches extend downward along the Z-axis (ie, toward the substrate 101 ), through the stack structure 110 , the dielectric layer 130 , the first insulating film 131 and the second insulating film 139 , so as to expose the upper surface 101U of the substrate 101 , and use The spacer layer 141 , a part of the first insulating layers 111 - 118 and the second insulating layers 121 - 127 serving as the sidewalls of the trench 142 are exposed. As shown in FIG. 8 , the spacer layer 141 prevents the dielectric layer 130 , the first insulating film 131 and the second insulating film 139 from being exposed by the trench 142 . The spacer layer 141 may be used to protect the dielectric layer 130 in subsequent steps.

Please refer to Figure 9. An etching process is performed through the trench 142 to remove the second insulating layers 121 - 127 , thereby forming spaces between the first insulating layers 111 - 118 . Since the dielectric layer 130 is not exposed by the trenches 142 due to the spacer layer 141 , the dielectric layer 130 is not removed during the removal of the second insulating layers 121 - 127 .

Please refer to Figure 10. Then, a gate oxide layer 143 is formed on the sidewall of the lower plug 133 exposed by the space between the first insulating layer 111 and the first insulating layer 112 . The gate oxide layer 143 may be formed by performing an oxidation process on the lower plug 133 . In this embodiment, a thermal oxidation process is performed on the exposed sidewalls of the lower plugs 133 to oxidize the exposed sidewalls of the lower plugs 133 to form the gate oxide layer 143 . In one embodiment, the gate oxide layer 143 may surround the lower plug 133 . .

In one embodiment, during the thermal oxidation process, the spacer layer 141 is also oxidized, for example, partially or completely oxidized, so the spacer layer 141 after the thermal oxidation process may include oxides of semiconductor materials, such as silicon oxide ( not shown).

Please refer to Figure 11. Next, the space between the first insulating layers 111 - 118 is filled with conductive material, in other words, the conductive material is filled in the original positions of the removed second insulating layers 121 - 127 . The conductive material may include polysilicon, metal, or other suitable conductive materials. In one embodiment, the conductive material may include tungsten.

After the conductive material is filled, an etch-back process is performed on the structure to remove a portion of the conductive material, thereby forming a plurality of recesses 142R, as shown in FIG. 11 . After the etch back process, the remaining conductive materials form conductive layers 151 - 157 . In this embodiment, each of the recesses 142R is a lateral recess extending from the trench 142 (along the Y-axis direction) into the conductive material. Thus, each of the alcoves 142R connects the trenches 142 . Each of the recesses 142R may be defined as being formed by two adjacent first insulating layers 111 - 118 , conductive layers 151 - 157 between the two adjacent first insulating layers 111 - 118 , and a trench 142 Space. The gate oxide layer 143 can be used to electrically isolate the lower plug 133 from the conductive layer 151 . In one embodiment, the conductive layers 151 - 157 can be used as gate electrodes. The process steps included in FIGS. 9 to 11 may be understood as gate replacement processes.

In one embodiment, a dielectric film 160 may be further included between the conductive layers 151 - 157 and the first insulating layers 111 - 118 , as shown in FIG. 11A . For example, before filling the conductive material, the dielectric film 160 is firstly formed in the space between the first insulating layers 111-118 by lining, and then the remaining space between the first insulating layers 111-118 is filled with the conductive material . The dielectric film 160 may include a high dielectric constant (high-k) material, such as aluminum oxide (Al ₂ O ₃ ), hafnium dioxide (HfO ₂ ), silicon nitride (Si ₃ N ₄ ), zirconium dioxide ( ZrO ₂ ), titanium dioxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), lanthanum oxide (La ₂ O ), or other suitable materials, and the like. The dielectric film can be formed by a deposition process.

In the structures shown in FIGS. 11 and 11A , memory cells may be defined in the memory layer 135 . More specifically, memory cells may be defined in the memory layer 135 where each of the conductive layers 151 - 157 is interleaved with the channel layer 136 of the vertical channel structure 134 . The stacked structure 150 including the plurality of first insulating layers 111 - 118 and the plurality of conductive layers 151 - 157 which are alternately stacked includes a plurality of memory cells. A plurality of memory cells form a memory cell array.

Please refer to Figure 12. Spacers 144 are formed in the trenches 142 and the recesses 142R. Specifically, the sidewalls of the spacer layer 141 , the sidewalls of the conductive layers 151 to 157 , the sidewalls of the first insulating layers 111 to 118 and the substrate 101 are exposed by the trenches 142 A spacer 144 is formed on the upper surface 101U that comes out, for example, by a deposition process. Spacers 144 may include a dielectric material, such as silicon dioxide. Next, the spacer 144 at the bottom of the trench 142 is removed to expose the upper surface 101U of the substrate 101 , for example, a break-through etch process is performed to remove the spacer 144 at the bottom of the trench 142 .

Referring to FIG. 13 , after the spacers 144 are formed, a conductive film 145 is formed in the trenches 142 . The spacer 144 electrically isolates the conductive film 145 from the conductive layers 151 to 157 . The conductive film 145 may include polysilicon, metal or other suitable conductive materials. In one embodiment, the conductive film 145 may include tungsten. In this embodiment, the conductive film 145 extends on a plane formed by intersecting the X-axis and the Z-axis, and contacts the substrate 101 . As shown in FIG. 13 , the conductive film 145 penetrates through the stacked structure 150 and the dielectric layer 130 , and the spacer layer 141 is disposed between the conductive film 145 and the dielectric layer 130 .

Please refer to Figure 14. Next, an interlayer dielectric (ILD) 146 is formed on the second insulating film 139, for example, by a deposition process.

Please refer to Figure 15. Then, contact structures 147 and 148 are formed, and the contact structures 147 and 148 are electrically connected to the vertical channel structure 134 and the conductive film 145, respectively. The vertical channel structure 134 may be electrically connected to other conductive elements, such as a plurality of bit lines (not shown) above the interlayer dielectric layer 146 , via the contact structure 147 . Contact structures 147 and 148 may comprise polysilicon, metal, or other suitable conductive materials.

The contact structure 147 electrically connected to the vertical channel structure 134 is disposed on the upper surface 138U of the upper plug 138 , and the contact structure 147 may not contact the dielectric layer 130 . The memory cell array is electrically connected to other conductive elements, such as a plurality of bit lines, through the channel layer 136 , the upper plug 138 and the contact structure 147 .

In some cases, the process of forming the contact structure 147 may deviate. For example, taking FIG. 15 as an example, the contact structure 147 ′ is not completely aligned with the upper plug 138 , and the contact structure 147 ′ may extend toward the substrate 101 along the Z-axis direction. and contact the dielectric layer 130 . Specifically, the lower surface 147B of the contact structure 147' may be lower than the upper surface 138U of the upper plug 138, and the lower surface 147B of the contact structure 147' may be coplanar and in direct contact with the upper surface 130U of the dielectric layer 130. In this case, the memory cell array is electrically connected to other conductive elements, such as a plurality of bit lines, through the channel layer 136 and the upper plug 138 ; or, the memory cell array is electrically connected to the contact structure 147 ′ through the channel layer 136 . It is electrically connected to other conductive elements, such as electrically connected to a plurality of bit lines. Even if the process of forming the contact structure 147 deviates unexpectedly (eg, where the contact structure 147 ′ is formed), the dielectric layer 130 can prevent the contact structure 147 ′ from extending to the conductive layers 151 - 157 of the stack structure 150 and/or contact conductive At least one of the layers 151 to 157 causes problems such as short circuit.

16 to 18 are cross-sectional views illustrating a method of manufacturing the memory device 20 according to another embodiment. The differences between the memory device 20 and the memory device 10 are described below.

In the manufacturing method of the memory device 10 , as shown in FIG. 1 to FIG. 4 , firstly, the stacked structure 110 , the dielectric layer 130 and the first insulating film 131 are sequentially formed on the substrate 101 , and then the layers extending along the Z axis are formed. The vertical channel structure 134 penetrates through the stacked structure 110 , the dielectric layer 130 and the first insulating film 131 ; in other words, the vertical channel structure 134 is formed after the dielectric layer 130 is formed. In the manufacturing method of the memory device 20 , the stacked structure 110 is sequentially formed on the substrate 101 , and then the vertical channel structure 134 extending through the stacked structure 110 along the Z axis is formed (as shown in FIG. 16 ), and then the stacked structure is formed on the substrate 101 . The dielectric layer 130 and the first insulating film 131 are sequentially formed on the 110 (as shown in FIG. 17 ); in other words, the vertical channel structure 134 is formed before the dielectric layer 130 is formed, as shown in FIG. 17 , the vertical channel structure 134 is formed The structure 134 does not penetrate through the dielectric layer 130 and the first insulating film 131 .

In addition, as shown in FIG. 4 , the manufacturing method of the memory device 10 includes forming a second insulating film 139 to cover the upper surface 131U of the first insulating film 131 and the vertical channel structure 134 , and then performing the steps shown in FIGS. 5 to 15 . shown steps. Since the manufacturing method of the memory device 20 does not include forming the second insulating film 139 , the steps shown in FIGS. 5 to 15 can be performed after the first insulating film 131 is formed.

The following is a brief description of the manufacturing method of the memory device 20, which includes the following steps:

Please refer to Figure 16. A substrate 101 is provided. A stack structure 110 including first insulating layers 111 - 118 and second insulating layers 121 - 127 which are alternately stacked is formed on the substrate 101 . The lower plug 133 is formed in the stacked structure 110 . A vertical channel structure 134 is formed on the lower plug 133 , penetrating the stack structure 110 , and the vertical channel structure 134 includes a memory layer 135 , a channel layer 136 , an insulating pillar 137 and an upper plug 138 . Next, referring to FIG. 17 , a dielectric layer 130 is formed on the stacked structure 110 to cover the first insulating layer 118 and the vertical channel structure 134 , and the upper surface of the vertical channel structure 134 contacts the dielectric layer 130 . Then, a first insulating film 131 is formed on the dielectric layer 130 .

Next, the spacer layer 141 , the gate oxide layer 143 , the conductive layers 151 to 157 , the spacer 144 and the conductive film 145 are formed in steps similar to those shown in FIGS. 5 to 15 . After the conductive film 145 is formed, an interlayer dielectric layer 146 is formed on the first insulating film 131, and then contact structures 147 and 148 electrically connected to the vertical channel structure 134 and the conductive film 145, respectively, are formed, thereby forming as shown in FIG. 18 The memory device 20 is shown.

Please refer to Figure 18. In this embodiment, the contact structure 147 electrically connected to the vertical channel structure 134 is disposed on the upper surface 138U of the upper plug 138 , and the contact structure 147 penetrates through the dielectric layer 130 . The lower surface 147B of the contact structure 147 may be coplanar with the lower surface 130B of the dielectric layer 130 .

In one embodiment, when the memory device 10/20 of the present disclosure is applied to a three-dimensional memory device, such as a NAND type memory device with a vertical channel structure, the conductive layers 151-157 of the stack structure 150 The conductive layer 151 disposed at the bottom (bottom) can be used as a ground select line (GSL) of the memory devices 10/20, and the conductive layer 157 disposed on the top of the conductive layers 151-157 can be used as a tandem selection Line (string select line; SSL), the conductive layers 152-156 can be used as word lines (word line; WL), and the conductive film 145 can be used as a common source line (common source line; CSL). Alternatively, the memory device 10/20 may include a plurality of string select lines, for example, the conductive layers 156 and 157 are both used as string select lines. In one embodiment, the memory device 10/20 may be a gate-all-around type of memory device.

In the memory device 10 / 20 according to the present disclosure, the dielectric layer 130 is disposed above the stacked structure 150 , and the material of the dielectric layer 130 is different from the material of the first insulating layers 111 - 118 of the stacked structure 150 . Since the etching rate of the dielectric layer 130 is different from the etching rate of the first insulating layers 111-118 (in the same etching process), the dielectric layer 130 can be used as an etching stop during the process of forming the contact structures 147/147' An etch stop layer is used to avoid short circuit and other problems caused by the contact structures 147/147' extending to the conductive layers 151-157 of the stack structure 150 and/or at least one of the contact conductive layers 151-157 along the Z-axis direction. In addition, the memory device 10/20 includes a spacer layer 141, which can protect the dielectric layer 130 during the gate replacement process so that the dielectric layer 130 is not removed during the gate replacement process.

In a comparative example, the memory device does not include an etch stop layer, so that when the contact structure is formed electrically connected to the vertical channel structure, eg, to establish electrical connection between the bit line and the vertical channel structure, is formed over the vertical channel structure Contact structure, the contact structure will extend downward to the conductive layer in the stacked structure towards the substrate, resulting in the failure of electrical connection to be established correctly and causing short circuit problems between the bit line and the conductive layer, such as the bit line and the tandem Short circuits between select lines affect the yield and yield of memory devices. The present disclosure provides a memory device and a manufacturing method thereof by disposing a dielectric layer as an etch stop layer on the stacked structure, so that the depth of the contact structure can be properly controlled (or it can be understood that the lower surface of the contact structure can be positioned in a proper position), which can effectively reduce the short-circuit problem and improve the yield and yield of memory devices. In addition, the memory device and the manufacturing method thereof provided by the present disclosure include a spacer layer which can protect the dielectric layer, so as to prevent the dielectric layer from being damaged during the subsequent gate formation process. In addition, the memory device and the manufacturing method thereof provided by the present disclosure can be integrated into the existing memory device manufacturing process, and have the advantages of easy implementation and low cost.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

10,20: Memory Device 101: Substrate 101U, 121U, 127U, 130U, 131U, 133U, 135U, 138U, 139U: Upper surface 110: Stacked Structure 111~118: The first insulating layer 121~127: The second insulating layer 130: Dielectric layer 122B, 130B, 138B, 147B: lower surface 131: first insulating film 132: Hole 133: Lower plug 134: Vertical Channel Structure 135: Memory Layer 136: channel layer 137: Insulation column 138: Upper Plug 139: Second insulating film 140: Slit 141: Spacer Layer 142: Groove 142R: Alcove 143: gate oxide layer 144: Spacer 145: Conductive film 146: Interlayer dielectric layer 147, 147', 148: Contact Structure 150: Stacked Structure 151~157: Conductive layer 160: Dielectric film

1 to 15 are schematic cross-sectional views illustrating a method of manufacturing a memory device according to an embodiment; and 16 to 18 are schematic cross-sectional views illustrating a method for manufacturing a memory device according to another embodiment.

10: Memory device

101: Substrate

111~118: The first insulating layer

130U, 138U: Upper surface

130: Dielectric layer

131: first insulating film

134: Vertical Channel Structure

135: Memory Layer

136: channel layer

137: Insulation column

138: Upper Plug

139: Second insulating film

145: Conductive film

146: Interlayer dielectric layer

147, 147', 148: Contact Structure

150: Stacked Structure

151~157: Conductive layer

Claims (10)

A method of manufacturing a memory device, comprising: A stack structure is provided, the stack structure includes a plurality of first insulating layers and a plurality of second insulating layers stacked alternately, and the materials of the first insulating layers are different from those of the second insulating layers; forming a dielectric layer on the stacked structure; forming a slit through the dielectric layer, a bottom of the slit exposes a first insulating layer disposed at the top of the first insulating layers; and A spacer layer is formed on one side wall of the slit. The manufacturing method according to claim 1, further comprising: forming a vertical channel structure through the stack structure, wherein the vertical channel structure is formed before the step of forming the dielectric layer on the stacked structure. The manufacturing method of claim 2, wherein an upper surface of the vertical channel structure contacts the dielectric layer. The manufacturing method according to claim 1, further comprising: forming a vertical channel structure through the stack structure, wherein the vertical channel structure is formed after the step of forming the dielectric layer on the stacked structure. The manufacturing method of claim 4, wherein the vertical channel structure penetrates the dielectric layer, and a side surface of the vertical channel structure contacts the dielectric layer. A memory device comprising: a stack structure, comprising a plurality of insulating layers and a plurality of conductive layers stacked alternately; a dielectric layer disposed above the stacked structure, and the material of the dielectric layer is different from the material of the insulating layers; a conductive film penetrating the stacked structure and the dielectric layer; and A spacer layer is arranged between the conductive film and the dielectric layer. The memory device as claimed in claim 6, further comprising: A vertical channel structure penetrates the stack structure, wherein the vertical channel structure contacts the dielectric layer. The memory device of claim 7, wherein an upper surface of the vertical channel structure contacts the dielectric layer. The memory device of claim 7, wherein a side surface of the vertical channel structure contacts the dielectric layer. The memory device as claimed in claim 7, further comprising: a contact structure disposed above the stack structure and electrically connected to the vertical channel structure, The contact structure has a lower surface, and the lower surface is coplanar with an upper surface or a lower surface of the dielectric layer.

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