TWI785462B - Memory device and method for manufacturing the same - Google Patents

Abstract

A method for manufacturing a memory device is provided. The method includes: providing a stack structure; forming a dielectric layer on the stack structure; forming a slit passing through the dielectric layer; forming a spacer on a sidewall of the slit. The stack structure includes first insulating layers and second insulating layers arranged alternately. The materials of the first insulating layers are different from the materials of the second insulating layers. A bottom of the slit exposes a first insulating layer disposed at the top of the first insulating layers.

Description

Memory device and manufacturing method thereof

The present disclosure relates to memory devices and methods of fabricating the same, and more particularly to memory devices having dielectric layers disposed on stacked structures and methods of fabricating the same.

In a memory device, especially in a three-dimensional memory device, a bit line (BL) is usually electrically connected to a memory cell array (array) through a contact structure. Stress from the stack structure or metal gates can cause the cell array to bend, making it difficult for the contact structure to align with the memory cell array. Therefore, the contact structure of the misaligned memory cell array may extend to the position of the string select line (SSL), causing a short-circuit problem (short risk) between the bit line and the string select line, affecting the memory Device yield and throughput.

Therefore, it is very important to avoid the short circuit problem between the bit line and the string select line.

The present disclosure relates to memory devices and methods of making them.

According to an aspect of the present disclosure, a method for manufacturing a memory device is provided. The manufacturing method of the memory device includes the following steps. Provide a stack structure, the stack structure includes a plurality of first insulating layers and a plurality of second insulating layers stacked staggered, the material of the first insulating layer different from the material of the second insulating layer. A dielectric layer is formed on the stacked structure. A slit is formed to penetrate the dielectric layer, and the bottom of the slit exposes the top insulating layer among the plurality of insulating layers. A spacer layer is formed on the sidewall of the slit.

According to another aspect of the present disclosure, a memory device is provided. The memory device includes: a stack structure, a dielectric layer disposed above the stack structure, a conductive film passing through the stack structure and the dielectric layer, and a spacer layer disposed between the conductive film and the dielectric layer. The stack structure includes a plurality of insulating layers and a plurality of conductive layers stacked alternately. The material of the dielectric layer is different from that of the insulating layer.

In order to have a better understanding of the above and other aspects of the present invention, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

10,20: memory device

101: Substrate

101U, 121U, 127U, 130U, 131U, 133U, 135U, 138U, 139U: upper surface

110:Stack structure

111~118: the first insulating layer

121~127: second insulating layer

130: dielectric layer

122B, 130B, 138B, 147B: lower surface

131: first insulating film

132: hole

133: lower plug

134: Vertical channel structure

135: memory layer

136: Channel layer

137: Insulation column

138: upper plug

139: second insulating film

140: slit

141: spacer layer

142: Groove

142R: alcove

143:Gate oxide layer

144: gap wall

145: Conductive film

146: interlayer dielectric layer

147, 147’, 148: contact structure

150: stacked structure

151~157: conductive layer

160: Dielectric film

1 to 15 are schematic cross-sectional views illustrating a method of manufacturing a memory device according to an embodiment; and FIGS. 16 to 18 are schematic cross-sectional views illustrating a method of manufacturing a memory device according to another embodiment.

In an embodiment of the disclosure, a memory device and a method for manufacturing the memory device are proposed. According to the embodiment of the manufacturing method, a memory device can be obtained, for example, a memory device including a dielectric layer disposed on a stack structure, thereby improving the short circuit problem between the bit line and the serial selection line, and improving the quality of the memory device at the same time. rate and production.

In practical applications, the embodiments of the present disclosure can be implemented as various memory devices. For example, the embodiments can be applied to three-dimensional vertical channel type memory devices, but the present disclosure is not limited to this application. The relevant embodiments are proposed below, and the memory device and its manufacturing method proposed in this disclosure are described in detail in conjunction with the drawings. However, the present disclosure is not limited thereto. The descriptions in the embodiments, such as the detailed structure, the steps of the manufacturing method and the application of materials, etc., are for illustration purposes only, and the protection scope of the present disclosure is not limited to the above-mentioned aspects.

At the same time, it should be noted that this disclosure does not show all possible embodiments. Those skilled in the art may change and modify the structures and manufacturing methods of the embodiments without departing from the spirit and scope of the present disclosure, so as to meet the needs of practical applications. Therefore, other implementation aspects not proposed in this disclosure may also be applicable. Furthermore, the drawings are simplified to clearly illustrate the content of the embodiments, and the size ratios in the drawings are not drawn according to the proportion of the actual product. Therefore, the specification and drawings are only used to describe the embodiments, rather than to limit the protection scope of the present disclosure. The same/similar symbols are used to represent the same/similar components in the following description.

Furthermore, the ordinal numbers used in the specification and claims, such as "first", "second", and "third", are intended to modify the elements of the claim, and do not imply and represent the claimed The components have any previous ordinal numbers, nor does it imply the order of one claimed component with another, or the order in the method of manufacture. The use of these ordinal numbers is only used to make a claimed component with a certain designation An element is clearly distinguishable from another claimed element having the same designation.

1 to 15 are cross-sectional views illustrating a manufacturing method of the memory device 10 according to an embodiment. The manufacturing method of memory device 10 comprises the following steps:

Please refer to Figure 1. A substrate 101 is provided. The substrate 101 may comprise a semiconductor substrate, such as a semiconductor substrate comprising p-type doped, n-type doped or undoped polysilicon, germanium or other suitable semiconductor materials. A stacked structure 110 is formed on the upper surface 101U of the substrate 101. The stacked structure 110 includes a plurality of first insulating layers 111, 112, 113, 114, 115, 116, 117, 118 and a plurality of second insulating layers 121, 122, 123, 124, 125, 126, 127 stacked staggered along the Z-axis direction. The materials of the first insulating layers 111-118 It is different from the material of the second insulating layers 121-127. In an embodiment, the first insulating layers 111 - 118 may include oxides, such as silicon oxide; the second insulating layers 121 - 127 may include nitrides, such as silicon nitride. Next, a dielectric layer 130 and a first insulating film 131 are sequentially formed on the stack structure 110 along the Z-axis direction, and the first insulating film 131 is formed on the dielectric layer 130 . The material of the dielectric layer 130 is different from that of the first insulating layers 111 - 118 . Specifically, in the same etching process, the material of the dielectric layer 130 is different from that of the first insulating layers 111 - 118 , so that the etching rate of the dielectric layer 130 is different from the etching rate of the first insulating layers 111 - 118 . In one embodiment, the dielectric layer 130 may include nitride, such as silicon nitride; the first insulating film 131 may include oxide, such as silicon dioxide.

In this embodiment, the first insulating layer 111 is located at the bottom of the stack structure 110 and directly contacts the substrate 101 , and the first insulating layer 118 is located at the top of the stack structure 110 and directly contacts the dielectric layer 130 . Among the first insulating layers 111-118, the thickness of the first insulating layer 112 closest to the first insulating layer 111 can be different from other first insulating layers 111, 113, 114, 115, 116, 117, 118, for example, the thickness of the first insulating layer 112 is greater than that of the first insulating layer 111 and the first insulating layer 111. An insulating layer 113-118, but the present invention is not limited thereto. In one embodiment, the first insulating layers 111-118 and the second insulating layers 121-127 can be made by deposition process, such as chemical vapor deposition (chemical vapor deposition; CVD) process.

Please refer to Figure 2. The hole 132 is formed in the stack structure 110, the dielectric layer 130 and the first insulating film 131, for example, by patterning the stack structure 110, the dielectric layer 130 and the first insulating film 131 through an exposure lithography process. A hole 132 is formed. The hole 132 extends downward along the Z axis and penetrates through the stacked structure 110 , the dielectric layer 130 and the first insulating film 131 , so that the upper surface 101U of the substrate 101 and a part of the first insulating layer 111 used as the sidewall of the hole 132 ~118 and the second insulating layers 121~127 are exposed. On the plane formed by the intersection of the X axis and the Y axis, the hole 132 may have a substantially circular or elliptical cross-sectional shape, but the present disclosure is not limited thereto.

Please refer to Figure 3. Next, a lower plug 133 is formed in the hole 132 , such as by a selective deposition process, so as to form the lower plug 133 at the bottom of the hole 132 . In one embodiment, the lower plug 133 can be a single crystal or polycrystalline silicon layer formed by selective epitaxial growth (SEG) or any combination of the above, and can also be undoped or n-type or p-type doped epitaxial growth layer.

In this embodiment, the upper surface 133U of the lower plug 133 is interposed between the second insulating layer 121 and the second insulating layer 122 . More specifically, the upper surface 133U of the lower plug 133 is higher than the upper surface 121U of the second insulating layer 121 and lower than the lower surface 122B of the second insulating layer 122 . But this disclosure is not limited thereto.

Please refer to Figure 4. Next, a vertical channel structure 134 is formed on the inner sidewall of the hole 132 , and the vertical channel structure 134 extends along the Z-axis through the stack structure 110 , the dielectric layer 130 and the first insulating film 131 . The vertical channel structure 134 can fill the hole 132 . The vertical channel structure 134 may be formed on the upper surface 133U of the lower plug 133 . The vertical channel structure 134 includes a memory layer 135 , a channel layer 136 , insulating pillars 137 and upper plugs 138 . Forming the vertical channel structure 134 may, for example, include the following steps:

First, the memory layer 135 is formed on the inner sidewall of the hole 132 , the upper surface 133U of the lower plug 133 and the upper surface 131U of the first insulating film 131 , for example, by a deposition process. The memory layer 135 may comprise a multilayer structure (multilayer structure) known in the field of memory technology, such as ONO (oxide-nitride-oxide) structure, ONONO (oxide-nitride-oxide-nitride-oxide ) structure, ONONONO (oxide-nitride-oxide-nitride-oxide-nitride-oxide) structure, SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, BE-SONOS ( Band gap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, TANOS (tantalum nitride-alumina-silicon nitride-silicon oxide-silicon) structure, MA BE-SONOS (metal-high dielectric constant Material bandgap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure and its combination.

Next, the memory layer 135 formed on the upper surface 131U of the first insulating film 131 is removed by an etching process, and part of the memory layer 135 formed on the upper surface 133U of the lower plug 133 is removed, so that the lower plug 133 A portion of the upper surface 133U is exposed.

Next, a channel layer 136 is formed on the inner sidewall of the memory layer 135 and the exposed upper surface 133U of the lower plug 133 , for example, by a deposition process. The channel layer 136 may also cover the upper surface 131U of the first insulating film 131 and approximately the upper surface 131U is coplanar with the upper surface 135U of the memory layer 135 . The channel layer 136 formed on the upper surface 131U of the first insulating film 131 and the upper surface 135U of the memory layer 135 is removed by an etching process, so that the upper surface 131U of the first insulating film 131 and the upper surface 135U of the memory layer 135 are exposed . The channel layer 136 may comprise a semiconductor material, such as a doped semiconductor material or an undoped semiconductor material. In one embodiment, the channel layer 136 may include polysilicon, such as doped polysilicon or undoped polysilicon.

Next, insulating pillars 137 are formed on inner sidewalls of the channel layer 136 . More specifically, the insulating pillars 137 are formed by deposition to fill the holes 132 . The insulating pillar 137 may include a dielectric material including an oxide (eg, silicon oxide). After an etch back process is performed on the insulating pillar 137, the upper plug 138 is formed on the insulating pillar 137, for example, the upper plug 138 is formed by a deposition process. The upper plug 138 may include semiconductor material, such as metal silicide, doped semiconductor material or undoped semiconductor material. In one embodiment, the upper plug 138 may comprise polysilicon, such as doped polysilicon or undoped polysilicon. The upper plug 138 is electrically connected to the channel layer 136 .

As shown in FIG. 4 , the channel layer 136 of the vertical channel structure 134 is disposed between the memory layer 135 and the insulating pillar 137 , and is disposed between the memory layer 135 and the upper plug 138 . The memory layer 135 can also be understood as being disposed on the outer sidewall of the channel layer 136 . Side surfaces of the vertical channel structure 134 are in contact with the dielectric layer 130 .

In one embodiment, the height of the dielectric layer 130 in the Z-axis direction is smaller than the height of the upper plug 138 in the Z-axis direction. For example, in the Z-axis direction, the upper surface 130U of the dielectric layer 130 may be lower than the upper surface 138U of the upper plug 138 , and the lower surface 130B of the dielectric layer 130 may be higher than the lower surface 138B of the upper plug 138 . But this disclosure is not limited thereto.

After the vertical channel structure 134 is formed, the second insulating film 139 is formed to cover the upper surface 131U of the first insulating film 131 and the vertical channel structure 134 (as shown in FIG. 4 ), for example, by a deposition process. In one embodiment, the second insulating film 139 may include oxide, such as silicon dioxide.

Please refer to Figure 5. Next, the slit 140 is formed in the stacked structure 110 , the dielectric layer 130 , the first insulating film 131 and the second insulating film 139 , for example, the slit 140 is formed by an etching process. The slit 140 extends through the second insulating film 139, the first insulating film 131 and the dielectric layer 130 along the Z axis, so as to be used as a part of the sidewall of the slit 140, the first insulating layer 118, the dielectric layer 130, the first The insulating film 131 and the second insulating film 139 are exposed. In this embodiment, the etching process for forming the slit 140 stops when etching slightly beyond the lower surface 130B of the dielectric layer 130, so that the bottom of the slit 140 is disposed between the lower surface 130B of the dielectric layer 130 and the second insulating layer 130B. The bottom of the slit 140 exposes the first insulating layer 118 disposed on the top of the first insulating layers 111 - 118 between the upper surfaces 127U of the second insulating layer 127 disposed on the top among the layers 121 - 127 . However, the present disclosure is not limited thereto, and the bottom of the slit 140 may also be disposed in other layers.

In this embodiment, the slit 140 is shown as having a cross-sectional shape with a wide top and a narrow bottom on a plane formed by the intersection of the Y-axis and the Z-axis, but the disclosure is not limited thereto.

Please refer to Figure 6. Next, the spacer layer 141 is formed on the inner sidewall of the slit 140 , the bottom of the slit 140 and the upper surface 139U of the second insulating film 139 , for example, the spacer layer 141 is formed by a deposition process. The spacer layer 141 may include semiconductor material, such as silicon.

Please refer to Figure 7. Next, perform an etch-back process to remove the spacer layer 141 formed on the upper surface 139U of the second insulating film 139, and remove part of the spacer layer 141 formed at the bottom of the slit 140, so that the first insulating layer 111~ The first insulating layer 118 disposed on the top in 118 is exposed.

Please refer to Figure 8. Next, an etching process is performed on the stacked structure 110 from the bottom of the slit 140 toward the substrate 101 to form the trench 142 . The trench extends downward along the Z axis (ie, toward the substrate 101 ), and penetrates the stacked structure 110 , the dielectric layer 130 , the first insulating film 131 and the second insulating film 139 , so that the upper surface 101U of the substrate 101 is exposed, and used The spacer layer 141 serving as the sidewall of the trench 142 , a part of the first insulating layers 111 - 118 and the second insulating layers 121 - 127 are exposed. As shown in FIG. 8 , the spacer layer 141 prevents the dielectric layer 130 , the first insulating film 131 and the second insulating film 139 from being exposed by the trench 142 . The spacer layer 141 can be used to protect the dielectric layer 130 in subsequent steps.

Please refer to Figure 9. An etching process is performed through the trench 142 to remove the second insulating layers 121 - 127 , thereby forming spaces between the first insulating layers 111 - 118 . Since the spacer layer 141 prevents the dielectric layer 130 from being exposed by the trench 142 , the dielectric layer 130 will not be removed during the removal of the second insulating layers 121 - 127 .

Please refer to Figure 10. Then, a gate oxide layer 143 is formed on the sidewall of the lower plug 133 exposed by the space between the first insulating layer 111 and the first insulating layer 112 . The gate oxide layer 143 can be formed by performing an oxidation process on the lower plug 133 . In this embodiment, the exposed sidewall of the lower plug 133 is oxidized by performing a thermal oxidation process on the exposed sidewall of the lower plug 133 to form the gate oxide layer 143 . In one embodiment, the gate oxide layer 143 may surround the lower plug 133 . .

In one embodiment, during the thermal oxidation process, the spacer layer 141 is also oxidized, such as partially oxidized or fully oxidized, so the spacer layer 141 after the thermal oxidation process may include oxides of semiconductor materials, such as silicon oxide ( not shown).

Please refer to Figure 11. Next, the spaces between the first insulating layers 111 - 118 are filled with conductive material, in other words, the conductive material is filled in the original positions of the removed second insulating layers 121 - 127 . The conductive material may include polysilicon, metal or other suitable conductive materials. In one embodiment, the conductive material may include tungsten.

After filling the conductive material, an etch-back process is performed on the structure to remove part of the conductive material, thereby forming a plurality of recesses 142R, as shown in FIG. 11 . After the etch-back process, the remaining conductive materials form the conductive layers 151 - 157 . In this embodiment, each of the alcoves 142R are lateral alcoves extending from the trench 142 (along the Y-axis direction) into the conductive material. Accordingly, each of the alcoves 142R connects to the trench 142 . Each of the alcoves 142R can be defined as being formed by two adjacent first insulating layers 111-118, the conductive layers 151-157 between the two adjacent first insulating layers 111-118, and the trench 142. Space. The gate oxide layer 143 can be used to electrically isolate the lower plug 133 from the conductive layer 151 . In one embodiment, the conductive layers 151 - 157 can be used as gates. The process steps included in FIGS. 9 to 11 can be understood as a gate replacement process.

In one embodiment, a dielectric film 160 may be further included between the conductive layers 151 - 157 and the first insulating layers 111 - 118 , as shown in FIG. 11A . For example, before filling the conductive material, the dielectric film 160 is formed as a lining in the space between the first insulating layers 111-118, and then the remaining space between the first insulating layers 111-118 is filled with the conductive material. . The dielectric film 160 may include high-k materials, such as aluminum oxide (Al ₂ O ₃ ), hafnium dioxide (HfO ₂ ), silicon nitride (Si ₃ N ₄ ), zirconium dioxide ( ZrO ₂ ), titanium dioxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), lanthanum oxide (La ₂ O) or other suitable materials. The dielectric film can be formed by a deposition process.

In the structures shown in FIG. 11 and FIG. 11A , the memory cells can be defined in the memory layer 135 . More specifically, memory cells can be defined in the memory layer 135 where each of the conductive layers 151 - 157 intersects with the channel layer 136 of the vertical channel structure 134 . The stack structure 150 comprising a plurality of first insulating layers 111 - 118 and a plurality of conductive layers 151 - 157 stacked alternately comprises a plurality of memory cells. A plurality of memory cells form a memory cell array.

Please refer to Figure 12. The spacers 144 are formed in the trenches 142 and the recesses 142R, specifically, the sidewalls of the spacer layer 141, the sidewalls of the conductive layers 151-157, the sidewalls of the first insulating layers 111-118, and the substrate 101 are exposed by the trenches 142. A spacer 144 is formed on the upper surface 101U, for example, formed by a deposition process. The spacer 144 may include a dielectric material, such as silicon dioxide. Next, the spacer 144 at the bottom of the trench 142 is removed to expose the upper surface 101U of the substrate 101 , for example, the spacer 144 at the bottom of the trench 142 is removed by a break-through etch process.

Referring to FIG. 13 , after the spacer 144 is formed, a conductive film 145 is formed in the trench 142 . The spacers 144 electrically isolate the conductive film 145 from the conductive layers 151 - 157 . The conductive film 145 may include polysilicon, metal or other suitable conductive materials. In one embodiment, the conductive film 145 may include tungsten. In this embodiment, the conductive film 145 extends on a plane formed by the intersection of the X axis and the Z axis, and contacts the substrate 101 . As shown in FIG. 13 , the conductive film 145 penetrates through the stack structure 150 and the dielectric layer 130 , and the spacer layer 141 is disposed between the conductive film 145 and the dielectric layer 130 .

Please refer to Figure 14. Next, an interlayer dielectric (ILD) 146 is formed on the second insulating film 139 , for example, by a deposition process.

Please refer to Figure 15. Then, contact structures 147 and 148 are formed, and the contact structures 147 and 148 are electrically connected to the vertical channel structure 134 and the conductive film 145 respectively. The vertical channel structure 134 can be electrically connected to other conductive elements through the contact structure 147 , such as electrically connected to a plurality of bit lines (not shown) above the interlayer dielectric layer 146 . The contact structures 147 and 148 may include polysilicon, metal or other suitable conductive materials.

The contact structure 147 electrically connected to the vertical channel structure 134 is disposed on the upper surface 138U of the upper plug 138 , and the contact structure 147 may not contact the dielectric layer 130 . The memory cell array is electrically connected to other conductive elements through the channel layer 136 , the upper plug 138 and the contact structure 147 , for example, electrically connected to a plurality of bit lines.

In some cases, the process of forming the contact structure 147 may deviate. For example, taking FIG. 15 as an example, the contact structure 147' is not completely aligned with the upper plug 138, and the contact structure 147' may extend toward the substrate 101 along the Z-axis direction. And contact the dielectric layer 130 . Specifically, the lower surface 147B of the contact structure 147' may be lower than the upper surface 138U of the upper plug 138, and the lower surface 147B of the contact structure 147' may be coplanar with and in direct contact with the upper surface 130U of the dielectric layer 130. In this case, the memory cell array is electrically connected to other conductive elements through the channel layer 136 and the upper plug 138, for example, electrically connected to a plurality of bit lines; or, the memory cell array is electrically connected to the contact structure 147' through the channel layer 136. electrically connected to other conductive elements, such as electrically connected to a plurality of bit lines. Even if the process of forming the contact structure 147 deviates unexpectedly (such as forming the position of the contact structure 147'), the dielectric layer 130 can avoid contact structure 147' extends to the conductive layers 151-157 of the stack structure 150 and/or contacts at least one of the conductive layers 151-157 to cause problems such as short circuit.

16 to 18 are cross-sectional views illustrating a manufacturing method of the memory device 20 according to another embodiment. The differences between the memory device 20 and the memory device 10 are described as follows.

In the manufacturing method of the memory device 10, as shown in FIG. 1 to FIG. 4, the stacked structure 110, the dielectric layer 130 and the first insulating film 131 are formed sequentially on the substrate 101, and then formed along the Z-axis. The vertical channel structure 134 runs through the stack structure 110 , the dielectric layer 130 and the first insulating film 131 ; in other words, the vertical channel structure 134 is formed after the dielectric layer 130 is formed. In the manufacturing method of the memory device 20, the stacked structure 110 is sequentially formed on the substrate 101 first, and then the vertical channel structure 134 extending through the stacked structure 110 along the Z axis is formed (as shown in FIG. 16 ), and then the stacked structure Dielectric layer 130 and first insulating film 131 are sequentially formed on 110 (as shown in FIG. 17); in other words, the formation of vertical channel structure 134 is before the formation of dielectric layer 130. As shown in FIG. The structure 134 does not penetrate the dielectric layer 130 and the first insulating film 131 .

In addition, as shown in FIG. 4, the manufacturing method of the memory device 10 includes forming a second insulating film 139 to cover the upper surface 131U of the first insulating film 131 and the vertical channel structure 134, and then performing the steps shown in FIGS. the steps shown. Since the manufacturing method of the memory device 20 does not include the formation of the second insulating film 139, the steps shown in FIG. 5 to FIG. 15 can be performed after the first insulating film 131 is formed.

The following briefly describes the manufacturing method of the memory device 20, which includes the following steps:

Please refer to Figure 16. A substrate 101 is provided. A stack structure 110 comprising first insulating layers 111 - 118 and second insulating layers 121 - 127 stacked alternately is formed on the substrate 101 . Lower plugs 133 are formed in the stack structure 110 . A vertical channel structure 134 penetrating through the stack structure 110 is formed on the lower plug 133 , and the vertical channel structure 134 includes a memory layer 135 , a channel layer 136 , an insulating pillar 137 and an upper plug 138 . Next, please refer to FIG. 17 , a dielectric layer 130 is formed on the stack structure 110 to cover the first insulating layer 118 and the vertical channel structure 134 , and the upper surface of the vertical channel structure 134 contacts the dielectric layer 130 . Then, a first insulating film 131 is formed on the dielectric layer 130 .

Next, a spacer layer 141 , a gate oxide layer 143 , conductive layers 151 - 157 , spacers 144 and a conductive film 145 are formed by steps similar to those shown in FIGS. 5 to 15 . After the conductive film 145 is formed, an interlayer dielectric layer 146 is formed on the first insulating film 131, and then the contact structures 147 and 148 electrically connected to the vertical channel structure 134 and the conductive film 145 are formed, thereby forming a structure as shown in FIG. Memory device 20 is shown.

Please refer to Figure 18. In this embodiment, the contact structure 147 electrically connected to the vertical channel structure 134 is disposed on the upper surface 138U of the upper plug 138 , and the contact structure 147 penetrates through the dielectric layer 130 . The lower surface 147B of the contact structure 147 may be coplanar with the lower surface 130B of the dielectric layer 130 .

In one embodiment, when the memory device 10/20 of the present disclosure is applied to a three-dimensional memory device, such as a NAND type memory device with a vertical channel structure, in the conductive layers 151-157 of the stack structure 150 The conductive layer 151 disposed at the bottom (bottom) can be used as a ground select line (GSL) of the memory device 10/20, and the conductive layer 157 disposed at the top of the conductive layers 151-157 can be used as a serial selection line (string select line (SSL), the conductive layers 152-156 can be used as a word line (word line; WL), and the conductive film 145 can be used as a common source line (common source line; CSL). Alternatively, the memory device 10/20 may include a plurality of serial selection lines, for example, the conductive layers 156 and 157 are both used as serial selection lines. In one embodiment, the memory device 10/20 may be a gate-all-around type memory device.

In the memory device 10 / 20 according to the present disclosure, the dielectric layer 130 is disposed above the stack structure 150 , and the material of the dielectric layer 130 is different from that of the first insulating layers 111 - 118 of the stack structure 150 . Since the etching rate of the dielectric layer 130 is different from the etching rate of the first insulating layers 111-118 (in the same etching process), the dielectric layer 130 can be used as an etching stop during the process of forming the contact structure 147/147'. layer (etch stop layer), so as to prevent the contact structure 147 / 147 ′ extending to the conductive layers 151 - 157 of the stack structure 150 along the Z-axis direction and/or contacting at least one of the conductive layers 151 - 157 to cause a short circuit and the like. In addition, the memory device 10/20 includes a spacer layer 141, and the spacer layer 141 can protect the dielectric layer 130 during the gate replacement process, so that the dielectric layer 130 will not be removed during the gate replacement process.

In a comparative example, the memory device does not include an etch stop layer, so that contact structures electrically connected to the vertical channel structures are formed above the vertical channel structures, for example, to establish electrical connections between the bit lines and the vertical channel structures. The contact structure, the contact structure will extend down to the conductive layer in the stack structure towards the substrate, causing the electrical connection to not be established correctly, and causing a short circuit problem between the bit line and the conductive layer, such as bit line and serial The short circuit problem between the selection lines further affects the yield and yield of the memory device. The memory device and its manufacturing method provided in this disclosure enable the depth of the contact structure to be properly controlled by disposing a dielectric layer as an etch stop layer on the stack structure (or it can be understood as, contact The lower surface of the contact structure can be positioned in a proper position), which can effectively reduce the short circuit problem and improve the yield and yield of the memory device. Moreover, the memory device and the manufacturing method provided by the present disclosure include a spacer layer that can protect the dielectric layer, and can prevent the dielectric layer from being damaged in the subsequent process of forming the gate electrode. In addition, the memory device and its manufacturing method provided by the present disclosure can be integrated into the existing memory device manufacturing process, which has the advantages of easy implementation and low cost.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

10: memory device

101: Substrate

111~118: the first insulating layer

130U, 138U: upper surface

130: dielectric layer

131: first insulating film

134: Vertical channel structure

135: memory layer

136: Channel layer

137: Insulation column

138: upper plug

139: second insulating film

145: Conductive film

146: interlayer dielectric layer

147, 147’, 148: contact structure

150: stacked structure

151~157: conductive layer

Claims (10)

A method of manufacturing a memory device, comprising: providing a stack structure, the stack structure includes a plurality of first insulating layers and a plurality of second insulating layers stacked alternately, the materials of the first insulating layers are different from those of the second insulating layers layer material; forming a dielectric layer on the stacked structure; forming a slit through the dielectric layer, a bottom of the slit exposes a first insulating layer disposed on the top among the first insulating layers; And a spacer layer is formed on a side wall of the slit, wherein a bottom surface of the spacer layer is formed in the first insulating layer disposed at the top among the first insulating layers. The manufacturing method according to claim 1, further comprising: forming a vertical channel structure through the stack structure, wherein the vertical channel structure is formed before the step of forming the dielectric layer on the stack structure. The manufacturing method according to claim 2, wherein an upper surface of the vertical channel structure contacts the dielectric layer. The manufacturing method as claimed in claim 1, further comprising: forming a vertical channel structure through the stacked structure, wherein the vertical channel structure is formed after the step of forming the dielectric layer on the stacked structure. The manufacturing method according to claim 4, wherein the vertical channel structure penetrates the dielectric layer, and one side surface of the vertical channel structure contacts the dielectric layer. A memory device, comprising: a stack structure, including a plurality of insulating layers and a plurality of conductive layers stacked alternately; a dielectric layer, disposed above the stack structure, the material of the dielectric layer is different from the material of the insulating layers ; a conductive film, penetrating the stacked structure and the dielectric layer; and a spacer layer, disposed between the conductive film and the dielectric layer, a bottom surface of the spacer layer is formed in the insulating layers and disposed on the top in an insulating layer. The memory device according to claim 6, further comprising: a vertical channel structure passing through the stacked structure, wherein the vertical channel structure contacts the dielectric layer. The memory device as claimed in claim 7, wherein an upper surface of the vertical channel structure contacts the dielectric layer. The memory device as claimed in claim 7, wherein a side surface of the vertical channel structure contacts the dielectric layer. The memory device as claimed in claim 7, further comprising: a contact structure disposed above the stack structure and electrically connected to the vertical channel structure, wherein the contact structure has a lower surface, the lower surface and a portion of the dielectric layer The upper or lower surface is coplanar.

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