TW202203430A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device with a cell region and a periphery region, and it includes a substrate, a capacitor over bitline (COB) dynamic random access memory (DRAM), and a multi-time programmable memory (MTP). The COB DRAM is disposed in the cell region and includes a bit line and a first capacitor. The MTP is disposed in the periphery region, and includes a floating gate formed on the substrate, a second capacitor on the floating gate, and at least one contact electrically connecting the floating gate and the second capacitor. The floating gate is a structure patterned simultaneously with the bit line, and the second capacitor is a capacitor structure manufactured simultaneously with the first capacitor.

Description

Semiconductor device and method of manufacturing the same

The present invention relates to a semiconductor technology, and more particularly, to a semiconductor device and a method of manufacturing the same.

Memory is a semiconductor device used to store information or data. It is widely used in personal computers, mobile phones, networks, etc., and has become an indispensable and important electronic product in life. As the functions of computer microprocessors are getting stronger and stronger, the programs and operations performed by software are also increasing, and the storage capacity of various data is also increasing day by day, so the demand for memory capacity is getting higher and higher.

In a traditional multi-time programmable memory (MTP) memory cell structure, a floating gate and a control gate are fabricated by doped polysilicon for erase/write operations. Recently, in order to avoid the problem of data misjudgment caused by excessive erasing/writing, one side of the memory cell is connected in series with a select transistor to form a two transistor structure, which is controlled by the select transistor. Programming and reading of memory cells.

However, since there are devices in both the cell area and the peripheral area on the wafer to be fabricated, and the fabrication processes of the memory cell and peripheral devices are usually performed separately, multiple masks and complicated process steps are required, resulting in increased cost and time.

The present invention provides a semiconductor device having a multi-time programmable memory (MTP) simultaneously fabricated with a capacitor over bitline (COB) type dynamic random access memory (DRAM), which can reduce process cost and time .

The present invention further provides a manufacturing method of a semiconductor device, which can integrate the floating gate of the MTP, the inter-gate dielectric layer and the control gate into the COB-type DRAM manufacturing process.

The semiconductor device of the present invention has a cell area and a peripheral area, including a substrate, a capacitor on bit line (COB) type dynamic random access memory (DRAM) and a multiple time programmable memory (MTP). The COB-type DRAM is disposed in the cell region and includes a bit line and a first capacitor. The MTP is disposed in the peripheral region, and includes a floating gate formed on the substrate, a second capacitor located on the floating gate, and at least one contact window electrically connecting the floating gate and the second capacitor . The floating gate is a structure patterned at the same time as the bit line, and the second capacitor is a capacitor structure fabricated at the same time as the first capacitor.

In an embodiment of the present invention, the MTP may further include a tunnel oxide layer located between the substrate and the floating gate.

In an embodiment of the present invention, the material of the floating gate includes doped polysilicon or polysilicon metal.

In an embodiment of the present invention, the MTP may further include a metal film formed on the surface of the floating gate and in direct contact with the contact window.

In an embodiment of the present invention, the metal film and the bit line are structural layers deposited simultaneously.

In an embodiment of the present invention, the first capacitor includes a first lower electrode, a first dielectric layer and a first upper electrode, and the second capacitor includes a second lower electrode, a second dielectric layer and a second upper electrode , wherein the second lower electrode is an electrode structure fabricated at the same time as the first lower electrode, and the second upper electrode is an electrode structure fabricated at the same time as the first upper electrode.

In an embodiment of the present invention, the above-mentioned semiconductor device may further include a zero-th metal layer between the second lower electrode and the contact window and in direct contact with the contact window.

In an embodiment of the present invention, the first capacitor and the second capacitor have a structure with a groove, and the first upper electrode and the second upper electrode each include an upper electrode layer located above the groove and a filling Conductive material within the groove and below the upper electrode layer.

In an embodiment of the present invention, the conductor material includes polysilicon or polysilicon, and the conductor material in the second capacitor is used as the control gate of the MTP.

In an embodiment of the present invention, the number of grooves in the second capacitor is multiple, which can form parallel capacitors.

In an embodiment of the present invention, the second dielectric layer and the first dielectric layer are high dielectric constant materials.

In an embodiment of the present invention, the thickness of the second dielectric layer may be greater than the thickness of the first dielectric layer.

In an embodiment of the present invention, the number of the above-mentioned second capacitors is plural, which can constitute capacitors connected in series.

A method of manufacturing a semiconductor device of the present invention includes forming a DRAM element of a capacitor on bit line (COB) type dynamic random access memory (DRAM) in a cell region, the DRAM element including a bit line. A floating gate is formed in the peripheral region, and the floating gate is a structure patterned simultaneously with the bit line. At least one contact window is formed on the floating gate, and then a first capacitor and a second capacitor are simultaneously fabricated, the first capacitor is formed on the DRAM element, and the second capacitor is formed on the contact window. The second capacitor is electrically connected to the floating gate through the contact window, so that the floating gate, the contact window and the second capacitor constitute a multi-time programmable memory (MTP).

In another embodiment of the present invention, a tunnel oxide layer may also be formed on the substrate in the peripheral region before forming the floating gate.

In another embodiment of the present invention, after the floating gate is formed, a metal film may also be formed on the surface of the floating gate.

In another embodiment of the present invention, the method for simultaneously fabricating the first and second capacitors includes simultaneously fabricating the first lower electrode of the first capacitor and the second lower electrode of the second capacitor, and forming the first lower electrode on the first lower electrode. The first dielectric layer and the second dielectric layer are formed on the second lower electrode, and then the first upper electrode of the first capacitor is formed on the first dielectric layer and the second dielectric layer is formed on the second dielectric layer at the same time. the second top electrode of the capacitor.

In another embodiment of the present invention, a groove structure may be formed on the DRAM element and the floating gate before the first and second capacitors are simultaneously fabricated.

In another embodiment of the present invention, the method for forming the first upper electrode and the second upper electrode includes filling a conductor material in the groove structure, and then forming an upper electrode layer on the conductor material, and the above The conductor material in the second capacitor acts as the control gate of the MTP.

In another embodiment of the present invention, the number of the above-mentioned groove structures formed on the floating gate is, for example, multiple.

In another embodiment of the present invention, the first dielectric layer and the second dielectric layer are formed simultaneously.

In another embodiment of the present invention, the first dielectric layer and the second dielectric layer are formed separately, and the thickness of the second dielectric layer is greater than that of the first dielectric layer.

In another embodiment of the present invention, a zeroth metal layer may be formed on the contact window before the first and second capacitors are simultaneously fabricated.

In another embodiment of the present invention, the number of the above-mentioned second capacitors is multiple and connected in series with each other.

Based on the above, the present invention can integrate the floating gate, the inter-gate dielectric layer and the control gate of the multi-time programmable memory into the process of the capacitor dynamic random access memory on the bit line through a specific process. , thus not only increasing the possibility of process integration, but also further reducing process time and cost.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention, wherein the left side of FIG. 1 shows a capacitor over bitline (COB) type dynamic random access formed in a cell region Memory (DRAM), shown on the right in Figure 1 is a multi-time programmable memory (MTP) formed in the peripheral area.

Referring to FIG. 1 , the semiconductor device of the first embodiment has a cell region and a peripheral region, and includes a substrate 10 , a COB-type DRAM 100 a and an MTP 100 b.

In FIG. 1, the COB type DRAM 100a is disposed in the cell area, and includes a first capacitor 102, wherein the first capacitor 102 includes a first lower electrode 104, a first dielectric layer 106 and a first upper electrode 108, and the first lower The electrode 104 is, for example, Ti/TiN, and the first dielectric layer 106 is, for example, a high-k material. Since the first capacitor 102 may have a structure with the groove 110 , the first upper electrode 108 may further include the upper electrode layer 112 located above the groove 110 and the upper electrode layer 112 filled in the groove 110 and located below the upper electrode layer 112 . The conductor material 114, wherein the upper electrode layer 112 is such as a tungsten layer, and the conductor material 114 is such as polysilicon or polysilicon metal. The MTP 100b is disposed in the peripheral region, and includes a floating gate (FG) 116 formed on the substrate 10 , a second capacitor 118 located on the floating gate 116 , and electrically connecting the floating gate 116 and the second capacitor At least one contact window 120 of 118 . The floating gate 116 may include a conductor layer 122 (material such as doped polysilicon or polysilicon metal) and a metal film 124 (material such as tungsten) above it, while the contact 120 is such as a tungsten plug.

Please continue to refer to FIG. 1 , the second capacitor 118 of the MTP 100 b is a capacitor structure fabricated at the same time as the first capacitor 102 , wherein the second capacitor 118 includes a second lower electrode 126 , a second dielectric layer 128 and a second upper electrode 130 , Furthermore, the second lower electrode 126 is an electrode structure fabricated at the same time as the first lower electrode 104 , the second upper electrode 130 is an electrode structure fabricated at the same time as the first upper electrode 108 , and the second dielectric layer 128 may also be connected to the first dielectric layer. Layer 106 is fabricated simultaneously. Therefore, the second lower electrode 126 and the first lower electrode 104 can also be made of Ti/TiN, and the second dielectric layer 128 and the first dielectric layer 106 can also be made of high dielectric constant materials. In one embodiment, since the MTP 100b may withstand a large voltage, the second dielectric layer 128 can also be fabricated separately from the first dielectric layer 106 , so that the thickness t2 of the second dielectric layer 128 is greater than that of the first dielectric layer 106 thickness t1.

The COB-type DRAM 100a generally further includes DRAM elements 132 located under the first capacitor 102, such as bit lines 134 (eg, metal wires), buried word lines 136 in the substrate 10, doped regions 138 on the surface of the substrate 10, The bit line contacts 140 (eg, tungsten plugs) electrically connecting the bit lines 134 and the doped regions 138 , the storage node contacts 142 electrically connecting the first lower electrodes 104 and the other doped regions 138 , and the like. However, the present invention is not limited thereto, and any DRAM device known in the field of COB DRAM can be used in the present invention. In addition, an insulating layer 144 (eg, an oxide layer) for electrical isolation and inner layer dielectric layers (ILD) 146a, 146b, 146c, 146d, etc. exist in the above structure. A first metal layer M1 may be disposed above the first capacitor 102 to be electrically connected to the upper electrode layer 112 through a contact window 148 (eg, a tungsten plug), and an active region isolation structure 150 (eg, STI) is provided in the substrate 10 .

Please continue to refer to FIG. 1 , since the first capacitor 102 has a structure with a groove 110 , the second capacitor 118 can also have a structure with a groove 152 , but the size of the groove 152 and the groove 110 is determined according to the design of the photomask , so the size and shape of the two can be the same or different. For example, the grooves 152 and 110 have cylindrical walls, but the diameter of the grooves 152 can be larger or smaller than the diameter of the grooves 110 , and the number of the grooves 152 can be designed as one or more according to requirements. As for the second upper electrode 130 and the first upper electrode 108, since they are fabricated at the same time, they can also include the upper electrode layer 112 located above the groove 152 and the conductive material 114 filled in the groove 152 and located below the upper electrode layer 112. , and the conductor material 114 in the second capacitor 118 acts as the control gate (CG) of the MTP 100b.

In FIG. 1 , the MTP 100 b generally further includes a tunneling oxide layer 154 between the substrate 10 and the floating gate 116 , and can be formed in the substrate 10 on both sides of the floating gate 116 as a Doped regions 156 for source and drain. The metal film 124 of the MTP 100b of the first embodiment can also be fabricated at the same time as the bit line 134 of the DRAM element 132, so the material of the bit line 134 can be the same as that of the metal film 124. For example, after the bit line contact window 140 is formed, the tunnel oxide layer 154 and the conductor layer 122 can be formed in the peripheral area first, and then a metal film can be formed on the entire substrate 10, and then patterned to obtain During the step of floating the gate electrode 116 , the above-mentioned metal film is patterned at the same time to form the bit line 134 of the DRAM element 132 . Moreover, the control gate of the MTP 100b can not only be fabricated at the same time as the capacitor of the COB DRAM, but its structure can also be integrated into the general semiconductor process, and includes the zeroth metal layer M0 between the second lower electrode 126 and the contact window. 120, and in direct contact with the contact window 120. In addition, both the interlayer dielectric layers 146b and 146c for electrical isolation in the COB DRAM 100a and the MTP 100b can be fabricated simultaneously. A first metal layer M1 may also be disposed above the second capacitor 118 and electrically connected to the upper electrode layer 112 through the contact window 148 . The aforementioned structures with the same reference numerals can be formed by the same process to simplify the process. However, the present invention is not limited to this, and can also be formed by different processes.

2A to 2J are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

Referring to FIG. 2A first, the active region isolation structure 202 is formed in the substrate 20 of the peripheral region 200a and the cell region 200b, and then the doped region 204 is formed in the substrate 20 of the cell region 200b. Then, buried word lines 206 are formed in the substrate 20 of the cell region 200b, and an insulating layer 208 may be formed before the buried word lines 206 are formed.

Then, referring to FIG. 2B , after forming an inner layer dielectric layer 210 on the substrate 20 of the unit region 200b, bit line contact windows 212 are formed in the inner layer dielectric layer 210; in addition, on the substrate 20 of the peripheral region 200a A tunnel oxide layer 214 and a conductor layer 216 are formed. Next, a metal film is fully deposited on the substrate 20 of the peripheral region 200a and the cell region 200b, wherein the metal film 218a of the cell region 200b can be used as a bit line, and the metal film 218b of the peripheral region 200a can be used as a floating gate of the MTP part to facilitate subsequent electrical characteristics.

Then, referring to FIG. 2C, the metal film 218a of the cell region 200b and the metal film 218b of the peripheral region 200a are patterned to form the bit line 218c of the cell region 200b, and the conductor layer 216 and the through-holes under the metal film 218b are continuously removed by etching. The tunnel oxide layer 214 is formed to form the floating gate 220 of the peripheral region 200a. Then, doped regions 222 serving as source and drain electrodes are formed in the substrate 20 of the peripheral region 200a.

Next, referring to FIG. 2D , the entire surface of the substrate 20 is covered with an interlayer dielectric layer 224 .

Then, referring to FIG. 2E, at least one contact window 226 electrically connected to the floating gate 220 is formed in the ILD 224 of the peripheral region 200a, wherein the contact window 226 is, for example, a tungsten plug, and can be connected to the metal film 218b. direct contact. In addition, a contact window 228 in contact with the doped region 222 may be formed at the same time as or before or after the formation of the contact window 226 . In addition, a storage node contact window 230 connected to the doped region 204 can be formed in the cell region 200b, and an insulating layer 232 isolated from the bit line 218c can be formed before the storage node contact window 230 is formed, so as to complete the COB type Fabrication of the DRAM element 234 of the DRAM. However, the present invention is not limited to this. According to the structural design of the existing DRAM device 234, other steps may be added to the above process. Next, a zeroth metal layer M0 may be formed on the ILD 224 and electrically connected to the floating gate 220 through the contact window 226 and the metal film 218b. The zeroth metal layer M0 may also be in contact with the contact window 228 .

After that, referring to FIG. 2F , another ILD 500 can be formed on the ILD 224 of the peripheral region 200 a and the cell region 200 b , and then the ILD 500 can be formed on the DRAM element 234 and the internal layer above the floating gate 220 A groove structure 502 is formed in each of the dielectric layers 500, wherein the groove structure 502 of the peripheral region 200a exposes the zeroth metal layer M0 above the floating gate 220, and the groove structure 502 of the cell region 200b exposes the storage node contact window 230 . Although the peripheral region 200a in FIG. 2F shows one groove structure 502, the present invention is not limited thereto, and the number of groove structures 502 formed on the floating gate 220 may also be multiple.

Then, referring to FIG. 2G , a conductor layer 504 , such as Ti/TiN, which is conformal to the groove structure 502 , is formed on the entire surface of the substrate 20 .

2H, the conductor layer 504 outside the groove structure 502 of the peripheral region 200a and the cell region 200b is removed, and what remains is the first lower electrode 504a of the cell region 200b and the second lower electrode 504b of the peripheral region 200a. The method of removing the conductor layer 504 other than the groove structure 502 is, for example, to directly remove the conductor layer 504 other than the groove structure 502; The mask layer is removed until the conductor layer 504 is exposed, and then the exposed conductor layer 504 is removed, leaving the first lower electrode 504 a and the second lower electrode 504 b in the groove structure 502 .

After that, referring to FIG. 2I, a first dielectric layer 506a and a second dielectric layer 506b are formed. In this embodiment, the first dielectric layer 506a of the cell region 200b and the second dielectric layer 506b of the peripheral region 200a are formed simultaneously, so the materials are the same (eg high dielectric constant material) and the thickness is also the same . However, in another embodiment, the first dielectric layer 506a and the second dielectric layer 506b are formed separately, and the thickness of the second dielectric layer 506b in the peripheral region 200a may be greater than that of the first dielectric layer in the cell region 200b thickness of layer 506a for high voltage operation. Then, a conductor material 508 (such as polysilicon or polysilicon metal) is filled into the groove structure 502 at the same time, and an upper electrode layer 510 is formed on the conductor material 508, wherein the conductor material 508 of the cell region 200b and the upper electrode layer 510 form the first electrode layer 510. An upper electrode 512, thus the first capacitor 520 formed by the first lower electrode 504a, the first dielectric layer 506a and the first upper electrode 512 has been completed.

Next, referring to FIG. 2J, the structure on the inner layer dielectric layer 500 of the peripheral region 200a is patterned to form a second lower electrode 504b, a second dielectric layer 506b and a second upper electrode 514 (including the conductor material 508a and The second capacitor 522 formed by the upper electrode layer 510a), and the conductor material 508a in the second capacitor 522 is used as the control gate of the MTP.

In FIG. 2J , the first capacitor 520 is formed on the DRAM element 234 and the second capacitor 522 is formed on the contact window 216 . The second capacitor 522 is electrically connected to the floating gate 220 through the contact window 216 , so that the floating gate 220 , the contact window 226 and the second capacitor 522 form a multi-time programmable memory (MTP). Furthermore, it can be seen from the above description that the floating gate, the inter-gate dielectric layer and the control gate of the MTP can be integrated into the COB DRAM process in this embodiment.

3 is a schematic cross-sectional view of an MTP in a semiconductor device according to a third embodiment of the present invention, wherein the same reference numerals as those on the right side of FIG. 1 are used to denote the same or similar components, and the content of the same or similar components can also be referred to The above will not be repeated.

Referring to FIG. 3 , the present embodiment increases the capacitive coupling ratio by increasing the number of grooves 152 on the floating gate 116 . In detail, if the grooves 152 become plural, the size of the floating gate 116 (eg, the conductor layer 122 and the metal film 124 ) may become larger, and the number of the contact windows 120 may be increased, so that the second capacitors 300 are connected in parallel of multiple capacitors.

4 is a schematic cross-sectional view of an MTP in a semiconductor device according to a fourth embodiment of the present invention, wherein the same reference numerals as those on the right side of FIG. 1 are used to denote the same or similar components, and the content of the same or similar components can also be referred to The above will not be repeated.

Referring to FIG. 4 , in this embodiment, a plurality of second capacitors 400 connected in series are formed to achieve the effect of voltage reduction. Except for the second capacitor 400 directly above the floating gate 116 , other second capacitors 400 can use the zeroth The metal layer M0 is used to connect the circuits in series, and is finally connected to the first metal layer M1.

To sum up, the present invention integrates the floating gate, the inter-gate dielectric layer and the control gate of the MTP into the COB DRAM process, thereby reducing the process time and cost.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10, 20: Substrate 100a: COB DRAM 100b: MTP 102, 520: The first capacitor 104, 504a: the first lower electrode 106, 506a: first dielectric layer 108, 512: The first upper electrode 110, 152: groove 112, 510, 510a: upper electrode layer 114, 508, 508a: Conductor materials 116, 220: floating gate 118, 300, 522: Second capacitor 120, 148, 226, 228: Contact window 122, 216, 504: Conductor layer 124, 218a, 218b: metal film 126, 504b: the second lower electrode 128, 506b: the second dielectric layer 130, 514: Second upper electrode 132, 234: DRAM components 134, 218c: bit line 136, 206: Buried word line 138, 156, 204, 222: doped regions 140, 212: bit line contact window 142, 230: Storage node contact window 144, 208, 232: insulating layer 146a, 146b, 146c, 146d, 210, 224, 500: inner dielectric layer 150: Active Zone Isolation Structure 154, 214: Tunneling oxide layer 200a: Surrounding area 200b: Unit Area 502: groove structure M0: zeroth metal layer M1: first metal layer t1, t2: thickness

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 2A to 2J are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention. 3 is a schematic cross-sectional view of an MTP in a semiconductor device according to a third embodiment of the present invention. 4 is a schematic cross-sectional view of an MTP in a semiconductor device according to a fourth embodiment of the present invention.

10: Substrate

100a: COB DRAM

100b: MTP

102: First capacitor

104: The first lower electrode

106: first dielectric layer

108: The first upper electrode

110, 152: groove

112: Upper electrode layer

114: Conductor material

116: floating gate

118: Second capacitor

120, 148: Contact window

122: Conductor layer

124: metal film

126: Second lower electrode

128: Second Dielectric Layer

130: Second upper electrode

132: DRAM components

134: bit line

136: Buried word line

138, 156: Doping region

140: bit line contact window

142: Storage node contact window

144: Insulation layer

146a, 146b, 146c, 146d: inner dielectric layers

150: Active Zone Isolation Structure

154: Tunneling oxide layer

t1, t2: thickness

M0: zeroth metal layer

M1: first metal layer

Claims (24)

A semiconductor device having a cell region and a peripheral region, the semiconductor device comprising: substrate; A capacitor over bitline (COB) type dynamic random access memory (DRAM) is disposed in the cell region, and the COB type DRAM includes a bit line and a first capacitor; and A multi-time programmable memory (MTP) is arranged in the peripheral area, wherein the MTP includes: A floating gate, formed on the substrate, is a structure patterned simultaneously with the bit line; a second capacitor on the floating gate, a capacitor structure fabricated at the same time as the first capacitor; and At least one contact window is electrically connected to the floating gate and the second capacitor. The semiconductor device of claim 1, wherein the MTP further comprises a tunnel oxide layer located between the substrate and the floating gate. The semiconductor device of claim 1, wherein the material of the floating gate comprises doped polysilicon or polysilicon metal. The semiconductor device of claim 1, wherein the MTP further comprises a metal film formed on the surface of the floating gate electrode and in direct contact with the at least one contact window. The semiconductor device of claim 4, wherein the metal film and the bit line are structural layers deposited simultaneously. The semiconductor device of claim 1, wherein the first capacitor includes a first lower electrode, a first dielectric layer and a first upper electrode, and the second capacitor includes a second lower electrode, a second dielectric layer and The second upper electrode, the second lower electrode is an electrode structure fabricated at the same time as the first lower electrode, and the second upper electrode is an electrode structure fabricated at the same time as the first upper electrode. The semiconductor device of claim 6, further comprising a zeroth metal layer interposed between the second lower electrode and the at least one contact window and in direct contact with the at least one contact window. The semiconductor device of claim 6, wherein the first capacitor and the second capacitor are structures having grooves, and each of the first upper electrode and the second upper electrode comprises: an upper electrode layer over the groove; and A conductor material is filled into the groove and located under the upper electrode layer. The semiconductor device of claim 8, wherein the conductor material comprises polysilicon or polysilicon, and the conductor material in the second capacitor acts as a control gate of the MTP. The semiconductor device of claim 8, wherein the number of the grooves in the second capacitor is plural to form a parallel capacitor. The semiconductor device of claim 6, wherein the second dielectric layer and the first dielectric layer are high dielectric constant materials. The semiconductor device of claim 6, wherein the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer. The semiconductor device according to claim 1, wherein the number of the second capacitors is plural to constitute capacitors connected in series. A method of manufacturing a semiconductor device, comprising: forming a DRAM element of a capacitor over bitline (COB) type dynamic random access memory (DRAM) in the cell region, the DRAM element comprising a bit line; A floating gate is formed in the peripheral region, and the floating gate is a structure patterned simultaneously with the bit line; forming at least one contact window on the floating gate; A first capacitor and a second capacitor are fabricated at the same time, the first capacitor is formed on the DRAM element, the second capacitor is formed on the at least one contact window, and is electrically connected to the at least one contact window through the at least one contact window. the floating gate, so that the floating gate, the at least one contact window and the second capacitor form a multi-time programmable memory (MTP). The method for manufacturing a semiconductor device according to claim 14, wherein before forming the floating gate, the method further comprises: forming a tunnel oxide layer on the substrate in the peripheral region. The method for manufacturing a semiconductor device according to claim 14, wherein after forming the floating gate electrode, the method further comprises: forming a metal film on the surface of the floating gate electrode. The method for manufacturing a semiconductor device according to claim 14, wherein the method for simultaneously manufacturing the first capacitor and the second capacitor comprises: Simultaneously making the first lower electrode of the first capacitor and the second lower electrode of the second capacitor; forming a first dielectric layer on the first lower electrode; forming a second dielectric layer on the second lower electrode; and At the same time, a first upper electrode of the first capacitor is formed on the first dielectric layer and a second upper electrode of the second capacitor is formed on the second dielectric layer. The method for fabricating a semiconductor device according to claim 17, wherein before simultaneously fabricating the first capacitor and the second capacitor, the method further comprises: forming a groove structure on the DRAM element and on the floating gate, respectively. The method for manufacturing a semiconductor device according to claim 18, wherein the method for forming the first upper electrode and the second upper electrode comprises: Filling the groove structure with conductor material; and An upper electrode layer is formed on the conductor material, and the conductor material in the second capacitor acts as a control gate of the MTP. The method of manufacturing a semiconductor device according to claim 18, wherein the number of the groove structures formed on the floating gate is plural. The method of manufacturing a semiconductor device according to claim 17, wherein the first dielectric layer and the second dielectric layer are formed simultaneously. The method of manufacturing a semiconductor device according to claim 17, wherein the first dielectric layer and the second dielectric layer are formed separately, and the thickness of the second dielectric layer is larger than that of the first dielectric layer thickness of the electrical layer. The method for manufacturing a semiconductor device according to claim 14, wherein before simultaneously fabricating the first capacitor and the second capacitor, the method further comprises: forming a zeroth metal layer on the at least one contact window. The method of manufacturing a semiconductor device according to claim 14, wherein the number of the second capacitors is plural and connected in series with each other.

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