1239099 九、發明說明： 【發明所屬之技術領域】 本發明係概括關於一種非揮發性記憶體(non-v〇latile mem〇ry，NVM)單元及其製作方法，尤指一種可抹除式非揮 發性記憶單元及其製作方法。 【先如技術】 非揮發性記憶體是積體電路中常用來儲存資料的元件 之一，其最重要的特性便是存入非揮發性記憶體中的資料 不會因為電源供應的中斷而消失。廣義地講，硬碟機、可 抹除且可私式唯頃5己憶體（erasable programmable read-only memory, EPROM)、可電除且可程式唯讀記憶體（electrically erasable programmable read-only memory，EEPROM)以及快 閃記憶體(flash me腦ry)等記憶裝置都可以算是非揮發性 記憶體，因其所儲存的資料在未被供予電源的情況下仍能 保存。 依據記憶體之讀寫次數的限制，非揮發性記憶體可以分 為多次可程式化記憶體(multi-time programmable memory， MTP memory)以及單次可程式化記憶體（one_time programmable memory，OTP memory)兩種。MTP 記憶體具 有可重覆讀寫的功能，例如EEPROM以及快閃記憶體等， 在設計上必須搭配一些相關的電路，以支援資料寫入、抹 1239099 除以及讀取等不同操作。OTP記憶體僅能提供單次的資料 寫入，因此不需要抹除功能的電路，而僅需搭配具程式化 和讀取功能的電路即可正常運作。因此，用來控制OTP記 憶體操作的電路會較用來控制MTP記憶體操作的電路簡 單許多，以達到簡化製造程序以及降低製造成本等優點。 為了提高OTP記憶體在實際應用上的可行性，OTP記憶體 可以利用類似EPROM之抹除方式（紫外線照射）來抹除内 部儲存的資料，然而目前亦有人提出可利用簡單的電路設 計來控制OTP記憶體，使OTP記憶體也可以提供數次資料 重覆讀寫的功能。 MTP記憶單元以及OTP記憶單元的結構設計具有類似 的堆疊結構，包含一用來儲存電荷的浮動閘極，一絕緣層 (例如由一氧化層、一氮化矽層以及一矽氧層組成之ΟΝΟ 複合絕緣層），以及一用來控制資料存取的控制閘極。記憶 單元的操作可以利用類似電容的原理，將感應電荷儲存於 浮動閘極中，以改變記憶單元的起始電壓（threshold voltage， Vth)，達到儲存0或1等資料之目的。· 請參考第1圖，第1圖為習知一非揮發性記憶單元的剖 面示意圖。如第1圖所示，非揮發性記憶單元包含有一基 底10, 一 P型摻雜井12設於基底10表面，一由絕緣層14、 浮動閘極16、絕緣層18以及控制閘極20組成的堆疊結構 1239099 設於P型摻雜井12表面，以及一 N型掺雜區域22設於前 述堆疊結構周圍之P型摻雜井12表面。一般而言，浮動閘 極16以及控制閘極20均係由摻雜多晶矽形成，浮動閘極 16下方之絕緣層14係用來作為一隧穿氧化層，而介於浮 動閘極16與控制閘極20間之絕緣層18則可由ΟΝΟ複合 絕緣層形成。此外，浮動閘極16兩側的Ν型摻雜區域22 係用來作為一汲極以及一源極，以控制非揮發性記憶單元 之寫入、抹除以及讀取等操作。 為了提高元件積集度，在美國專利第6207507號更提出 一種多層次非揮發性記憶單元之結構設計。請參考第2 圖，第2圖為習知一多層次非揮發性記憶單元的剖面示意 , ...-~'…—~ 圖。如第2圖所示，多層次非揮發性記憶單元包含有一基 底30，一 Ρ型摻雜井32設於基底30表面，一絕緣層34 以及一絕緣層38設於Ρ型摻雜井32表面並用來隔離三個 相鄰的浮動閘極36a、36b以及36c。此外，多層次非揮發 性記憶單元另包含有一用來提供源極與汲極的N型摻雜區 域40設於浮動閘極36b以及浮動閘極36c周圍之P型摻雜 井32表面，一絕緣層42覆蓋於浮動閘極36a、36b、36c 以及N型摻雜區域40表面，以及一控制閘極44覆蓋於絕 緣層42表面。由於多層次非揮發性記憶單元包含有三個浮 動閘極36a、36b、36c，可以儲存二位元的二進位資料，例 如00、01、10或11，因此可以提高記憶單元之積集度。 1239099 習知非揮發性記憶單元大多係利用福樂漢諾隨穿 (Fowler Nordheim tunneling)技術來抹除非揮發性記憶單元 中儲存的資料，在進行抹除操作時，隧穿氧化層（例如第工 圖之絕緣Μ 14或第2圖之絕緣層34、38)之電場至少必須 達到W f萬伏W公分(MW⑽)之要求，為了避免施加高電 壓對元件造成破壞，因此通常會減少隧穿氧化層的厚度至 約介於80至120埃之範圍内，以滿足高電場之要求。受限 於隧穿氧化層的厚度以及摻雜濃度等條件，目前在非揮發 性記憶體製程上大多僅與周邊電路區域之低壓金氧半導體 電晶體製程結合（閘極氧化層之厚度約為7〇埃），無法進二 步整合至其他更高電壓操作之金氧半導體電晶體製程。 【發明内容】 因此，本發明之目的即在提供一種新的非揮發性記情單 元結構及其製作方法，可以將非揮發性記憶單元之製程整 合至高壓金氧半導體電晶體與低壓金氧半導體電晶體之昆 合机?虎製程中。 在本發明之較佳實施例中，非揮發性記憶單元包含有_ 基底，一第一隔離結構設於基底表面之一第一區域内，_ 第二隔離結構設於基底表面之一第二區域周圍，一控制間 極設於第一區域内之第一隔離結構表面，一第一絕緣芦< 1239099 於控制閘極表面，一第二絕緣層設於第二區域内之基底表 面，以及一浮動閘極設於第一絕緣層與第二絕緣層表面。 由於本發明係將浮動閘極設於控制閘極上方，因此本發 明可以先完成控制閘極之製程，再將非揮發性記憶單元之 隧穿氧化層、浮動閘極以及源極/汲極等製程整合至高壓金 氧半導體電晶體與低壓金氧半導體電晶體之混合訊號製程 中，有利於製程條件之控制與簡化。此外，本發明係將控 制閘極設於隔離結構表面，因此可以降低非揮發性記憶單 元操作時於基底表面產生之漏電流。 【實施方式】 請參考第3圖，第3圖為本發明一非揮發性記憶單元的 俯視圖。如第3圖所示，本發明之非揮發性記憶單元包含 有一基底50,且基底50表面定義有一第一區域I以及一第 二區域II。第一區域I係用來形成一控制閘極52與一浮動 閘極54之堆疊結構，其中浮動閘極54係覆蓋於控制閘極 52上方，且浮動閘極54包含有一開口 56暴露出部分之控 制閘極52表面，以提供導線結構連接至控制閘極52。第 二區域II係用來形成浮動閘極54與源極/汲極等N型摻雜 區域5 8。 為了進一步說明本發明非揮發性記憶單元之結構，請參 1239099 考第4圖至第6圖，其中第4圖為第3圖所示之非揮發性 記憶單元沿切線AA’之剖面示意圖，第5圖為第3圖所示 之非揮發性記憶單元沿切線BB’之剖面示意圖，且第6圖 為第3圖所示之非揮發性記憶單元沿切線CC’之剖面示意 圖。如第4圖所示，非揮發性記憶單元於第一區域I包含 有一 P型摻雜井60設於基底50表面，一隔離結構62設於 P型摻雜井60表面，以及由控制閘極52、絕緣層64、浮 動閘極54組成的堆疊結構設於隔離結構62上方。在本發 明之較佳實施例中，基底50係為一 P型矽基底，絕緣層 64係為一氧化層、一氮化石夕層以及一矽氧層組成之ΟΝΟ 複合絕緣層，控制閘極52以及浮動閘極54係由摻雜多晶 矽或其他導電材料形成，至於隔離結構62則可為場氧化層 (field oxide)或淺溝隔離（shallow trench isolation, STI)結 構。然而本發明並不限定於此，基底50、P型摻雜井60以 及N型摻雜區域58亦可視實際設計調整為其他導電型式， 或者亦可以於P型摻雜井60周圍形成一 N型深摻雜井 (deep N_well)，以提供一保護環(guard ring)。此外，絕緣層 64亦可由其他耐高壓之絕緣材料形成。 如第5圖所示，非揮發性記憶單元於第二區域II包含有 一絕緣層66設於浮動閘極54下方之P型摻雜井60表面， N型摻雜區域58設於浮動閘極.54周圍之P型摻雜井60表 面，以及複數個隔離結構62設於N型摻雜區域58周圍之 1239099 ι=:γ〇表面。絕緣層⑺係用來作為隨穿氧化層， :旱又約"於9G至12G埃之間。N型摻雜區域58係用來 作^揮發性記憶單元之源極歧極，並於浮動賴^下 方疋義出一通道區域。 太 '第6圖所不’非揮發性記憶單元之浮動閘極54係橫 Ϊ於弟一區域1之絕緣層64上方以及於第二區域11之絕緣 二66上Γ浮動閘極54下方係為一通道區域，且隔離結 構62係環繞於通道區域周圍。 驾 > 、表1為本發明—非揮發性記憶單元於進行 取:各項操作時之—^ 之控制時，储轉純記憶單元 同時使源極58與基底=也於沒極58施加一正電壓， 浮動閘極54巾，此時非 1利於電子射人並儲存於 至7〜9伏特。於進行抹除摔作：：之軸 極％係施加-高電壓，抑；^，非揮發性記憶單元之源 子 極58則設於-浮接狀態:=52與基 ，此時非揮發性師單元,4移除浮動閘極54中之電 ^〜2伏特。於讀取操作日士起始電壓被還原至原始值， 原始起始電壓〇〜2伏特^ 技制閘極52係施加一介於 電壓值，例如2.5〜4伏牲以及寫入起始電壓(7〜9伏特）間之 、/及極5 8係施加一正電壓， 1239099 58與基底50則係接地 請參考第7圖至第10圖，第7圖至楚 作-非揮發性記憶單元之方法示圖為本發明製 發明方法係先提供一基底50，例如p第7圖所示，本 -掺雜製程，於基底5G表面形成—石夕基底，接著進行 於基底50表面形成一絕緣層68以及一 雜井60。接著 層68可為一墊氧化層，遮罩70可為罩7〇，例如絕緣 用-微影暨蝕刻製程來定義遮罩7〇之氮化矽層’隨後利 成隔離結構62的絕緣層68表面。然㈤案以暴露出欲形 使水氣以及氧氣擴散進入絕緣層68及p〆 …、乳化法 以形成複數個隔離結構62,同時對彳摻雜井60内， 之較佳貫施例中，隔 驟形成為場氧化層，然而隔 之離子進行趨入(drive-in)。在本發明 里払雜井60内 離結構62係可利用前述方法步 離結構62亦可利用淺溝隔離製程带 少战為淺溝隔離結構。 如第8圖所示，接著去除遮罩7n、 以及絕緣層^ 基底50表面形成一絕緣層72，你u - ⑽並於 度約為300〜500埃。隨後於基底5〇矣 曰幸父L厚 一 衣面沉積一換雜夕日 層（未顯示於圖中），並利用絕緣層72作、、夕_夕曰曰矽 進行一微影暨蝕刻製程去除部分之撿施為蝕刻停止層， ^雜多晶秒層， 離結構62上方定義出控制閘極52 w圖案。 12 1239099 如第9圖所示，接著於控制閘極52表面形成一絕緣層 64 ’在本發明之較佳實施例中，絕緣層64係為一 ΟΝΟ絕 緣層，其形成方法介紹如下：進行一熱氧化製程，以於基底 50表面形成一約為5〇〜7〇埃的氧化層，用來當作底氧化 :并„行_低壓化學氣相沈積製程，於底氧化層表面 =—厚度約為200〜350埃之氮化石夕層；接著於.950ν 咼溫環境中，谁4 、乃〇 C之 進仃一回火製程30分鐘以修補h 厚度為5〇〜70拄夕访与a A 石二/w表面你上 微影暨蝕刻萝浐—蓋山， 層，最後再4丨 版私疋義出絕緣層64的圖案。曼再利用 -厚2==:;式氧化而在氮切層Γ的結 —緣層72後，仍如 形成絕緣層66,用來作二再於基底5〇* 面全面沉積1雜多晶二：如，基底50 刻製程去除部分之摻：厶？所示 出如第3圖所示 ^痛夕曰曰矽層74 二，二側壁上形成-側 型摻雜區域乂用來作A 作。 _ 元成非揮發性記憶單為' :參考第11圖至第20圖，第 “至一㈣金氧半導2 13 1239099 體以及一低壓金氧半導體電晶體之製程的方法示意圖。如 第11圖所示，本發明方法係先提供一基底100,例如P型 矽基底，且基底100表面包含有一用來製作非揮發性記憶 單元之NVM cell區域’一用來製作高壓金氧半導體電晶體 之高壓區域HV，以及一用來製作低壓金氧半導體電晶體之 低壓區域LV。接著於基底1〇〇表面形成一墊氧化層（未顯 不於圖中），並利用N型摻質進行一覆蓋式摻雜(bianket implant) ’以於低壓區域lv中形成一N型摻雜井102，於 咼壓區域HV中形成一 n型摻雜井1〇4，以及於NVM cell 區域中形成一 N型摻雜井（未顯示於圖中）。之後於基底1〇〇 表面沉積一厚度約為1000埃之氮化矽層（未顯示於圖中）， 並進行一回蝕刻製程，以於氮化矽層中形成複數個開口， 用來定義預定形成隔離結構之區域（亦即定義出主動區 域）。接著利用P型摻質進行摻雜，以於NVM cell區域中 形成一 P型摻雜井1〇8，於低壓區域LV中形成一 p型摻雜 井11〇，以及於高壓區域HV中形成一 p型摻雜井112。然 後利用氮化矽層作為遮罩1〇6，進行一熱氧化法以形成複 數個隔離結構114，同時對n型摻雜井1〇2、104以及P型 t雜井108、110、112等進行趨入。在本發明之較佳實施 例中’隔離結構114之厚度約為4000〜6000埃，且其可利 用如述方法步驟形成為場氧化層，或是利用淺溝隔離製程 形成為淺溝隔離結構。 14 1239099 如弟12圖所示，# 形成-絕緣層U6 ’妾著去除遮罩1G6,並於基底100表面 300〜500 i矣。如第’例如犧牲氧化層，較佳厚度約為 摻雜多晶石夕層（未站圖所示，#著於基底1〇〇纟面沉積〜 刻停止層，進行於圖中）’並利賴緣層116作為一飿 HV、低壓區域l/影懸刻製程去除覆蓋料壓區域 層，以使殘餘之狹M NVM CeU區域之部分摻雜多晶石夕 /雜多晶矽層於NVM cell區域内之隔離結 疋義〜控制閘極H8的圖案。1239099 IX. Description of the invention: [Technical field to which the invention belongs] The present invention is about a non-volatile memory (NVM) unit and its manufacturing method, especially an erasable non-volatile memory (NVM) unit. Volatile memory unit and manufacturing method thereof. [Such technology] Non-volatile memory is one of the components commonly used to store data in integrated circuits. Its most important characteristic is that the data stored in non-volatile memory will not disappear due to power supply interruption. . Broadly speaking, hard drives, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory , EEPROM) and flash memory (flash memory) can be regarded as non-volatile memory, because the stored data can be stored without power supply. According to the limitation of memory read and write times, non-volatile memory can be divided into multi-time programmable memory (MTP memory) and one-time programmable memory (OTP memory) ) Two. MTP memory has repeatable read and write functions, such as EEPROM and flash memory. It must be equipped with some related circuits in the design to support different operations such as data writing, erasing 1239099, and reading. OTP memory can only provide a single data write, so there is no need to erase the function of the circuit, but only the circuit with programming and reading function can work normally. Therefore, the circuit used to control the operation of the OTP memory will be much simpler than the circuit used to control the operation of the MTP memory to achieve the advantages of simplifying the manufacturing process and reducing the manufacturing cost. In order to improve the feasibility of OTP memory in practical application, OTP memory can use an erase method similar to EPROM (ultraviolet irradiation) to erase internally stored data. However, some people have also proposed that simple circuit design can be used to control OTP Memory, so that OTP memory can also provide data read and write functions several times. The structural design of the MTP memory cell and the OTP memory cell has a similar stacked structure, including a floating gate for storing electric charges, and an insulating layer (for example, an oxide layer, a silicon nitride layer, and a silicon oxide layer). Composite insulation), and a control gate to control data access. The operation of the memory cell can use the principle similar to that of a capacitor to store the induced charge in the floating gate to change the threshold voltage (Vth) of the memory cell to achieve the purpose of storing data such as 0 or 1. · Please refer to Figure 1. Figure 1 is a schematic cross-sectional view of a conventional non-volatile memory unit. As shown in FIG. 1, the non-volatile memory cell includes a substrate 10, a P-type doped well 12 disposed on the surface of the substrate 10, and an insulating layer 14, a floating gate 16, an insulating layer 18, and a control gate 20. The stacked structure 1239099 is provided on the surface of the P-type doped well 12, and an N-type doped region 22 is provided on the surface of the P-type doped well 12 around the aforementioned stacked structure. Generally speaking, the floating gate 16 and the control gate 20 are formed of doped polycrystalline silicon. The insulating layer 14 below the floating gate 16 is used as a tunneling oxide layer, and is interposed between the floating gate 16 and the control gate. The insulating layer 18 between the electrodes 20 may be formed by a ONO composite insulating layer. In addition, the N-type doped regions 22 on both sides of the floating gate 16 are used as a drain and a source to control the writing, erasing, and reading operations of the non-volatile memory cell. In order to improve the component accumulation, a multi-level non-volatile memory cell structure design is proposed in U.S. Patent No. 6,207,507. Please refer to Fig. 2. Fig. 2 is a schematic cross-sectional view of a conventional multi-level non-volatile memory cell, ...- ~ '...- ~. As shown in FIG. 2, the multi-level non-volatile memory cell includes a substrate 30, a P-type doped well 32 is provided on the surface of the substrate 30, an insulating layer 34 and an insulating layer 38 are provided on the surface of the P-type doped well 32. And used to isolate three adjacent floating gates 36a, 36b and 36c. In addition, the multi-level non-volatile memory cell further includes an N-type doped region 40 for providing a source and a drain provided on the surface of the P-type doped well 32 surrounding the floating gate 36b and the floating gate 36c. The layer 42 covers the surfaces of the floating gates 36 a, 36 b, 36 c and the N-type doped region 40, and a control gate 44 covers the surface of the insulating layer 42. Since the multi-level non-volatile memory cell contains three floating gates 36a, 36b, and 36c, it can store binary data of two bits, such as 00, 01, 10, or 11, so the accumulation of the memory cells can be increased. 1239099 It is known that most of non-volatile memory units use Fowler Nordheim tunneling technology to erase data stored in volatile memory units. During the erasing operation, tunneling oxide layers (such as The electric field of the insulating layer M14 in the figure or the insulating layers 34 and 38 in the second figure must meet the requirements of at least W f million volts and W centimeters (MW⑽). In order to avoid the damage caused by the application of high voltage, tunneling oxidation is usually reduced. The thickness of the layer is in the range of about 80 to 120 angstroms to meet the requirements of high electric fields. Limited by conditions such as the thickness of the tunneling oxide layer and the doping concentration, most of the current non-volatile memory systems are only combined with the low-voltage gold-oxide semiconductor transistor process in the peripheral circuit area (the thickness of the gate oxide layer is about 7 〇Angle), can not be further integrated into other higher voltage operation of the gold-oxide semiconductor transistor process. [Summary of the Invention] Therefore, an object of the present invention is to provide a new nonvolatile memory cell structure and a manufacturing method thereof, which can integrate the process of a nonvolatile memory cell into a high voltage metal oxide semiconductor transistor and a low voltage metal oxide semiconductor. Transistor's Kunhe? Tiger process. In a preferred embodiment of the present invention, the non-volatile memory unit includes a substrate, a first isolation structure is disposed in a first region of the substrate surface, and a second isolation structure is disposed in a second region of the substrate surface. Around, a control pole is provided on the surface of the first isolation structure in the first region, a first insulating reed < 1239099 is on the surface of the control gate, a second insulating layer is provided on the surface of the substrate in the second region, and a The floating gate is disposed on the surfaces of the first insulating layer and the second insulating layer. Since the present invention sets the floating gate above the control gate, the present invention can first complete the process of controlling the gate, and then tunnel the non-volatile memory cell through the oxide layer, the floating gate, the source / drain, etc. The process is integrated into the mixed signal process of high-voltage metal-oxide-semiconductor transistor and low-voltage metal-oxide-semiconductor transistor, which facilitates control and simplification of process conditions. In addition, in the present invention, the control gate is provided on the surface of the isolation structure, so the leakage current generated on the substrate surface during the operation of the non-volatile memory unit can be reduced. [Embodiment] Please refer to FIG. 3, which is a top view of a non-volatile memory unit according to the present invention. As shown in FIG. 3, the non-volatile memory cell of the present invention includes a substrate 50, and a surface of the substrate 50 defines a first region I and a second region II. The first region I is used to form a stacked structure of a control gate 52 and a floating gate 54, wherein the floating gate 54 covers the control gate 52 and the floating gate 54 includes an opening 56 exposed to a part The surface of the control gate 52 is provided to connect the control gate 52 with a wire structure. The second region II is used to form N-type doped regions 58 such as the floating gate 54 and the source / drain. In order to further explain the structure of the non-volatile memory unit of the present invention, please refer to FIGS. 4 to 6 in 1239099, where FIG. 4 is a schematic cross-sectional view of the non-volatile memory unit shown in FIG. 3 along the tangent line AA ′. FIG. 5 is a schematic cross-sectional view of the non-volatile memory unit shown in FIG. 3 along the tangent line BB ′, and FIG. 6 is a schematic cross-sectional view of the non-volatile memory unit shown in FIG. 3 along the tangent line CC ′. As shown in FIG. 4, the non-volatile memory cell includes a P-type doped well 60 on the surface of the substrate 50 in the first region I, an isolation structure 62 is provided on the surface of the P-type doped well 60, and a control gate 52. A stacked structure composed of an insulating layer 64 and a floating gate 54 is disposed above the isolation structure 62. In a preferred embodiment of the present invention, the substrate 50 is a P-type silicon substrate, and the insulating layer 64 is a 100N composite insulating layer composed of an oxide layer, a nitride layer, and a silicon oxide layer, and the gate 52 is controlled. And the floating gate 54 is formed of doped polycrystalline silicon or other conductive materials, and the isolation structure 62 may be a field oxide or a shallow trench isolation (STI) structure. However, the present invention is not limited to this. The substrate 50, the P-type doped well 60, and the N-type doped region 58 can also be adjusted to other conductive types according to the actual design, or an N-type can be formed around the P-type doped well 60. A deep doped well (deep well) to provide a guard ring. In addition, the insulating layer 64 may be formed of other high-voltage-resistant insulating materials. As shown in Figure 5, the non-volatile memory cell in the second region II includes an insulating layer 66 disposed on the surface of the P-type doped well 60 below the floating gate 54, and the N-type doped region 58 is disposed on the floating gate. The surface of the P-type doped well 60 around 54 and the plurality of isolation structures 62 are disposed on the 1239099 ι =: γ〇 surface around the N-type doped region 58. The insulation layer is used as a through-oxidation layer, and is between about 9G and 12G Angstroms. The N-type doped region 58 is used as a source diver of a volatile memory cell, and a channel region is defined below the floating layer. The 'floating gate' 54 of the non-volatile memory cell shown in FIG. 6 is located above the insulating layer 64 of the first region 1 and below the 'floating gate 54' on the insulating layer 66 of the second region 11. A passage area, and the isolation structure 62 is around the passage area. Driving > Table 1 is the present invention—Non-volatile memory cells are fetched: during various operations—the control of ^, the storage-to-pure memory unit simultaneously causes the source electrode 58 and the substrate to apply a Positive voltage, the floating gate is 54 towels. At this time, non-1 is good for electron shooting and stored at 7 ~ 9 volts. During the erasing and dropping :: The axis pole% is applied-high voltage, suppressed; ^, the source and electrode 58 of the non-volatile memory unit is set to-floating state: = 52 and base, at this time non-volatile Division unit, 4 to remove the electricity ^ ~ 2 volts in the floating gate 54. During the reading operation, the starting voltage is reduced to the original value. The original starting voltage is 0 ~ 2 volts ^ The technical gate 52 is applied with a voltage value, such as 2.5 ~ 4 volts and the writing starting voltage (7 ~ 9 Volts) and / or poles 5 and 8 are applied with a positive voltage, 1239099 58 and the substrate 50 are grounded. Please refer to Figures 7 to 10, and Figure 7 to Chu Zuo-Non-volatile memory cell method The figure shows that the method of manufacturing the invention is to first provide a substrate 50, for example, as shown in FIG. 7, this -doping process forms a Shi Xi substrate on the 5G surface of the substrate, and then forms an insulating layer 68 on the surface of the substrate 50. And a miscellaneous well 60. The next layer 68 may be a pad oxide layer, and the mask 70 may be a mask 70. For example, an insulation-lithography and etching process is used to define the silicon nitride layer of the mask 70. Then the insulating layer 68 of the isolation structure 62 is formed. surface. However, in the preferred embodiment, the water vapor and oxygen are diffused into the insulating layer 68 and p〆 by exposing the desired shape, and the emulsification method is used to form a plurality of isolation structures 62, and at the same time, the radon-doped well 60 is used. The step is formed as a field oxide layer, but the ions undergo drive-in. In the present invention, the internal structure 62 of the hybrid well 60 can use the method described above. The separation structure 62 can also use a shallow trench isolation process zone. As shown in FIG. 8, the mask 7n and the insulating layer ^ are then removed, and an insulating layer 72 is formed on the surface of the substrate 50. The thickness of the insulating layer 72 is about 300 to 500 angstroms. Subsequently, a replacement layer (not shown in the figure) was deposited on the substrate with a thickness of 50%, and the insulating layer 72 was used as a lithography and etching process to remove silicon. Part of the pick-up is an etch stop layer, a heteropolycrystalline second layer, and a pattern of control gates 52w is defined above the structure 62. 12 1239099 As shown in FIG. 9, an insulating layer 64 is formed on the surface of the control gate 52. In a preferred embodiment of the present invention, the insulating layer 64 is a 100N insulating layer. The method for forming the insulating layer 64 is as follows: Thermal oxidation process, to form an oxide layer of about 50 ~ 70 angstroms on the surface of the substrate 50, which is used as the bottom oxidation: and _ line _ low pressure chemical vapor deposition process on the surface of the bottom oxide layer =-thickness about It is a layer of nitrided stone of 200 ~ 350 angstroms; then in a .950 ν temperature environment, the temperature of 4 and 0 ° C is tempered for 30 minutes to repair h with a thickness of 50 to 70 ° and a A Shi Er / w surface you lithographic and etched Luo Di-Gai Shan, layer, and finally 4 丨 edition privately defined the pattern of the insulating layer 64. Man reuse-thickness 2 == :; type oxidation and cut in nitrogen After the junction-edge layer 72 of the layer Γ, the insulating layer 66 is still formed as it is, and it is used for the second full deposition of 1 polycrystalline poly on the 50 * side of the substrate. For example, the substrate 50 is etched to remove a part of the doping process. Shown as shown in Figure 3 ^ Tong Xi Yue said silicon layer 74 Second, two side doped regions formed on the two side walls 乂 for A. _ 元 成 非 volatile The sexual memory list is': Refer to FIG. 11 to FIG. 20, and the schematic diagram of the method for the process of manufacturing a metal oxide semiconductor 2 13 1239099 body and a low voltage metal oxide semiconductor transistor. As shown in FIG. 11, the method of the present invention first provides a substrate 100, such as a P-type silicon substrate, and the surface of the substrate 100 includes an NVM cell region for manufacturing non-volatile memory cells. The high-voltage region HV of the transistor and a low-voltage region LV used to make a low-voltage metal-oxide semiconductor transistor. Next, a pad oxide layer (not shown in the figure) is formed on the surface of the substrate 100, and an N-type dopant is used for a bianket implant to form an N-type dopant in the low-voltage region lv. Well 102, an n-type doped well 104 is formed in the HV region, and an N-type doped well is formed in the NVM cell region (not shown in the figure). Then, a silicon nitride layer (not shown in the figure) with a thickness of about 1000 angstroms is deposited on the substrate 100 surface, and an etching process is performed to form a plurality of openings in the silicon nitride layer to define a predetermined The area that forms the isolation structure (that is, defines the active area). P-type dopants are then used for doping to form a P-type doped well 108 in the NVM cell region, a p-type doped well 1110 in the low-voltage region LV, and a high-voltage region HV. The p-type doped well 112. Then, a silicon nitride layer is used as the mask 106, and a thermal oxidation method is performed to form a plurality of isolation structures 114. At the same time, the n-type doped wells 102, 104, and the p-type t-wells 108, 110, and 112 are simultaneously formed. Go in. In a preferred embodiment of the present invention, the thickness of the 'isolation structure 114 is about 4000 to 6000 angstroms, and it can be formed into a field oxide layer using the method steps described above, or formed into a shallow trench isolation structure using a shallow trench isolation process. 14 1239099 As shown in Fig. 12, # forming-insulating layer U6 'is removed by removing the mask 1G6, and 300 ~ 500 i 矣 on the surface of the substrate 100. As the first example, the sacrificial oxide layer, the preferred thickness is about doped polycrystalline silicon layer (not shown in the figure, # deposited on the substrate 100 纟 surface ~ etch stop layer, as shown in the figure) The marginal layer 116 is used as a HV, low-voltage region / overhang process to remove the overlay material region layer, so that a portion of the remaining narrow M NVM CeU region is doped with a polycrystalline silicon / heteropoly silicon layer in the NVM cell region. The meaning of isolation is to control the pattern of the gate H8.
如第14圖所；^ ^ 、’接耆於控制閉極118表面形成一絕緣 層12 0 ’在本日日& ” 月之較佳實施例中，絕緣層120係為一 〇N〇As shown in FIG. 14; ^ ^ and ′ are connected to the surface of the control closed electrode 118 to form an insulating layer 12 0 ′. In the preferred embodiment of today & ”month, the insulating layer 120 is a 〇N〇
、、、巴、、、彖層’其形成方法介紹如下:進行―熱氧化製程，以於基 底1〇0表面形成—約為50〜70埃的氧化層，用來當作底氣 化層，Ik後進行一低壓化學氣相沈積製程，於底氧化層表 面沈積一厚度約為200〜350埃之氮化矽層；接著於950¾ 之回溫裱境中，進行一回火製程30分鐘以修補氮化矽層的 結構’並通入水蒸氣以進行濕式氧化而在氮化矽層表面形 成一厚度為50〜7〇埃之矽氧層，作為上氧化層；最後再利 用一微影暨蝕刻製程定義出絕緣層120的圖案。 去除絕緣層116，仍如第Η圖所示，再於基底100表面 形成一絕緣層122，用來作為高壓金氧半導體電晶體之閉 極氧化層，較佳厚度約為300〜500埃。如第15圖所示，接 15 1239099 著對问£區域HV進行摻雜：例如於N型摻雜井1〇4周圍 離結構114下方形成-通道阻絕區域124及/或其他保 蔓衣，對p型摻雜井112進行摻雜，以調整NM〇s電晶體 之起始電壓值及/或於p型換雜井112中形成一反貫穿 (anti-punch through，APT)區域(未顯示於圖中）；以及對n 型摻雜井104進行摻雜，以調整pM〇s電晶體之起始電壓 值等。 如第16圖所示，接著再對P型摻雜并112、110、108 修 進行摻雜·例如於高壓區域Hv之p型摻雜井112周圍之 h離結構114下方形成一通道阻絕區域126及/或其他保護 裱’於低壓區域LV之P型摻雜井ι1〇形成一通道阻絕區 域128及/或反貫穿區域（未顯示於圖中），以及於nVm cell 區域之P型摻雜井1〇8中形成通道阻絕區域及/或反貫穿區 域（未顯示於圖中）。之後再進行一摻雜製程，以調整低壓 區域LV以及NVM cell區域之起始電壓值。然後去除低壓 鲁 區域LV以及NVMcell區域之絕緣層122，以暴露出低壓 區域LV以及NVM cell區域之基底1〇〇表面。 如第17圖所示，接著進行一熱氧化或化學氣相沈積製 程’於基底表面全面形成一絕緣層130，例如一氧化 層，較佳厚度約為50〜70埃，然後去除低壓區域Lv之絕 緣層130以暴露出低壓區域LV之基底1〇〇表面，並再次 16 1239099 於基底100表面全面形成一絕緣層132，較佳厚度約為 〜70埃。此時，低壓區域LV内之絕緣層i32具有一厚度 介於60〜70埃之間，可作為低壓金氧半導體電晶體之閘極 氧化層，NVM cell内之絕緣層130具有一累積厚度介於 95〜1〇〇埃之間，可作為nVm cell區域之隧穿氧化層，且 高壓區域HV内之絕緣層122具有一累積厚度介於45〇〜55〇 埃之間，可作為高壓金氧半導體電晶體之閘極氧化層。 如弟18圖所示’接著於基底1〇〇表面全面沉積一摻雜 Φ 多晶矽層（未顯示於圖中），並利用一微影暨蝕刻製程去除 4刀之摻雜多晶石夕層’以於NVM cell區域中定義出浮動閘 極134的圖案，於低壓區域LV中定義出複數個閘極136、 138 ’以及於高壓區域HV中定義出複數個閘極14〇、142。 此外’為了降低閘極片阻抗(sheet resistance)，本發明亦可 於摻雜多晶矽層表面形成一金屬矽化物層，例如矽化鎢。 在本發明之較佳實施例中’浮動閘極134係覆蓋於絕緣層 孀 12〇以及絕緣層130上方，且浮動閘極134包含有一開口 135设於控制閘極118上方，以提供導線結構連接至控制 間極118，用來控制非揮發性記憶單元之操作。 二乃然如第18圖所示，之後再對高壓區域Hv進行一推 雜製程，以於閘極140周圍之Ν型摻雜井1〇4中形成一 ρ 型漸層摻雜區域(P_typegraderegi〇n)144，用來作為pM〇s 17 !239〇99 電晶體之雙重擴散汲極（double diffused drain，DDD)結構， 以及於閘極142周圍之P型摻雜井i12中形成一 N型漸層 摻雜區域(N-type grade regi〇n)146，用來作為NM〇s電晶 體之雙重擴散汲極。此外，為了改善p型摻雜井112以及 N型摻雜井1〇4之摻質濃度分佈，本發明亦可選擇於p型 摻雜井112内形成至少一 p型漸層換雜區域144,以及於n 型摻雜井104内形成至少一 漸層摻雜區域i46。此外， 本發明亦可以於摻雜高壓區域阶時，同步於ΝνΜ_區 ^之P型換雜彳108中形成一 N型漸層摻雜區域叫設 提高源極端之崩潰電壓。隨後，於基底100 切層，並進行—㈣刻，㈣浮動閉極 壁上形η壁：::厂 如第19圖所示，對基底1〇〇進行一The formation method of ",", "", "", "", "" and "" are described as follows: The thermal oxidation process is performed to form the substrate 100 surface-an oxide layer of about 50 to 70 angstroms is used as the bottom gasification layer, Ik Then, a low-pressure chemical vapor deposition process is performed, and a silicon nitride layer with a thickness of about 200 to 350 angstroms is deposited on the surface of the bottom oxide layer. Then, a tempering process is performed in a temperature-recovered environment of 950¾ for 30 minutes to repair nitrogen. The structure of the silicon layer is formed, and water vapor is passed in for wet oxidation to form a silicon oxide layer with a thickness of 50 to 70 angstroms on the surface of the silicon nitride layer as an upper oxide layer. Finally, a lithography and etching process is used. A pattern of the insulating layer 120 is defined. After removing the insulating layer 116, an insulating layer 122 is further formed on the surface of the substrate 100 as shown in the second figure, and is used as a closed oxide layer of a high-voltage metal-oxide semiconductor transistor, preferably with a thickness of about 300 to 500 angstroms. As shown in FIG. 15, the doping of the HV region is followed by 15 1239099: for example, a channel-blocking region 124 and / or other protective clothing is formed around the N-type doped well 104 below the structure 114. The p-type doped well 112 is doped to adjust the initial voltage of the NMOS transistor and / or to form an anti-punch through (APT) region in the p-type doped well 112 (not shown in FIG. (In the figure); and doping the n-type doped well 104 to adjust the initial voltage value of the pMOS transistor. As shown in FIG. 16, P-type doping is then performed on 112, 110, and 108. For example, a channel blocking region 126 is formed below the p-type doping well 112 in the high-voltage region H below the isolation structure 114. And / or other protective P-type doped wells in the low-voltage region LV10 to form a channel blocking region 128 and / or anti-penetration region (not shown in the figure), and a P-type doped well in the nVm cell region A channel blocking region and / or a reverse penetration region are formed in 108 (not shown in the figure). Then, a doping process is performed to adjust the initial voltage values of the low-voltage region LV and the NVM cell region. Then, the insulating layer 122 in the low-voltage region LV and the NVMcell region is removed to expose the surface of the substrate 100 in the low-voltage region LV and the NVM cell region. As shown in FIG. 17, a thermal oxidation or chemical vapor deposition process is then performed to form an insulating layer 130 on the substrate surface, such as an oxide layer, preferably with a thickness of about 50 to 70 angstroms, and then removing the low-voltage region Lv. The insulating layer 130 exposes the surface of the substrate 100 in the low-voltage region LV, and forms an insulating layer 132 on the surface of the substrate 100 again, preferably with a thickness of about 70 angstroms. At this time, the insulating layer i32 in the low-voltage region LV has a thickness between 60 and 70 angstroms, which can be used as the gate oxide layer of the low-voltage metal-oxide semiconductor transistor. The insulating layer 130 in the NVM cell has a cumulative thickness between Between 95 and 100 angstroms, it can be used as a tunneling oxide layer in the nVm cell region, and the insulating layer 122 in the high voltage region HV has a cumulative thickness between 45 and 55 angstroms, which can be used as a high voltage metal-oxide semiconductor Gate oxide layer of transistor. As shown in Figure 18, 'Next, a doped Φ polycrystalline silicon layer (not shown in the figure) is deposited on the 100 surface of the substrate, and a 4-lithography doped polycrystalline silicon layer is removed by a lithography and etching process.' The pattern of the floating gate 134 is defined in the NVM cell region, a plurality of gates 136, 138 'are defined in the low-voltage region LV, and a plurality of gates 14 and 142 are defined in the high-voltage region HV. In addition, in order to reduce the sheet resistance, the present invention can also form a metal silicide layer, such as tungsten silicide, on the surface of the doped polycrystalline silicon layer. In the preferred embodiment of the present invention, the 'floating gate 134 covers the insulating layer 120 and the insulating layer 130, and the floating gate 134 includes an opening 135 provided above the control gate 118 to provide a wire structure connection. The control pole 118 is used to control the operation of the non-volatile memory unit. Second, as shown in FIG. 18, a doping process is then performed on the high-voltage region Hv to form a p-type graded doped region (P_typegraderegi.) In the N-type doped well 10 around the gate 140. n) 144, which is used as a double diffused drain (DDD) structure of the pM0s 17! 239〇99 transistor, and an N-type gradually formed in the P-type doped well i12 around the gate 142 A layer doped region (N-type grade region) 146 is used as the double diffusion drain of the NMOS transistor. In addition, in order to improve the dopant concentration distribution of the p-type doped well 112 and the N-type doped well 104, the present invention may also choose to form at least one p-type doped well replacement region 144 in the p-type doped well 112. And, at least one gradient doped region i46 is formed in the n-type doped well 104. In addition, the present invention can also form an N-type gradually doped region in the P-type doping region 108 synchronously with the NvM_ region when the high-voltage region is doped to increase the breakdown voltage at the source extreme. Subsequently, the layer is cut on the substrate 100 and engraved to form a η wall on the floating closed electrode wall ::: factory As shown in FIG. 19, the substrate 100 is subjected to
cell區域中形成一 μ ， 心維衣程，以於NVM Ν型推雜區域151、一 ρ刑4么 於低壓區域LV I穆雜區域152, 中形成一P型摻雜區域丨 區域156、一 Ν Μ、—N型摻雜 又摻雜區域158、一 ρ失 及於高壓區域山 主仏雜區域160，以 中形成一 P型摻雜區域 雜區域164、一 M⑴ A 162、一 N型摻 N型摻雜區域166、一卩刑仏 隨後，進行一回、> 制 1穆雜區域168。 大製程，以趨入上述摻雜 雜區域151、154 ^區域。其中，摻 摻雜區域152、156 的係用來作為源極/汲極， 156^ 160 > 164^ + H 糸用來調整摻雜井 18 1239099 108 ' 102 ' 110、l〇4、112之摻質濃度。此外，本發明亦可 依據實際設計需要，對低壓區域LV或NVMcell區域進行 摻雜’以形成輕摻雜沒極(lightly d〇pe(j drain, LDD)或口袋 摻雜區域(pocket doping regi〇n)。 最後，如第20圖所示，於基底loo表面全面沈積一層 間介電層170,並於層間介電層170中形成複數個接觸洞， 以用來提供導線172連接至各元件之閘極、源極以及汲極 專結構。 鲁 本發明之非揮發性記憶單元之各項電性測試結果係顯 示於第21圖至第23圖。第21圖為本發明一非揮發性記憶 單元之汲極電流對汲極電壓的關係示意圖，其中控制閘極 之施加電壓約為9伏特，如第21圖之曲線所示，當汲極電 疋Vds >及介於6〜8伏特時’>及極電流Ids具有一遞減趨勢， 表示部分通道熱電子已射入浮動閘極，因此非揮發性記憶 孀 單元於進行寫入操作時，汲極之施加電壓較佳值約介於6〜8 伏特，可以獲得最佳寫入效率。第22圖為本發明一非揮發 性記憶單元之寫入速度測試的示意圖，其中控制閘極之施 加電壓約為12伏特。如第22圖所示，本發明之非揮發性 記憶單元於進行寫入操作時，其起始電壓可於小於l〇〇ms 的時間内便達到7〜9伏特。第23圖為本發明一非揮發性記 憶單元之耐久力測試(endurance test)的示意圖，其中寫入操 19 1239099A μ is formed in the cell region, so that the NVM N-type doping region 151 and a ρ4 are formed in the low-voltage region LV I and the impurity region 152, forming a P-type doped region 丨 region 156, a NM, -N-type doped and doped regions 158, a ρ is lost in the high-voltage region and the main doped region 160 to form a P-type doped region, a doped region 164, a M⑴A 162, and an N-type doped The N-type doped region 166 is then subjected to a single step, and then one impurity region 168 is made. A large process is used to approach the doped impurity regions 151 and 154 ^. Among them, the doped regions 152 and 156 are used as source / drain electrodes, and 156 ^ 160 > 164 ^ + H 糸 is used to adjust the doped wells 18 1239099 108 '102' 110, 104, 112 Spike concentration. In addition, the present invention can also dope the low-voltage region LV or NVMcell region according to the actual design needs to form a lightly doped (j drain (LDD)) or pocket doping regi. n). Finally, as shown in FIG. 20, an interlayer dielectric layer 170 is deposited on the surface of the substrate loo, and a plurality of contact holes are formed in the interlayer dielectric layer 170, so as to provide the wires 172 connected to the components. Gate, source and drain structures. The electrical test results of the non-volatile memory unit of the present invention are shown in Figures 21 to 23. Figure 21 is a non-volatile memory unit of the present invention. Schematic diagram of the relationship between the drain current and the drain voltage, in which the applied voltage of the control gate is about 9 volts, as shown in the graph of FIG. 21, when the drain voltage 疋 Vds > and between 6 and 8 volts' > The pole current Ids has a decreasing trend, indicating that some channel hot electrons have been injected into the floating gate, so when the non-volatile memory cell is performing a write operation, the applied voltage of the drain electrode is preferably about 6 ~ 8 volts for best write efficiency FIG. 22 is a schematic diagram of a writing speed test of a non-volatile memory cell according to the present invention, in which the applied voltage of the control gate is about 12 volts. As shown in FIG. 22, the non-volatile memory cell according to the present invention performs writing During the start-up operation, the initial voltage can reach 7-9 volts in less than 100ms. Figure 23 is a schematic diagram of the endurance test of a non-volatile memory cell of the present invention, in which Entry 19 1239099
犬特，寫入時間約為 :約為9·5伏特，抹除 本發明非揮發性記憶 >Μ)時’其於經歷2〇 ，寫入操作時之起始電壓 ’抹除操作時之起始電墨 可以提供良好的耐久力。 ^相較於f知之非揮發性記憶單元結構及其製程，本發明 係將浮動閘極設於控彻極上方，因此本發明可以先完成 控制’之製程，再將非揮發性記憶單元之隧穿氧化層、 浮動閘極以及源極/汲極等製程整合至高壓金氧半導體電 晶體與低壓金氧半導體電晶體之混合訊號製程中，有利於 製私條件之控制與簡化。此外，本發明係將控制閘極設於 隔離結構表面，因此可以降低非揮發性記憶單元操作時於 基底表面產生之漏電流。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬·本發明專利之涵蓋 範圍。 【圖式簡單說明】 第1圖為習知一非揮發性記憶單元的剖面示意圖； 20 1239099 第2圖為習知一多層次非揮發性記憶單元的剖面示意 圖； 第3圖為本發明一非揮發性記憶單元的俯視圖； 第4圖為第3圖所示之非揮發性記憶單元沿切線AA’之 剖面示意圖； 第5圖為第3圖所示之非揮發性記憶單元沿切線BB’之 剖面示意圖； 第6圖為第3圖所示之非揮發性記憶單元沿切線CC’之 剖面示意圖； 第7圖至第10圖為本發明製作一非揮發性記憶單元之 方法示意圖； 第11圖至第20圖為本發明整合一非揮發性記憶單元之 製程至一高壓金氧半導體電晶體以及一低壓金氧半導體電 晶體之製程的方法示意圖； 第21圖為本發明一非揮發性記憶單元之汲極電流對汲 極電壓的關係示意圖； 第22圖為本發明一非揮發性記憶單元之寫入速度測試 的不意圖， 第23圖為本發明一非揮發性記憶單元之耐久力測試的 不意圖，以及 表1為本發明一非揮發性記憶單元於進行寫入、抹除以 及讀取等各項操作時之參數參考值。 21 1239099 【主要元件符號說明】 10 、 30 、 50 、 100 ΪΙ 12 、 32 、 60 、 108 、 110 、 112 P型摻雜井 14、18、34、38、42、64、66、68、 1絕緣層 ! 72、116、120、122、130、132 16、36a、36b、36c、54、134 浮動閘極 20、44、52、118 控制閘極 22、40、58、146、148、151、156、 N型摻雜區域 158 、 164 、 166 56、135 開口 62、114 隔離結構 70 、 106 遮罩 74 摻雜多晶矽層 76 、 150 側壁子 102 、 104 N型摻雜井 124 、 126 、 128 通道阻絕區域 136 、 138 、 140 、 142 閘極 144 、 152 、 154 、 160 、 162 、 168 P型摻雜區域 170 層間介電層 172 導線結構 I 第一區域 II 第二區域 22 1239099 NVM cell 非揮發性記憶單 元區域 HV 高壓區域 LV 低壓區域The write time is approximately: 9.5 volts. When erasing the non-volatile memory of the present invention > M), 'its initial voltage at the time of 20, the write operation' Initial electro-ink can provide good durability. ^ Compared with the structure of non-volatile memory cell and its manufacturing process, the present invention sets the floating gate above the control electrode, so the present invention can complete the process of control first, and then tunnel the non-volatile memory cell. Processes such as through-oxide, floating gate, and source / drain integration into the mixed-signal process of high-voltage metal-oxide-semiconductor transistors and low-voltage metal-oxide-semiconductor transistors facilitate the control and simplification of manufacturing conditions. In addition, in the present invention, the control gate is provided on the surface of the isolation structure, so the leakage current generated on the surface of the substrate during the operation of the non-volatile memory unit can be reduced. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent. [Brief description of the drawings] Figure 1 is a schematic sectional view of a conventional non-volatile memory unit; 20 1239099 Figure 2 is a schematic sectional view of a conventional multi-layer non-volatile memory unit; Figure 3 is a non-volatile memory unit of the present invention Top view of the volatile memory unit; Figure 4 is a schematic cross-sectional view of the non-volatile memory unit along the tangent line AA 'shown in Figure 3; Figure 5 is a section of the non-volatile memory unit along the tangent line BB' shown in Figure 3 Sectional schematic diagram; Figure 6 is a schematic sectional view of the non-volatile memory cell along the tangent line CC 'shown in Figure 3; Figures 7 to 10 are schematic diagrams of a method for making a non-volatile memory cell according to the present invention; Figure 11 FIG. 20 is a schematic diagram of a method for integrating a process of a non-volatile memory cell into a process of a high-voltage metal-oxide semiconductor transistor and a process of a low-voltage metal-oxide semiconductor transistor; FIG. 21 is a non-volatile memory cell of the present invention; Schematic diagram of the relationship between the drain current and the drain voltage; FIG. 22 is a schematic diagram of a write speed test of a nonvolatile memory cell according to the present invention, and FIG. 23 is a nonvolatile memory cell according to the present invention Durability test is not intended to, and a non-volatile memory cell of the present invention in Table 1 write, erase the parameters of the reference value and operative to read the like. 21 1239099 [Description of main component symbols] 10, 30, 50, 100 Ϊ12 12, 32, 60, 108, 110, 112 P-type doped wells 14, 18, 34, 38, 42, 64, 66, 68, 1 Insulation Layers! 72, 116, 120, 122, 130, 132 16, 36a, 36b, 36c, 54, 134 Floating gates 20, 44, 52, 118 Control gates 22, 40, 58, 146, 148, 151, 156 N-type doped regions 158, 164, 166 56, 135 Opening 62, 114 Isolation structure 70, 106 Mask 74 Doped polycrystalline silicon layer 76, 150 Side wall 102, 104 N-type doped well 124, 126, 128 Channel block Regions 136, 138, 140, 142 Gates 144, 152, 154, 160, 162, 168 P-type doped regions 170 Interlayer dielectric layer 172 Wire structure I First region II Second region 22 1239099 NVM cell Non-volatile memory Unit area HV High voltage area LV Low voltage area
23 1239099 寫入操作 抹除操作 讀取操作 控制閘極電壓vCG >10V ον 2·5 〜4V 汲極電壓Vd 6V 浮接 IV 源極電壓vs 0V 9〜10V ον 基底電壓Vsub ον ον ον 起始電壓Vth 7 〜9V (off) 1 〜2 V (on) 操作速度 100ms 1000ms23 1239099 Write operation Erase operation Read operation Control gate voltage vCG > 10V ον 2.5 · 4 ~ 4V Drain voltage Vd 6V Floating IV Source voltage vs 0V 9 ~ 10V ον Base voltage Vsub ον ον ον Start Voltage Vth 7 to 9V (off) 1 to 2 V (on) Operating speed 100ms 1000ms