TW202201573A - 晶粒堆疊結構及其形成方法 - Google Patents

晶粒堆疊結構及其形成方法 Download PDF

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TW202201573A
TW202201573A TW110102576A TW110102576A TW202201573A TW 202201573 A TW202201573 A TW 202201573A TW 110102576 A TW110102576 A TW 110102576A TW 110102576 A TW110102576 A TW 110102576A TW 202201573 A TW202201573 A TW 202201573A
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die
package
stack structure
device die
encapsulation
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TW110102576A
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TWI770786B (zh
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余振華
郭鴻毅
于宗源
劉重希
蔡豪益
謝政傑
曾明鴻
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台灣積體電路製造股份有限公司
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Priority claimed from US16/925,032 external-priority patent/US11521959B2/en
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Abstract

本發明提供一種方法，包含將第一元件晶粒接合至第二元件晶粒，將第一元件晶粒包封在第一包封體中，對第二元件晶粒執行背側研磨（grinding）製程以顯露出第二元件晶粒中的多個穿孔，以及在第二元件晶粒上形成多個第一電連接件以形成封裝。封裝包含第一元件晶粒及第二元件晶粒。方法更包含將第一封裝包封在第二包封體中，以及形成與第一封裝及第二包封體交疊的內連線結構。內連線結構包括多個第二電連接件。

Description

晶粒堆疊結構及其形成方法
半導體產業已歸因於多種電子組件（例如電晶體、二極體、電阻器、電容器等）的積集度（integration density）改良而經歷快速增長。主要地，積集度的改良源自於最小特徵尺寸的迭代減小，此允許將更多組件集成至給定區域中。隨著對於縮小電子元件的需求增長，已出現對於更小且更具創造性的半導體晶粒的封裝技術的需求。此類封裝系統的實例為疊層封裝（Package-on-Package；PoP）技術。在PoP元件中，頂部半導體封裝堆疊於底部半導體封裝的頂部上，以提供高積集度及高組件密度。PoP技術大體上能夠在印刷電路板（printed circuit board；PCB）上使半導體元件的生產具有增強的功能性及小的佔據面積（footprint）。
以下揭露內容提供用以實施本揭露的不同特徵的許多不同實施例或實例。下文描述組件及佈置的具體實例以簡化本揭露。當然，這些實例僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成，使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露可在各種實例中重複附圖符號及/或字母。此重複是出於簡單及清晰的目的，且本身並不指示所論述的各種實施例及/或配置之間的關係。
另外，為易於描述，可在本文中使用例如「在…之下」、「在…下方」、「下部」、「上覆」、「上部」以及類似物的空間相對性術語，以描述如圖中所示出的一個部件或特徵與另一部件或特徵的關係。除圖式中所描繪的取向之外，空間相對性術語亦意欲涵蓋元件在使用或操作中的不同取向。裝置可以其他方式取向（旋轉90度或處於其他取向），且本文中所使用的空間相對性描述詞可同樣相應地進行解譯。
根據一些實施例，提供一種晶粒堆疊及形成晶粒堆疊的製程。根據本揭露的一些實施例，晶粒堆疊包含接合至第二元件晶粒的第一元件晶粒，其中第一元件晶粒及第二元件晶粒兩者均將積體電路元件（諸如電晶體）包含於其中。第二元件晶粒包含多個穿孔（有時稱為基底穿孔（Through-Substrate Via；TSV）或矽穿孔（Through-Silicon Via；TSV））。可使用扇出型製程在晶粒堆疊上形成多個重佈線路，使得重佈線路實體地結合至第二元件晶粒而在其間沒有焊料區。多個探針接墊可形成於第二元件晶粒的表面上，且可與將第一元件晶粒包封於其中的包封體接觸。本文中所論述的實施例將提供使得能夠製造或使用本揭露的主題的實例，且所屬領域中具通常知識者將易於理解可在保持於不同實施例的所涵蓋範疇內的同時進行的修改。在各種視圖及示例實施例中，相同附圖符號用以表示相同部件。儘管方法實施例可論述為以特定次序執行，但其他方法實施例可以任何邏輯次序執行。
圖1至圖9、圖10A、圖10B、圖11至圖14、圖15A、圖16A、圖15B、圖16B以及圖17至圖20示出根據本揭露的一些實施例的形成晶粒堆疊的中間階段的橫截面視圖。如圖25中所示的製程流程200中示意性地反映對應製程。
圖1示出晶圓20的橫截面視圖。晶圓20可包含其中的多個元件晶粒（也稱為晶粒）22，其中以所述多個元件晶粒22中的一者為實例進行說明。多個元件晶粒22彼此相同。根據本揭露的一些實施例，晶圓20為包含主動元件及可能包含被動元件（示出為多個積體電路元件26）的元件晶圓。根據一些實施例，元件晶粒22為邏輯晶粒，所述邏輯晶粒可為特定應用積體電路（Application Specific Integrated Circuit；ASIC）晶粒、現場可程式化閘陣列（Field Programmable Gate Array；FPGA）晶粒或類似者。舉例而言，元件晶粒22可為中央處理單元（Central Processing Unit；CPU）晶粒、圖形處理單元（Graphic Processing Unit；GPU）晶粒或類似者。
根據本揭露的一些實施例，元件晶粒22包含半導體基底（也稱為基底）24。半導體基底24可由結晶矽、結晶鍺、鍺化矽或III-V化合物半導體形成，所述III-V化合物半導體諸如GaN、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或類似者。半導體基底24亦可為塊狀半導體基底或絕緣層上半導體（Silicon-On-Insulator；SOI）基底。淺溝槽隔離（Shallow Trench Isolation；STI）區（未示出）可形成於半導體基底24中，以隔離半導體基底24中的主動區。
形成多個穿孔（有時稱為矽穿孔或半導體穿孔）25以延伸至半導體基底24中，其中所述多個穿孔25用以使元件晶粒22的相對側上的特徵電性互耦。多個穿孔25電性連接至上覆的多個接合接墊32，且可電性連接至多個探針接墊36。
根據本揭露的一些實施例，積體電路元件26可包含互補金屬氧化物半導體（Complementary Metal-Oxide Semiconductor；CMOS）電晶體、電阻器、電容器、二極體及類似者。多個積體電路元件26中的一些可形成於半導體基底24的頂部表面處。本文中未示出積體電路元件26的細節。
內連線結構28形成於半導體基底24上方。內連線結構28的細節未繪示且在本文中簡要論述。根據一些實施例，內連線結構28包含在半導體基底24上方且填充多個積體電路元件26中的多個電晶體（未示出）的多個閘極堆疊之間的間隔的層間介電質（Inter-Layer Dielectric；ILD）。根據一些實施例，ILD由磷矽酸鹽玻璃（Phospho Silicate Glass；PSG）、硼矽酸鹽玻璃（Boro Silicate Glass；BSG）、硼摻雜磷矽酸鹽玻璃（Boron-Doped Phospho Silicate Glass；BPSG）、氟摻雜矽酸鹽玻璃（Fluorine-Doped Silicate Glass；FSG）、氧化矽或類似者形成。根據本揭露的一些實施例，使用沈積方法形成ILD，所述沈積方法諸如電漿增強型化學氣相沈積（Plasma-Enhanced Chemical Vapor Deposition；PECVD）、低壓化學氣相沈積（Low Pressure Chemical Vapor Deposition；LPCVD）、旋塗式塗佈、可流動化學氣相沈積（Flowable Chemical Vapor Deposition；FCVD）或類似者。
多個接觸塞（contact plug）（未示出）形成於ILD中，且用以將積體電路元件26及穿孔25電性連接至上覆的金屬線及通孔。根據本揭露的一些實施例，接觸塞由選自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、其合金，及/或其多層的導電材料形成。接觸塞的形成可包含在ILD中形成接觸開口，將導電材料填充至接觸開口中，以及執行平坦化製程（諸如化學機械拋光（Chemical Mechanical Polish；CMP）製程或機械研磨（grinding）製程），以使接觸塞的頂部表面與ILD的頂部表面齊平。
內連線結構28可更包含在ILD及接觸塞上方的多個介電層（未示出）。多個金屬線及多個通孔（未示出）形成於多個介電層（亦稱為金屬間介電質（Inter-Metal Dielectrics；IMD）中。位於相同水平處的多個金屬線在下文中共同稱為金屬層。根據本揭露的一些實施例，內連線結構28包含多個金屬層，每一者包含位於相同水平處的多個金屬線。相鄰金屬層中的金屬線經由通孔互連。金屬線及通孔可由銅或銅合金形成，且其亦可由其他金屬形成。根據本揭露的一些實施例，IMD由低介電常數（low-k）介電材料形成。舉例而言，低介電常數介電材料的介電常數（k值）可小於約3.0。介電層可包括含碳低介電常數介電材料、氫倍半矽氧烷（Hydrogen SilsesQuioxane；HSQ）、甲基倍半矽氧烷（MethylSilsesQuioxane；MSQ）或類似者。根據本揭露的一些實施例，介電層的形成包含沈積含致孔劑的介電材料，且接著執行固化製程以向外驅除致孔劑，且因此剩餘的介電層為多孔的。表面介電層30形成於內連線結構28上方。根據一些實施例，表面介電層30由聚合物形成，所述聚合物可包含聚苯并噁唑（polybenzoxazole；PBO）、聚醯亞胺、苯并環丁烯（benzocyclobutene；BCB）或類似者。
多個接合接墊32及多個探針接墊36形成於元件晶粒22的頂部表面上。相應製程在如圖25中所示的製程流程200中示出為製程202。根據一些實施例，接合接墊32及探針接墊36兩者均電性且傳送訊號地連接至積體電路元件26，且可能至穿孔25。根據一些實施例，接合接墊32為具有橫向尺寸W1及間距P1的微凸塊，且探針接墊36具有橫向尺寸W2及間距P2。橫向尺寸W2可大於（或可等於）橫向尺寸W1。間距P2可大於（或可等於）間距P1。根據一些實施例，探針接墊36用於探測積體電路元件26（測試積體電路元件26的功能）。因此，藉由具有相對較大尺寸及較大間距的探針接墊36，減少探測成本。另一方面，接合接墊32用於接合至封裝組件122（圖4）。因此，藉由具有減小尺寸及減小間距的接合接墊32，可分配更多接合接墊32，且因此更多訊號路徑可在元件晶粒22與封裝組件122之間建立。根據一些實施例，比率W2/W1可在約1與約5之間的範圍內。比率P2/P1亦可在約1與約5之間的範圍內。
多個焊料區34及多個焊料區38分別形成於多個接合接墊32的頂部及多個探針接墊36的頂部。相應製程亦在如圖25中所示的製程流程200中示出為製程202。接合接墊32、探針接墊36以及焊料區34及焊料區38的形成可包含沈積金屬晶種層，形成且圖案化諸如光阻的鍍覆罩幕，以及在經圖案化鍍覆罩幕中的開口中鍍覆接合接墊32、探針接墊36以及焊料區34及焊料區38。金屬晶種層可包含銅層，或鈦層以及在鈦層上方的銅層。經鍍覆的接合接墊32及探針接墊36可包含銅、鎳、鈀或其組成物層。接著移除經圖案化鍍覆罩幕，接著執行蝕刻製程以移除先前由鍍覆罩幕覆蓋的金屬晶種層的部分。接著執行回焊製程以回焊焊料區34及焊料區38。
進一步參考圖1，例如藉由使探針卡40的引腳與焊料區38接觸來探測元件晶粒22。相應製程在如圖25中所示的製程流程200中示出為製程204。探針卡40連接至探測元件（未示出），所述探針元件電性連接至經配置以判定元件晶粒22的連接及功能性的工具（未示出）。經由元件晶粒22的探測，其可判定元件晶粒22中的哪些為有缺陷的晶粒，以及元件晶粒22中的哪些為有功能（良好）的晶粒。焊料區38比下伏的探針接墊36更軟，使得探針卡40中的引腳可更佳地電性連接至探針接墊36。
參考圖2，根據一些實施例，在探測製程之後，經由蝕刻移除焊料區38。相應製程在如圖25中所示的製程流程200中示出為製程206。另一方面，保持焊料區34未蝕刻。根據替代性實施例，焊料區38未蝕刻，且保持在圖20至圖23中所示的最終封裝中。在後續圖中的一些中，未示出焊料區38。然而，應瞭解，在這些圖中，焊料區38可仍然存在（或可不存在）。
圖3示出使晶圓120探測且單體化成離散的多個晶粒（也稱為元件晶粒）122。元件晶粒122亦可為ASIC晶粒，所述ASIC晶粒可為邏輯晶粒或記憶體晶粒或類似者。根據一些實施例，晶圓120包含半導體基底124及積體電路元件（未示出），所述積體電路元件可包含主動元件（諸如電晶體）及被動元件。內連線結構128形成於半導體基底124上方，且用以連接至積體電路元件（且使積體電路元件互連）。內連線結構128的結構亦可包含介電層（其可包含低介電常數介電層）、金屬線以及通孔等。表面介電層130在元件晶粒122的表面處形成。應瞭解，儘管元件晶粒用作實例，但包含且不限於封裝、記憶體堆疊（諸如高頻寬記憶體（High-Bandwidth Memory；HBM）堆疊）或類似者的其他類型的封裝組件可用以置換元件晶粒122。
多個接合接墊132及多個焊料區134形成於多個元件晶粒122的表面處。相應製程在如圖25中所示的製程流程200中示出為製程208。接合接墊132及焊料區134的形成製程及材料可類似於接合接墊32及焊料區34的形成製程及材料（圖1）。例如使用探針卡140來探測元件晶粒122，使得發現有缺陷的元件晶粒122且判定已知良好的晶粒。對多個元件晶粒122中的每一者執行探測。在探測之後，晶圓120在晶粒切割製程中單體化以將多個元件晶粒122彼此分離。相應製程在如圖25中所示的製程流程200中示出為製程210。保持已知良好的晶粒122且丟棄有缺陷的晶粒122。
接著，參考圖4，多個已知良好的晶粒122接合至晶圓20中的多個已知良好的晶粒22。相應製程在如圖25中所示的製程流程200中示出為製程212。儘管示出一個元件晶粒122及一個元件晶粒22，但存在經接合的多個元件晶粒22及122。元件晶粒122為呈晶粒形式的離散晶粒，而元件晶粒22為呈晶圓形式的未經切割的晶圓20的部分。接合製程包含將助焊劑（flux）施加至焊料區34上，將已知良好的晶粒122放置於已知良好的晶粒22上，以及執行回焊製程，使得焊料區34及焊料區134熔融以形成焊料區35。在回焊製程之後，底部填充物42經施配至元件晶粒122與相應下伏的元件晶粒22之間的間隙中，且接著經固化。貫穿描述，包含晶圓20的結構及接合於其上的多個元件晶粒122共同地稱為經重建構晶圓44。
參考圖5，多個元件晶粒122包封在包封體46中。相應製程在如圖25中所示的製程流程200中示出為製程214。包封體46填充相鄰元件晶粒122之間的間隙。包封體46可為或可包括模製化合物、模製底部填充物、環氧樹脂（epoxy）及/或樹脂。在包封之後，包封體46的頂部表面高於元件晶粒122的頂部表面。包封體46可包含可為聚合物、樹脂、環氧樹脂或類似者的基材46A（圖24），及基材46A中的填充劑顆粒46B。填充劑顆粒46B可為諸如SiO2 、Al2 O3 、矽石或類似者的介電材料的顆粒，且可具有球形形狀。此外，球形的填充劑顆粒46B可具有相同或不同直徑。在包封製程之後，執行平坦化製程以減小包封體46的厚度，且使包封體46的頂部表面齊平。此外，使得包封體46的頂部表面平坦以用於後續製程。
探針接墊36用於探測，且不用於接合至其他封裝組件。在包封之後，包封體46可與包含多個探針接墊36及可能包含多個焊料區38的多個電連接件的多個側壁接觸。舉例而言，當在探測之後移除多個焊料區38時，多個探針接墊36的所有的多個側壁及多個頂部表面將與包封體46實體接觸。當在探測之後不蝕刻多個焊料區38時，多個焊料區38具有接觸探多個針接墊36的多個底部表面，而多個焊料區38的所有的多個側壁及多個頂部表面可與包封體46接觸。
圖6至圖9以及圖10A（或圖10B）示出用於經重建構晶圓44的背側內連線結構的形成，其背側內連線結構在晶圓20的背側上。參考圖6，經重建構晶圓44經由釋放膜（release film）50貼合至載板52。相應製程在如圖25中所示的製程流程200中示出為製程216。為黏著膜的晶粒貼合膜（Die-Attach Film；DAF）48亦可用以將經重建構晶圓44貼合至釋放膜50。釋放膜50可由聚合物類材料（諸如光熱轉換（Light-To-Heat-Conversion；LTHC）材料）形成，當經受來自光（諸如雷射光束）的熱時所述聚合物類材料可分解。碳黑顆粒可添加至釋放膜50中以改善能量吸收。
對晶圓20執行背側研磨製程以移除基底24的部分，直至顯露出穿孔25。相應製程在如圖25中所示的製程流程200中示出為製程218。接著，如圖7中所示，（例如經由蝕刻）使基底24略微凹陷，使得穿孔25自基底24的背表面凸出。相應製程在如圖25中所示的製程流程200中示出為製程220。接著例如執行濕式清潔製程以移除在蝕刻製程中產生的聚合物。
參考圖8，沈積介電層54，接著執行諸如CMP製程或機械研磨製程的平坦化製程以再暴露出穿孔25。相應製程在如圖25中所示的製程流程200中示出為製程222。介電層54可由氮化矽、氧化矽、氮氧化矽或類似者形成，或包括氮化矽、氧化矽、氮氧化矽或類似者。沈積製程可經由電漿增強化學氣相沈積（PECVD）、原子層沈積(Atomic Layer Deposition；ALD)或類似者來執行。在平坦化製程之後，穿孔25亦穿透介電層54，如圖8中所示。
參考圖9，形成介電（隔離）層56。相應製程在如圖25中所示的製程流程200中示出為製程224。根據本揭露的一些實施例，介電層56由諸如PBO、聚醯亞胺或類似者的聚合物形成。形成方法可包含塗佈呈可流動形式的介電層56，且接著固化介電層56。根據本揭露的替代性實施例，介電層56由諸如氮化矽、氧化矽或類似者的無機介電材料形成。形成方法可包含CVD、ALD、PECVD或其他可適用的沈積方法。接著例如經由微影製程形成多個開口58。根據介電層56由光敏性材料（諸如PBO或聚醯亞胺）形成的一些實施例，開口58的形成涉及使用微影罩幕(未示出)的曝光製程(photo exposure process)及顯影製程。經由開口58暴露出穿孔25。
接著，參考圖10A，形成包含多個導電柱60及多個通孔61的多個非焊料導電特徵。相應製程在如圖25中所示的製程流程200中示出為製程226。通孔61延伸至介電層56中以結合至穿孔25，且導電柱60連接至穿孔25。根據本揭露的一些實施例，在鍍覆製程中形成導電柱60及通孔61，所述鍍覆製程包含沈積金屬晶種層（未示出），在金屬晶種層上方形成且圖案化鍍覆罩幕（諸如光阻（未示出）），以及在金屬晶種層上方鍍覆諸如銅及/或鋁的金屬材料。導電柱60的金屬材料為非焊料金屬材料。金屬晶種層及經鍍覆金屬材料可由相同材料或不同材料形成。接著移除經圖案化鍍覆罩幕，接著蝕刻先前由經圖案化鍍覆罩幕覆蓋的金屬晶種層的部分。
在多個導電柱60的頂部，可形成多個焊料區62。根據一些實施例，焊料區62經由鍍覆形成，且用於形成導電柱60及通孔61的相同鍍覆罩幕可用於鍍覆焊料區62。回焊焊料區62以使其具有圓形頂部表面。可存在或可不存在流動至導電柱60的側壁的焊料區62的一些部分。接著使用探針卡64執行探測製程以測試經重建構晶圓44的電路及功能性。舉例而言，可測試元件晶粒122及元件晶粒22在其接合之後的經結合功能。相應製程在如圖25中所示的製程流程200中示出為製程228。根據一些實施例，在探測製程之後，例如經由蝕刻製程移除焊料區62。根據替代性實施例，焊料區62未蝕刻且經由如圖16A或圖16B中所示的後續平坦化製程移除。因此，焊料區62繪示為短劃線以表示此時其可移除或可保持不移除。
在形成導電柱60之後，導電柱60可保持不覆蓋，如圖10A中所示，且可執行諸如圖11中所示的製程的後續製程。根據替代性實施例，如圖10B中所示，形成介電層66以包封導電柱60。根據一些實施例，介電層66由諸如PBO、聚醯亞胺或類似者的聚合物形成。舉例而言，介電層66可由低溫聚醯亞胺（low-temperature polyimide；LTPI）形成。
接著，經重建構晶圓44貼合至膠帶68，如圖11中所示。例如藉由將光束（諸如雷射光束）投射於釋放膜50上以使經重建構晶圓44自載板52卸下（圖10A或圖10B），且光穿透透明的載板52。相應製程在如圖25中所示的製程流程200中示出為製程230。因此分解釋放膜50，且經重建構晶圓44自載板52釋放。根據形成介電層66的一些實施例，介電層66貼合至膠帶68，如圖11中所示。根據不形成介電層66的其他實施例，導電柱60（及焊料區62（若存在））突出至膠帶68中。
在後續製程中，在清潔製程中移除DAF 48，接著執行諸如CMP製程或機械研磨製程的平坦化製程以移除包封體46的過量部分，直至暴露出半導體基底124。亦藉由平坦化製程薄化半導體基底124。相應製程在如圖25中所示的製程流程200中示出為製程232。圖12中繪示所得結構。
參考圖13，經重建構晶圓44以及貼合於其上的膠帶68進一步經由DAF 72貼合至框架70。接著，參考圖14，移除膠帶68，使得暴露出介電層66（若已形成）、下伏的焊料區62（當未蝕刻時）或導電柱60。接著經由晶粒切割執行單體化製程，使得經重建構晶圓44分離成亦包含晶粒堆疊的多個封裝44'。相應製程在如圖25中所示的製程流程200中示出為製程234。
接著封裝44'用以形成積體扇出型（Integrated Fan-Out；InFO）封裝。參考圖15A，多個封裝44'經由多個DAF 80放置於載板74及釋放膜76上方。接著，執行包封製程，且將多個封裝44'包封在包封體82中。相應製程在如圖25中所示的製程流程200中示出為製程236。包封體82亦可包含基材82A（圖24）及基材82A中的填充劑顆粒82B。基材82A及填充劑顆粒82B的材料可分別類似於基材46A及填充劑顆粒46B的材料（圖24）。參考圖16A，執行諸如CMP製程或機械研磨製程的平坦化製程以顯露出多個導電柱60的多個頂部表面。
根據如圖15A及圖16A中所示的實施例，介電層66形成為環繞且接觸多個導電柱60的多個側壁。除不形成介電層66，且包封體82填充至多個導電柱60之間的多個間隙中以外，圖15B及圖16B分別示出類似於圖15A及圖16A中所示的實施例的替代性實施例。因此，在執行如圖16B中所示的平坦化製程之後，包封體82仍具有在元件晶粒22正上方的部分，且所述部分環繞且接觸多個導電柱60。
根據未蝕刻焊料區62的一些實施例（圖10B），移除在導電柱60正上方的焊料區62的部分。當存在焊料區62的一些部分62'流至導電柱60的側壁上時（圖16A及圖16B），所述部分62'可在平坦化製程之後存留。存留的部分62'亦可存在於圖21至圖23中所示的封裝中。
圖17至圖19示出根據一些實施例的用於形成扇出型內連線結構的製程。相應製程在如圖25中所示的製程流程200中示出為製程238。參考圖17，形成介電層84A。根據本揭露的一些實施例，介電層84A由諸如PBO、聚醯亞胺或類似者的聚合物形成，或由諸如氮化矽、氧化矽或類似者的無機介電材料形成。接著例如經由微影製程形成多個開口86。經由開口86暴露出導電柱60。應瞭解，開口86可在所有（儘管僅繪示一些）導電柱60的正上方形成。
接著，參考圖18，形成多個重佈線路（redistribution line，RDL）88A。根據本揭露的一些實施例，在鍍覆製程中形成RDL 88A，所述製程可類似於導電柱60及通孔61的形成。
在後續製程中，如圖19中所示，形成更多介電層84B及更多RDL 88B。貫穿描述，介電層84A及介電層84B共同地稱為介電層84，且RDL 88A及RDL 88B共同地稱為多個RDL 88。RDL 88A及/或RDL 88B橫向地延伸超出相應下伏的封裝44'的邊緣以形成扇出型封裝。接著形成介電層90及多個電連接件92以電性連接至封裝44'。根據一些實施例，電連接件92包括導電（非焊料）柱，且在導電柱的頂部上可包含焊料區或可不包含焊料區。因此形成了InFO內連線結構94。貫穿描述，多個DAF 80上方的多個所示出結構共同地稱為經重建構晶圓96。
在後續製程中，經重建構晶圓96自載板74剝離，接著例如經由CMP製程或機械研磨製程來移除DAF 80。接著可執行單體化製程以將經重建構晶圓96分離成分離的多個封裝96'。相應製程在如圖25中所示的製程流程200中示出為製程240。圖20中繪示實例封裝96'。
圖21至圖23示出基於形成於前述製程中的封裝44'（圖14）或封裝96'（圖20）所形成的封裝。圖21示出根據一些實施例的所形成的封裝，其中如圖14中所示的隨單體化製程而形成的封裝44'經由多個焊料區102接合至封裝組件98。封裝組件98可為封裝基底、另一封裝、印刷電路板（Printed Circuit Board，PCB）或類似者。底部填充物106施配至封裝44'與封裝組件98之間的間隙中。多個焊料區104形成於封裝組件98的底部處。因此形成了封裝110。
圖22及圖23示出根據替代性實施例的封裝110的形成。應瞭解，圖22及圖23中所示的封裝96'經修改以類似於如圖20中所示的封裝96'及略微不同於如圖20中所示的封裝96'。封裝96'經由多個焊料區102接合至對應的封裝組件98。根據替代性實施例，如圖20中所示的封裝96'可直接接合（而不經修改）至封裝組件98以形成封裝110。如圖22中所示的封裝96'與圖20中的封裝96'的不同之處在於，兩個元件晶粒122接合至相同元件晶粒22。如圖23中所示的封裝96'與圖20中的封裝96'的不同之處在於，兩個封裝44'包含於封裝96'中。所屬領域中具通常知識者將認識到根據本揭露的實施例所提供的具有教示的這些封裝的形成。
圖24示出根據一些實施例的圖20中的區112的放大圖。歸因於用於封裝44'的單體化的晶粒切割製程，切割了包封體46的球形的顆粒46B'，且因此在包封體46與包封體82之間的界面處存在部分的顆粒46B'，所述顆粒46B'為歸因於晶粒切割製程而部分地經切割的顆粒。因此包封體46與包封體82之間的界面為可區分的。此外，歸因於在形成內連線結構之前執行的平坦化製程（圖16A），研磨了包封體82的球形的顆粒82B'，且因此在包封體82與介電層84A之間的界面處存在部分的顆粒82B'。
在上文所示出的實施例中，根據本揭露的一些實施例論述一些製程及特徵以形成三維（three-dimensional；3D）封裝。亦可包含其他特徵及製程。舉例而言，可包含測試結構以輔助對3D封裝或三維積體電路（three dimensional integrated circuit，3DIC）元件的驗證測試。測試結構可包含例如形成於重佈線層中或形成於基底上的測試接墊，其允許測試3D封裝或3DIC、探針及/或探針卡（probe card）的使用以及類似者。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可與併入有對已知良好的晶粒的中間驗證的測試方法結合使用，以增加良率且降低成本。
本揭露的實施例具有一些有利特徵。在封裝的形成中，可執行多個探測製程以測試元件晶粒，使得經接合的元件晶粒為已知良好的晶粒。因此提高製造良率，且因此減少製造成本。根據實施例所形成的封裝可包含與包封體接觸的探針接墊（可能地包含焊料區）。此外，執行InFO製程以在包含經由接合堆疊的兩個或大於兩個晶粒的晶粒堆疊上形成內連線結構。因此，InFO內連線結構可置換習知封裝基底。由於使用InFO製程，因此在InFO內連線結構與晶粒堆疊之間不使用焊料區。更確切而言，InFO內連線結構中的RDL與晶粒堆疊的電連接件直接接觸。
根據本揭露的一些實施例，一種方法包括：將第一元件晶粒接合至第二元件晶粒；將所述第一元件晶粒包封在第一包封體中；對所述第二元件晶粒執行背側研磨製程以顯露出所述第二元件晶粒中的多個穿孔；在所述第二元件晶粒上形成多個第一電連接件以形成第一封裝，其中所述第一封裝包括所述第一元件晶粒及所述第二元件晶粒；將所述第一封裝包封在第二包封體中；以及形成與所述第一封裝及所述第二包封體交疊的內連線結構，其中所述內連線結構包括多個第二電連接件。在一實施例中，形成所述內連線結構包括：形成與所述第一封裝及所述第二包封體交疊的介電層；在所述介電層中形成多個開口，其中經由所述多個開口顯露出所述多個第一電連接件；以及形成延伸至所述多個開口中的多個重佈線路以接觸所述多個穿孔。在一實施例中，所述第二元件晶粒包括多個探針接墊，且所述方法更包括使用所述多個探針接墊測試所述第二元件晶粒，且其中所述第一包封體與所述多個探針接墊實體接觸。在一實施例中，所述方法更包括：在所述測試之前，在所述多個探針接墊上形成多個焊料區；以及在所述測試之後且在所述第一元件晶粒接合至所述第二元件晶粒之前，移除所述多個焊料區。在一實施例中，所述方法更包括：在所述測試之前，在所述多個探針接墊上形成多個焊料區，其中所述測試是藉由接觸所述多個焊料區上的多個探針引腳執行，且其中在將所述第一元件晶粒包封於所述第一包封體中之後，所述多個焊料區與所述第一包封體實體接觸。在一實施例中，所述第二包封體填充所述多個第一電連接件之間的多個間隔，且將所述第一封裝包封在所述第二包封體中包括平坦化製程以使所述多個第一電連接件的多個表面與所述第二包封體的表面齊平。在一實施例中，所述方法更包括將填充介電材料施配至所述多個第一電連接件之間的多個間隔中，且將所述第一封裝包封在所述第二包封體中包括平坦化製程以使所述多個第一電連接件的多個表面與所述填充介電材料的表面齊平。在一實施例中，所述方法更包括：切割所述第二包封體及所述內連線結構以形成第二封裝，其中所述第二封裝包括所述第一元件晶粒及所述第二元件晶粒；以及將所述第二封裝接合至封裝基底。
根據本揭露的一些實施例，一種結構包括封裝，所述封裝包括第一晶粒及第二晶粒。所述第一晶粒包括多個第一接合接墊。所述第二晶粒包括：多個第二接合接墊，接合至所述多個第一接合接墊；半導體基底，在所述多個第二接合接墊之下；多個穿孔，穿透所述半導體基底；以及多個第一電連接件，在所述多個穿孔之下且連接至所述多個穿孔。所述封裝更包括：第一包封體，將所述第一晶粒包封於其中。所述結構更包括：第二包封體，將所述封裝包封於其中；以及內連線結構，在所述封裝之下。所述內連線結構包括：介電層，在所述第二包封體及所述封裝之下且接觸所述第二包封體及所述封裝；以及多個重佈線路，延伸至所述介電層中以接觸所述多個第一電連接件。在一實施例中，所述多個重佈線路由非焊料材料形成。在一實施例中，所述多個重佈線路的部分在所述第二包封體的正下方。在一實施例中，所述第一包封體及所述第二包封體具有可區分的界面。在一實施例中，所述第二晶粒更包括多個探針接墊，且其中所述多個探針接墊的所有的多個側壁及多個頂部表面與所述第一包封體接觸。在一實施例中，所述第二晶粒更包括：多個探針接墊；以及多個焊料區，在所述多個探針接墊上方且接觸所述多個探針接墊，其中所述多個焊料區的所有的多個側壁及多個頂部表面與所述第一包封體接觸。在一實施例中，所述結構更包括：封裝基底，在所述內連線結構之下；以及多個焊料區，將所述內連線結構實體地接合至所述封裝基底。
根據本揭露的一些實施例，一種結構包括封裝，所述封裝包括：元件晶粒，包含半導體基底；封裝組件，在所述元件晶粒上方且接合至所述元件晶粒；第一模製化合物，將所述封裝組件模製於其中；介電層，在所述元件晶粒之下，其中所述介電層的多個邊緣與所述第一模製化合物的對應的多個邊緣及所述元件晶粒的對應的多個邊緣齊平；以及多個非焊料導電特徵，在所述元件晶粒的所述半導體基底之下，其中所述多個非焊料導電特徵延伸至所述介電層中。所述結構更包括：多個重佈線路，在所述多個非焊料導電特徵之下且實體地接觸所述多個非焊料導電特徵，其中所述多個重佈線路分佈於橫向地延伸超出所述封裝的對應的多個第一邊緣的區域中。在一實施例中，所述結構更包括：第二模製化合物，環繞所述封裝；以及多個介電層，其中所述多個重佈線路延伸至所述多個介電層中，且其中所述第二模製化合物的多個第二邊緣與所述多個介電層的對應的多個第三邊緣齊平。在一實施例中，所述第二模製化合物包括在所述介電層正下方的部分，且所述第二模製化合物與所述多個非焊料導電特徵實體接觸。在一實施例中，所述結構更包括位於所述封裝中且將所述多個非焊料導電特徵包封於其中的聚合物層，其中所述聚合物層的多個額外邊緣與所述第一模製化合物的對應多個邊緣及所述元件晶粒的對應的多個第四邊緣齊平。在一實施例中，所述元件晶粒包括多個電氣導電特徵，且其中所述多個電氣導電特徵包括接觸所述第一模製化合物的多個頂部表面及多個側壁。
前文概述若干實施例的特徵，以使得所屬領域中具通常知識者可更佳地理解本揭露的態樣。所屬領域中具通常知識者應瞭解，其易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬領域中具通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
20、120:晶圓 22、122:元件晶粒/晶粒 24:半導體基底/基底 25:穿孔 26:積體電路元件 28、94、128:內連線結構 30、130:表面介電層 32、132:接合接墊 34、35、38、62、102、104、134:焊料區 36:探針接墊 40、64、140:探針卡 42、106:底部填充物 44、96:經重建構晶圓 44'、96'、110:封裝 46、82:包封體 46A、82A:基材 46B、82B:填充劑顆粒 46B'、82B':顆粒 48、80、72:晶粒貼合膜 50、76:釋放膜 52、74:載板 54、56、66、84、84A、84B、90:介電層 58、86:開口 60:導電柱 61:通孔 62':部分 68:膠帶 70:框架 88、88A、88B:重佈線路 92:電連接件 98:封裝組件 112:區 124:半導體基底 200:製程流程 202、204、206、208、210、212、214、216、218、220、222、224、226、228、230、232、234、236、238、240:製程 P1、P2:間距 W1、W2:橫向尺寸
結合附圖閱讀以下詳細描述會最佳地理解本揭露的各態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。實際上，為論述清楚起見，可任意增大或減小各種特徵的尺寸。 圖1至圖9、圖10A、圖10B、圖11至圖14、圖15A、圖16A、圖15B、圖16B以及圖17至圖20示出根據一些實施例的形成晶粒堆疊的中間階段的橫截面視圖。 圖21示出根據一些實施例的包含晶粒堆疊的封裝的橫截面視圖。 圖22及圖23示出根據一些實施例的包含晶粒堆疊的封裝的橫截面視圖。 圖24示出根據一些實施例的封裝的部分的放大視圖。 圖25示出根據一些實施例的用於形成晶粒堆疊的製程流程。
22、122:元件晶粒/晶粒
24:半導體基底/基底
25:穿孔
32:接合接墊
35、38:焊料區
36:探針接墊
44':封裝
46、82:包封體
54、56、66、84、84A、84B、90:介電層
60:導電柱
88、88A、88B:重佈線路
92:電連接件
94:內連線結構
96':封裝
112:區
124:半導體基底

Claims (20)

  1. 一種晶粒堆疊結構的形成方法，包括： 將第一元件晶粒接合至第二元件晶粒； 將所述第一元件晶粒包封在第一包封體中； 對所述第二元件晶粒執行背側研磨（grinding）製程以顯露出所述第二元件晶粒中的多個穿孔； 在所述第二元件晶粒上形成多個第一電連接件以形成第一封裝，其中所述第一封裝包括所述第一元件晶粒及所述第二元件晶粒； 將所述第一封裝包封在第二包封體中；以及 形成實體地接觸所述第一封裝及所述第二包封體的內連線結構，其中所述內連線結構包括多個第二電連接件。
  2. 如請求項1所述的晶粒堆疊結構的形成方法，其中形成所述內連線結構包括： 形成與所述第一封裝及所述第二包封體交疊的介電層； 在所述介電層中形成多個開口，其中經由所述多個開口顯露出所述多個第一電連接件；以及 形成延伸至所述多個開口中的多個重佈線路以接觸所述多個穿孔。
  3. 如請求項1所述的晶粒堆疊結構的形成方法，其中所述第二元件晶粒包括多個探針接墊，且所述方法更包括使用所述多個探針接墊測試所述第二元件晶粒，且其中所述第一包封體與所述多個探針接墊實體接觸。
  4. 如請求項3所述的晶粒堆疊結構的形成方法，更包括： 在所述測試之前，在所述多個探針接墊上形成多個焊料區；以及 在所述測試之後且在所述第一元件晶粒接合至所述第二元件晶粒之前，移除所述多個焊料區。
  5. 如請求項3所述的晶粒堆疊結構的形成方法，更包括： 在所述測試之前，在所述多個探針接墊上形成多個焊料區，其中所述測試是藉由接觸所述多個焊料區上的多個探針引腳執行，且其中在將所述第一元件晶粒包封於所述第一包封體中之後，所述多個焊料區與所述第一包封體實體接觸。
  6. 如請求項1所述的晶粒堆疊結構的形成方法，其中所述第二包封體填充所述多個第一電連接件之間的多個間隔，且將所述第一封裝包封在所述第二包封體中包括平坦化製程以使所述多個第一電連接件的多個表面與所述第二包封體的表面齊平。
  7. 如請求項1所述的晶粒堆疊結構的形成方法，更包括將填充介電材料施配至所述多個第一電連接件之間的多個間隔中，且將所述第一封裝包封在所述第二包封體中包括平坦化製程以使所述多個第一電連接件的多個表面與所述填充介電材料的表面齊平。
  8. 如請求項1所述的晶粒堆疊結構的形成方法，更包括： 切割所述第二包封體及所述內連線結構以形成第二封裝，其中所述第二封裝包括所述第一元件晶粒及所述第二元件晶粒；以及 將所述第二封裝接合至封裝基底。
  9. 一種晶粒堆疊結構，包括： 封裝，包括： 第一晶粒，包括多個第一接合接墊；第二晶粒，包括： 多個第二接合接墊，接合至所述多個第一接合接墊； 半導體基底，在所述多個第二接合接墊之下； 多個穿孔，穿透所述半導體基底；以及 多個第一電連接件，在所述多個穿孔之下且連接至所述多個穿孔；以及 第一包封體，將所述第一晶粒包封於其中； 第二包封體，將所述封裝包封於其中；以及 內連線結構，在所述封裝之下，其中所述內連線結構包括： 介電層，在所述第二包封體及所述封裝之下且接觸所述第二包封體及所述封裝；以及多個重佈線路，延伸至所述介電層中以接觸所述多個第一電連接件。
  10. 如請求項9所述的晶粒堆疊結構，其中所述多個重佈線路由非焊料材料形成。
  11. 如請求項9所述的晶粒堆疊結構，其中所述多個重佈線路的部分在所述第二包封體的正下方。
  12. 如請求項9所述的晶粒堆疊結構，其中所述第一包封體及所述第二包封體具有可區分的界面。
  13. 如請求項9所述的晶粒堆疊結構，其中所述第二晶粒更包括多個探針接墊，且其中所述多個探針接墊的所有的多個側壁及多個頂部表面與所述第一包封體接觸。
  14. 如請求項9所述的晶粒堆疊結構，其中所述第二晶粒更包括： 多個探針接墊；以及 多個焊料區，在所述多個探針接墊上方且接觸所述多個探針接墊，其中所述多個焊料區的所有的多個側壁及多個頂部表面與所述第一包封體接觸。
  15. 如請求項9所述的晶粒堆疊結構，更包括： 封裝基底，在所述內連線結構之下；以及 多個焊料區，將所述內連線結構實體地接合至所述封裝基底。
  16. 一種晶粒堆疊結構，包括： 封裝，包括： 元件晶粒，包括半導體基底； 封裝組件，在所述元件晶粒上方且接合至所述元件晶粒； 第一模製化合物，將所述封裝組件模製於其中； 介電層，在所述元件晶粒之下，其中所述介電層的多個邊緣與所述第一模製化合物的對應的多個邊緣及所述元件晶粒的對應的多個邊緣齊平；以及 多個非焊料導電特徵，在所述元件晶粒的所述半導體基底之下，其中所述多個非焊料導電特徵延伸至所述介電層中；以及 多個重佈線路，在所述多個非焊料導電特徵之下且實體地接觸所述多個非焊料導電特徵，其中所述多個重佈線路分佈於橫向地延伸超出所述封裝的對應的多個第一邊緣的區域中。
  17. 如請求項16所述的晶粒堆疊結構，更包括： 第二模製化合物，環繞所述封裝；以及 多個介電層，其中所述多個重佈線路延伸至所述多個介電層中，且其中所述第二模製化合物的多個第二邊緣與所述多個介電層的對應的多個第三邊緣齊平。
  18. 如請求項17所述的晶粒堆疊結構，其中所述第二模製化合物包括在所述介電層正下方的部分，且所述第二模製化合物與所述多個非焊料導電特徵實體接觸。
  19. 如請求項16所述的晶粒堆疊結構，更包括位於所述封裝中且將所述多個非焊料導電特徵包封於其中的聚合物層，其中所述聚合物層的多個額外邊緣與所述第一模製化合物的對應的所述多個邊緣及所述元件晶粒的對應的多個第四邊緣齊平。
  20. 如請求項16所述的晶粒堆疊結構，其中所述元件晶粒包括多個電氣導電特徵，且其中所述多個電氣導電特徵包括接觸所述第一模製化合物的多個頂部表面及多個側壁。
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