TW202135170A - Semiconductor device and semiconductor device manufacturing method including a low-concentration first conductivity type semiconductor layer, a second conductivity type semiconductor layer and a passivation film - Google Patents
Semiconductor device and semiconductor device manufacturing method including a low-concentration first conductivity type semiconductor layer, a second conductivity type semiconductor layer and a passivation film Download PDFInfo
- Publication number
- TW202135170A TW202135170A TW110105553A TW110105553A TW202135170A TW 202135170 A TW202135170 A TW 202135170A TW 110105553 A TW110105553 A TW 110105553A TW 110105553 A TW110105553 A TW 110105553A TW 202135170 A TW202135170 A TW 202135170A
- Authority
- TW
- Taiwan
- Prior art keywords
- conductivity type
- semiconductor layer
- type semiconductor
- concentration
- low
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 232
- 238000002161 passivation Methods 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910001385 heavy metal Inorganic materials 0.000 claims abstract description 26
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 17
- 239000011521 glass Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 11
- 229910052697 platinum Inorganic materials 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 146
- 230000000052 comparative effect Effects 0.000 description 10
- 239000002344 surface layer Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000287 alkaline earth metal oxide Inorganic materials 0.000 description 1
- LKTZODAHLMBGLG-UHFFFAOYSA-N alumanylidynesilicon;$l^{2}-alumanylidenesilylidenealuminum Chemical compound [Si]#[Al].[Si]#[Al].[Al]=[Si]=[Al] LKTZODAHLMBGLG-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Noodles (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
本發明涉及具有鈍化層的半導體裝置及半導體裝置的製造方法。The present invention relates to a semiconductor device having a passivation layer and a method of manufacturing the semiconductor device.
一直以來,人們都在嘗試提供對雷電突波等具有高耐久性的半導體裝置。例如在日本特開2012-165013號公報中,揭露了一種半導體裝置,其包括:For a long time, attempts have been made to provide semiconductor devices with high durability against lightning surges and the like. For example, in Japanese Patent Laid-Open No. 2012-165013, a semiconductor device is disclosed, which includes:
第一導電型半導體層;擴散區域,由選擇性地設置在第一導電型半導體層的表面層上的第二導電型半導體區域構成,且位於大於等於12.6μm,且小於等於30μm的深度;以及低壽命區域,通過使在整個第一導電型半導體層以及所述擴散區域上,從比擴散區域與第一導電型半導體層之間的接合介面即PN接面的最深位置淺的位置直至比PN接面的最深位置深的位置上含有通過He離子照射而形成的壽命殺手(Life-time killer),從而使載流子的壽命比其他區域短。The first conductivity type semiconductor layer; the diffusion region is composed of a second conductivity type semiconductor region selectively provided on the surface layer of the first conductivity type semiconductor layer, and is located at a depth of 12.6 μm or more and 30 μm or less; and The low-life region is formed on the entire first conductivity type semiconductor layer and the diffusion region from a position shallower than the deepest position of the PN junction, which is the junction interface between the diffusion region and the first conductivity type semiconductor layer, to a position shallower than PN The deepest part of the junction contains a life-time killer formed by He ion irradiation, so that the life-time of the carrier is shorter than other areas.
在日本特開2012-165013號公報中,雖然是以在壓低雷電突波的耐久性的同時,降低順向電壓VF為目的,但是除了需要He離子照射這一特有製程外,還無法將順向電壓抑制得足夠低。In Japanese Patent Laid-Open No. 2012-165013, although the goal is to reduce the durability of lightning surges and reduce the forward voltage VF, in addition to the special process of He ion irradiation, it is not possible to reduce the forward voltage. The voltage is suppressed sufficiently low.
鑒於上述情況,本發明提供了一種能夠緩和電流集中、獲得高雷電突波耐久性的半導體裝置。In view of the above-mentioned circumstances, the present invention provides a semiconductor device capable of alleviating current concentration and obtaining high lightning surge durability.
概念1
本發明涉及的一種半導體裝置,其特徵在於,包括:A semiconductor device related to the present invention is characterized in that it comprises:
低濃度第一導電型半導體層,由第一導電型構成;The low-concentration first conductivity type semiconductor layer is composed of the first conductivity type;
第二導電型半導體層,設置在所述低濃度第一導電型半導體層上,且由第二導電型構成;以及The second conductivity type semiconductor layer is provided on the low-concentration first conductivity type semiconductor layer and is composed of the second conductivity type; and
鈍化層,設置在第二導電型半導體層的一部分上,The passivation layer is provided on a part of the second conductivity type semiconductor layer,
其中,距離所述第二導電型半導體層的一側的面30μm以內的距離處的摻雜濃度小於等於1×1019 cm-3 ,且大於等於 1×1017 cm-3 ,Wherein, the doping concentration at a distance within 30 μm from the side surface of the second conductivity type semiconductor layer is less than or equal to 1×10 19 cm -3 , and is greater than or equal to 1×10 17 cm -3 ,
所述第二導電型半導體層、以及所述低濃度第一導電型半導體層與所述第二導電型半導體層之間的介面含有重金屬。The second conductivity type semiconductor layer and the interface between the low-concentration first conductivity type semiconductor layer and the second conductivity type semiconductor layer contain heavy metals.
概念2
在上述概念1所述的半導體裝置中,所述第二導電型半導體層的厚度大於等於50μm。In the semiconductor device described in
概念3Concept 3
在上述概念1或概念2所述的半導體裝置中,在距離所述第二導電型半導體層的一側的面20μm以內的距離處的摻雜濃度大於等於1×1018
cm-3
。In the semiconductor device described in
概念4Concept 4
在上述概念1或概念2所述的半導體裝置中,在所述低濃度第一導電型半導體層的另一側,設置有第一導電型的摻雜濃度比所述低濃度第一導電型半導體層高的高濃度第一導電型半導體層,In the semiconductor device described in
起始於所述第一導電型半導體層的端面,直至所述高濃度第一導電型半導體層的第一導電型的摻雜濃度達到所述低濃度第一導電型半導體層的第一導電型的摻雜濃度的1000倍為止的厚度方向上的距離D1、與起始於所述低濃度第一導電型半導體層的端面,直至所述第二導電型半導體層的第二導電型的摻雜濃度達到所述低濃度第一導電型半導體層的第一導電型的摻雜濃度的1000倍為止的厚度方向上的距離D2之間的關係滿足下述(公式1):Starting from the end surface of the first conductivity type semiconductor layer, until the doping concentration of the first conductivity type of the high concentration first conductivity type semiconductor layer reaches the first conductivity type of the low concentration first conductivity type semiconductor layer The distance D1 in the thickness direction up to 1000 times the doping concentration of the doping concentration and the doping of the second conductivity type starting from the end face of the low-concentration first conductivity type semiconductor layer to the second conductivity type semiconductor layer The relationship between the distance D2 in the thickness direction until the concentration reaches 1000 times the doping concentration of the first conductivity type of the low-concentration first conductivity type semiconductor layer satisfies the following (Equation 1):
1.1×D2≥D1≥0.9×D2(公式1)。1.1×D2≥D1≥0.9×D2 (Formula 1).
概念5Concept 5
在上述概念4所述的半導體裝置中,起始於所述低濃度第一導電型半導體層的端面,直至所述第二導電型半導體層的第二導電型的摻雜濃度達到所述低濃度第一導電型半導體層的第一導電型的摻雜濃度的1000倍為止的厚度方向上的距離D2為20μm~40μm。In the semiconductor device described in Concept 4 above, starting from the end face of the low-concentration first conductivity type semiconductor layer, until the second conductivity type doping concentration of the second conductivity type semiconductor layer reaches the low concentration The distance D2 in the thickness direction of the first conductivity type semiconductor layer up to 1000 times the doping concentration of the first conductivity type is 20 μm to 40 μm.
概念6Concept 6
在上述概念1或概念2所述的半導體裝置中,所述重金屬為鉑。In the semiconductor device described in
概念7
在上述概念1或概念2所述的半導體裝置中,所述鈍化層為玻璃層。In the semiconductor device described in
概念8Concept 8
本發明涉及的一種半導體裝置的製造方法,其特徵在於,包括:The manufacturing method of a semiconductor device according to the present invention is characterized in that it comprises:
準備半導體基板的製程,所述半導體基板具有:由第一導電型構成的低濃度第一導電型半導體層、以及設置在所述低濃度第一導電型半導體層上,且由第二導電型構成的第二導電型半導體層。A process of preparing a semiconductor substrate, the semiconductor substrate having: a low-concentration first conductivity type semiconductor layer composed of a first conductivity type, and a low-concentration first conductivity type semiconductor layer provided on the low-concentration first conductivity type semiconductor layer and composed of a second conductivity type的Second conductivity type semiconductor layer.
在第二導電型半導體層的一部分上設置鈍化層的製程。A process of disposing a passivation layer on a part of the second conductivity type semiconductor layer.
使重金屬滲透到所述第二導電型半導體層內的製程;以及對所述半導體基板以及所述鈍化層加熱的製程。A process of infiltrating heavy metals into the second conductive semiconductor layer; and a process of heating the semiconductor substrate and the passivation layer.
其中,距離所述第二導電型半導體層的一側的面30μm以內的距離處的摻雜濃度小於等於1×1019 cm-3 ,且大於等於 1×1017 cm-3 。Wherein, the doping concentration at a distance within 30 μm from the side surface of the second conductivity type semiconductor layer is less than or equal to 1×10 19 cm -3 , and is greater than or equal to 1×10 17 cm -3 .
所述第二導電型半導體層、以及所述低濃度第一導電型半導體層與所述第二導電型半導體層之間的介面含有重金屬。The second conductivity type semiconductor layer and the interface between the low-concentration first conductivity type semiconductor layer and the second conductivity type semiconductor layer contain heavy metals.
發明效果Invention effect
在本發明中,當採用距離第二導電型半導體層的一側的面30μm以內的距離處的摻雜濃度小於等於1×1019 cm-3 ,且大於等於 1×1017 cm-3 ,且第二導電型半導體層、以及低濃度第一導電型半導體層與第二導電型半導體層之間的介面含有重金屬的形態的情況下,就能夠緩和電流集中、獲得高雷電突波耐久性。In the present invention, when the doping concentration at a distance within 30 μm from the surface of the second conductivity type semiconductor layer is less than or equal to 1×10 19 cm -3 , and greater than or equal to 1×10 17 cm -3 , and When the second conductivity type semiconductor layer and the interface between the low concentration first conductivity type semiconductor layer and the second conductivity type semiconductor layer contain heavy metals, current concentration can be alleviated and high lightning surge durability can be obtained.
第一實施例The first embodiment
本實施例的半導體裝置為二極體、閘流體等具有PN接面的裝置。半導體裝置例如圖1所示,可以包括:高濃度第一導電型半導體層11;設置在高濃度第一導電型半導體層11上,且由第一導電型摻雜濃度比高濃度第一導電型半導體層11低的第一導電型構成的低濃度第一導電型半導體層12;設置在低濃度第一導電型半導體層12上,且由第二導電型構成的第二導電型半導體層13;以及設置在第二導電型半導體層13的一部分上的鈍化膜(如後述例如玻璃膜50 )。第一導電型例如為n型,第二導電型例如為p型。不過,並不限於此,第一導電型也可以是p型,第二導電型也可以是n型。本實施例的半導體裝置的額定電壓可以大於等於600V。第二導電型半導體層13可以設置在低濃度第一導電型半導體層12的一側的整個面上。通過這樣在低濃度第一導電型半導體層12一側的整個面上設置第二導電型半導體層13,就能夠切實地承受後述具有高di/dt的雷電突波。The semiconductor device of this embodiment is a device with a PN junction such as a diode and a thyristor. For example, as shown in FIG. 1, the semiconductor device may include: a high-concentration first conductivity
距離第二導電型半導體層13的一側的面30μm以內的距離處的摻雜濃度可以小於等於1×1019
cm-3
,且大於等於1×1017
cm-3
。第二導電型半導體層13、以及低濃度第一導電型半導體層12與第二導電型半導體層13之間的介面可以含有重金屬。重金屬可列舉金、鉑等,較佳實施例為使用鉑。重金屬不僅可以包含在低濃度第一導電型半導體層12與第二導電型半導體層13之間的介面處,也可以包含在低濃度第一導電型半導體層12的內部,還可以遍及整個低濃度第一導電型半導體層12。另外,在本實施例中,將圖1的上方側稱為一側,將圖1的下方側稱為另一側。低濃度第一導電型半導體層12摻雜濃度例如小於等於1×1015
cm-3
,且大於等於1×1013
cm-3
,典型值為1×1014
cm-3
。The doping concentration at a distance within 30 μm from the side surface of the second conductivity
第二導電型半導體層13的厚度可以大於等於50μm,也可以大於等於60μm。The thickness of the second conductivity
距離第二導電型半導體層13的一側的面20μm以內的距離處的摻雜濃度可以大於等於1×1018
cm-3
。The doping concentration at a distance within 20 μm from the side surface of the second conductivity
起始於第一導電型半導體層12的端面(另一側的面),直至高濃度第一導電型半導體層11的第一導電型的摻雜濃度達到低濃度第一導電型半導體層12的第一導電型的摻雜濃度的1000倍為止的厚度方向上的距離D1(另一側處的距離)、與起始於低濃度第一導電型半導體層12的端面(一側的面),直至第二導電型半導體層13的第二導電型的摻雜濃度達到低濃度第一導電型半導體層12的第一導電型的摻雜濃度的1000倍為止的厚度方向上的距離D2(一側處的距離)之間的關係滿足下述(公式1)(參照圖6):Starting from the end face (the face on the other side) of the first conductivity
1.1×D2≥D1≥0.9×D2(公式1)。1.1×D2≥D1≥0.9×D2 (Formula 1).
D1和D2大致相等,可以滿足下述(公式2):D1 and D2 are roughly equal, and the following (Equation 2) can be satisfied:
1.05×D2≥D1≥0.95×D2(公式2)1.05×D2≥D1≥0.95×D2 (Formula 2)
D1和D2實質上相等,可以滿足下述(公式3):D1 and D2 are substantially equal and can satisfy the following (Equation 3):
1.01×D2≥D1≥0.99×D2(公式3)1.01×D2≥D1≥0.99×D2 (Formula 3)
起始於低濃度第一導電型半導體層12的端面(一側的面),直至第二導電型半導體層13的第二導電型的摻雜濃度達到低濃度第一導電型半導體層12的第一導電型的摻雜濃度的1000倍為止的厚度方向上的距離D2(一側處的距離)可以為20μm~40μm。可以根據D2的值來調整D1的值,以滿足上述(公式1)、(公式2)和(公式3)中的任一個。作為典型值,D1和D2可以各自為30μm (四捨五入後的30μm )。也可以(參照圖6 )。另外,也可以根據D1的值來調整D2的值。Starting from the end surface (one side surface) of the low-concentration first conductivity
矽基板、碳化矽基板、氮化鎵基板等可以用作高濃度第一導電型半導體層11。第二導電型半導體層13可以藉由向低濃度第一導電型半導體層12注入例如p型摻雜(例如硼)來形成。A silicon substrate, a silicon carbide substrate, a gallium nitride substrate, etc. can be used as the high-concentration first conductivity
如圖1所示,可以在第二導電型半導體層13的正面設置有第一電極20,並且在高濃度第一導電型半導體層11的背面設置有第二電極30。第一電極20例如可以是陽電極,第二電極30例如可以是陰電極。第一電極20例如可以由矽化鋁或矽化鎳構成。第二電極30也可以是含矽化物膜的鎳膜。As shown in FIG. 1, the
也可以在第一電極20的周圍設置作為鈍化膜的玻璃膜50。A
玻璃膜50中使用的玻璃材料例如SiO2
的含量在49.5mol%~64.3mol%的範圍內,Al2
O3
的含量在3.7mol%~14.8mol%的範圍內,B2
O3
的含量在8.4mol%~17.9mol%的範圍內,ZnO的含量在3.9mol%~14.2mol%的範圍內,鹼土金屬的氧化物的含量在7.4mol%~12.9mol%的範圍內。The content of the glass material used in the
上述的半導體裝置可以採用如下方法進行製造。The above-mentioned semiconductor device can be manufactured by the following method.
準備低濃度第一導電型半導體層12(圖2A)。低濃度第一導電型半導體層12可以採用單晶圓。在採用單晶圓的情況下,能夠抑制製造成本。不過,也不限於此,也可以採用磊晶晶圓或擴散晶圓。The low-concentration first conductivity
在低濃度第一導電型半導體層12的一側的面和另一側的面上分別上例如以沉積物設置第二導電型的摻雜表面層16 (圖2B)。作為第二導電型摻雜表面層16的摻雜,例如可以為B (硼)。A doped
在用抗蝕劑膜17覆蓋第二導電型的摻雜表面層16後,對低濃度第一導電型半導體層12的另一側的面進行蝕刻(圖2C)。After covering the doped
接著,在低濃度第一導電型半導體層12的一側的面上形成例如由SiO2
構成的氧化膜19後,在低濃度第一導電型半導體層12的另一側的面上設置第一導電型的摻雜表面層18 (圖3A)。作為第一導電型摻雜表面層18的摻雜,例如可以舉出P (磷)。 Next, an oxide film 19 made of, for example, SiO 2 is formed on one surface of the low-concentration first conductivity
接著,例如在1100℃~1300℃下加熱20小時。通過這樣進行加熱,摻雜區域就會分別在低濃度第一導電型半導體層12的一側和另一側擴大(圖3B)。最終,在低濃度第一導電型半導體層12的一側的面上形成第二導電型半導體層13,在低濃度第一導電型半導體層12的另一側的面上形成摻雜濃度比低濃度第一導電型半導體層12高的高濃度第一導電型半導體層11。各摻雜表面層的厚度可以大於等於50μm,也可以大於等於60μm。Then, heating is performed at, for example, 1100°C to 1300°C for 20 hours. By heating in this way, the doped regions are enlarged on one side and the other side of the low-concentration first conductivity
接著,在第二導電型半導體層13上形成由SiO2 等構成的絕緣膜61 (圖4A )。並且在第一導電型半導體基板11背面形成由SiO2 等構成的絕緣膜62 (圖4A)。 Next, an insulating film 61 made of SiO 2 or the like is formed on the second conductivity type semiconductor layer 13 (FIG. 4A ). In addition, an insulating film 62 made of SiO 2 or the like is formed on the back surface of the first conductive type semiconductor substrate 11 (FIG. 4A ).
接著,將形成的絕緣膜61用作遮罩,對一側的面進行蝕刻,形成檯面槽65 (圖4B )。作為本實施例的蝕刻,可以使用乾蝕刻或濕蝕刻等方式來進行。Next, using the formed insulating
接著,以覆蓋形成的檯面槽65和絕緣膜61的方式,形成由玻璃膜50構成的保護膜(鈍化膜) (圖5A )。Next, a protective film (passivation film) composed of a
接著,通過選擇性地對所形成的絕緣膜61和玻璃膜50進行蝕刻來形成開口部70 (圖5B )。Next, the
接著,在第二導電型半導體層13和玻璃膜50上設置重金屬(圖5B )。作為重金屬可採用鉑。此時,為了在第二導電型半導體層13和玻璃膜50上設置重金屬,可以通過塗布、蒸鍍、濺射等進行沉積。重金屬可以塗布在一側的整個面上,這樣,重金屬就會滲透到第二導電型半導體層13內部、低濃度第一導電型半導體層12與第二導電型半導體層13的介面以及低濃度第一導電型半導體層12內。重金屬也可以分佈在整個低濃度第一導電型半導體層12上。Next, heavy metals are placed on the second conductivity
接著,將半導體基板和玻璃膜50以例如700度~900度加熱10~60分鐘。通過這樣加熱,使重金屬在半導體層內擴散。Next, the semiconductor substrate and the
在如上所述製造的半導體裝置中,在距第二導電型半導體層13的一側的面30μm以內距離處的摻雜濃度為小於等於1×1019
cm-3
,且大於等於1×1017
cm-3
。In the semiconductor device manufactured as described above, the doping concentration at a distance within 30 μm from the surface of one side of the second conductivity
然後,在正面側的開口部70形成第一電極20,在背面側形成第二電極30 (參照圖1 )。Then, the
《效果》"Effect"
接著,對本實施例的效果的進行說明。本發明可以採用《效果》中說明的任何形態。Next, the effect of this embodiment will be described. The present invention can adopt any of the forms described in "Effects".
在本實施例中,距離第二導電型半導體層13的一側的面30μm以內的距離處的摻雜濃度小於等於1×1019
cm-3
,且大於等於 1×1017
cm-3
,且第二導電型半導體層13、以及低濃度第一導電型半導體層12與第二導電型半導體層13之間的介面含有重金屬的形態的情況下,就能夠緩和電流集中,並且可以承受由高di/dt構成的雷電突波(可以得到高的雷電突波耐受性)。從可以獲得如此高的雷電突波耐久性來看,半導體裝置可以是用於轉換器的二極體。In this embodiment, the doping concentration at a distance within 30 μm from the surface of one side of the second conductivity
如果一側的面(上端面)的摻雜濃度超過1×1019 cm-3 ,則鉑等重金屬難以進入,從而就無法加快後述的反向恢復時間(reverse recover time, trr)。If the doping concentration of one side surface (upper end surface) exceeds 1×10 19 cm -3 , it is difficult for heavy metals such as platinum to enter, so that the reverse recovery time (trr) described later cannot be accelerated.
而如果一側的面(上段面)的摻雜濃度小於1×1018
cm-3
的情況下,則難以與第一電極20形成歐姆接觸。因此,使一側的面的摻雜濃度在1×1018
cm-3
以上是有益的。特別是當第一電極20中與第二導電型半導體層13的介面由Ni等構成的情況下特別有益。On the other hand, if the doping concentration of one surface (upper surface) is less than 1×10 18 cm −3 , it is difficult to form an ohmic contact with the
在採用第二導電型半導體層13的厚度為50μm以上的形態的情況下,能夠以充分的厚度保持摻雜濃度高的區域,這樣就特別能夠緩和電流集中。In the case of adopting a form in which the thickness of the second conductivity
在採用了距離第二導電型半導體層13的一側的面20μm以內的距離處的摻雜濃度為1×1018
cm-3
以上的形態的情況下,能夠提高深度較淺的區域中的摻雜濃度,遮掩更就特別能夠提高對雷電突波的耐久性。In the case of adopting a form in which the doping concentration at a distance within 20 μm from the surface of the second conductivity
當起始於第一導電型半導體層12的端面,直至高濃度第一導電型半導體層11的第一導電型的摻雜濃度達到低濃度第一導電型半導體層12的第一導電型的摻雜濃度的1000倍為止的厚度方向上的距離D1、與起始於低濃度第一導電型半導體層12的端面,直至第二導電型半導體層13的第二導電型的摻雜濃度達到低濃度第一導電型半導體層12的第一導電型的摻雜濃度的1000倍為止的厚度方向上的距離D2之間的關係滿足公式: 1.1×D2≥D1≥0.9×D2的情況下,就能夠在一側和另一側上均設置摻雜濃度高的區域。這樣一來,就能夠提高對雷電突波的耐久性(參照圖6以及圖9中的“實施例”)。When starting from the end surface of the first conductivity
當採用起始於低濃度第一導電型半導體層12的端面,直至第二導電型半導體層13的第二導電型的摻雜濃度達到低濃度第一導電型半導體層12的第一導電型的摻雜濃度的1000倍為止的厚度方向上的距離D2為20μm~40μm的形態的情況下,就能夠增大摻雜濃度較高的區域的厚度,這樣一來,就能夠在提高對雷電突波的耐久性的同時,緩和電流集中(參照圖6以及圖9中的“實施例”)。When the end surface of the low-concentration first conductivity
圖9的實施例展示了圖6所示形態的雷電突波容量相對於後述的比較例一的比率。在圖7所示的比較例一的形態中,在第二導電型半導體層13中,不存在第二導電型的摻雜濃度為第一導電型的摻雜濃度的1000倍的部位,在高濃度第一導電型半導體層11中,起始於低濃度第一導電型半導體層12端面,直至達到低濃度第一導電型半導體層12的第一導電型摻雜濃度的1000倍的厚度方向上距離D1為4μm。雖然圖9中用比較例一來表示這種情況下的雷電突波耐久性,但是其值僅為作為實施例表示的值的1/12左右。在圖8所示的比較例二的形態中,距第二導電型半導體層13的一側的面(上端面) 30μm以內的距離處的摻雜濃度未達到大於等於1×1017
cm-3
,在第二導電型半導體層13中,在第二導電型摻雜濃度達到第一導電型摻雜濃度的1000倍的部位處的距離第一導電型半導體層的端面的厚度方向上的距離D2為10μm。雖然在圖9中作為比較例二展示了此情況下的雷電突波耐久性相對於比較例一的比例,但是其值僅為作為實施例表示的值的2/3左右。The example of FIG. 9 shows the ratio of the lightning surge capacity of the form shown in FIG. 6 to the comparative example 1 described later. In the form of Comparative Example 1 shown in FIG. 7, in the second conductivity
通過在第二導電型半導體層13、以及低濃度第一導電型半導體層12與第二導電型半導體層13之間的介面上設置重金屬,可以降低內建電勢。這樣,就可以將反向恢復時間trr加快至數μs的程度。另外,使用鉑作為重金屬,也特別有益於加快trr。如圖10所示,在使用鉑作為重金屬的情況下,還能夠得到降低低電流側的VF (順向電壓)的效果。例如用於空調的電流使用1A~2A,對於在空調等中使用的半導體裝置來說,降低低電流側的VF (順向電壓)是非常有益的。By disposing heavy metals on the second conductivity
第二實施例Second embodiment
下面,對本發明的第二實施例進行說明。Next, the second embodiment of the present invention will be described.
在第一實施例中,設置有檯面槽65,但在本實施例中,設置有凹部66來代替檯面槽65 (參照圖11 )。除此之外,與第一實施例相同,在第二實施例中也可以採用在第一實施例中採用的所有結構。In the first embodiment, a
本實施例的半導體裝置例如圖11所示,包括:高濃度第一導電型半導體層11;設置在高濃度第一導電型半導體層11上,且由第一導電型的摻雜濃度比高濃度第一導電型半導體層11低的第一導電型構成的低濃度第一導電型半導體層12;設置在低濃度第一導電型半導體層12上,且有第二導電型構成的第二導電型半導體層13;以及設置在第二導電型半導體層13的一部分上的玻璃膜50。The semiconductor device of this embodiment is shown in FIG. 11, for example, including: a high-concentration first conductivity
距離第二導電型半導體層13的一側的面30μm以內的距離處的摻雜濃度可以小於等於1×1019
cm-3
且大於等於1×1017
cm-3
。第二導電型半導體層13、以及低濃度第一導電型半導體層12與第二導電型半導體層13之間的介面可以含有重金屬。The doping concentration at a distance within 30 μm from the side surface of the second conductive
在本實施例中,也能夠得到與第一實施例同樣的效果,即,能夠緩和電流集中,且能夠獲得高雷電突波耐久性。Also in this embodiment, the same effect as the first embodiment can be obtained, that is, current concentration can be alleviated and high lightning surge durability can be obtained.
上述各實施例、變形例中的記載以及圖式中揭露的圖式僅為用於說明請求項中記載的發明的一例,因此請求項中記載的發明不受上述實施例或圖式中揭露的內容所限定。本申請最初的請求項中的記載僅僅是一個示例,可以根據說明書、圖式等的記載對請求項中的記載進行適宜的變更。The descriptions in the above-mentioned embodiments and modifications and the drawings disclosed in the drawings are only examples for explaining the inventions described in the claims, and therefore, the inventions described in the claims are not disclosed in the above-mentioned embodiments or drawings. Content limited. The description in the initial claim of this application is only an example, and the description in the claim can be appropriately changed according to the description, drawings, etc.
11:高濃度第一導電型半導體層
12:低濃度第一導電型半導體層
13:第二導電型半導體層
16、18:摻雜表面層
17:抗蝕劑膜
19:氧化膜
20:第一電極
30:第二電極
50:玻璃膜
61、62:絕緣膜
65:檯面槽
66:凹部
70:開口部11: High concentration first conductivity type semiconductor layer
12: Low-concentration first conductivity type semiconductor layer
13: Second conductivity
圖1是可在本發明的第一實施例中使用的半導體裝置的截面圖。FIG. 1 is a cross-sectional view of a semiconductor device that can be used in the first embodiment of the present invention.
圖2A-圖2C是可在本發明的第一實施例中使用的半導體裝置的製造過程的截面圖。2A-2C are cross-sectional views of a manufacturing process of a semiconductor device that can be used in the first embodiment of the present invention.
圖3A和圖3B是緊接著圖2C中的製程後的半導體裝置的製造製程的過程截面圖。3A and 3B are process cross-sectional views of the manufacturing process of the semiconductor device immediately after the process in FIG. 2C.
圖4A和圖4B是緊接著圖3B中的製程後的半導體裝置的製造製程的過程截面圖。4A and 4B are process cross-sectional views of the manufacturing process of the semiconductor device immediately after the process in FIG. 3B.
圖5A和圖5B是緊接著圖4B中的製程後的半導體裝置的製造製程的過程截面圖。5A and 5B are process cross-sectional views of the manufacturing process of the semiconductor device immediately after the process in FIG. 4B.
圖6是展示本發明第一實施例的一個例子(實施例)中的深度方向上的摻雜濃度的曲線圖。FIG. 6 is a graph showing the doping concentration in the depth direction in an example (embodiment) of the first embodiment of the present invention.
圖7是展示比較例一中的深度方向上的摻雜濃度的曲線圖。FIG. 7 is a graph showing the doping concentration in the depth direction in Comparative Example 1. FIG.
圖8是展示比較例二中的深度方向上的摻雜濃度的曲線圖。FIG. 8 is a graph showing the doping concentration in the depth direction in Comparative Example 2. FIG.
圖9是展示比較例一、比較例二以及實施例中的會損壞半導體裝置的雷電突波施加電壓的比率的曲線圖。FIG. 9 is a graph showing the ratio of the lightning surge applied voltage that can damage the semiconductor device in Comparative Example 1, Comparative Example 2, and Examples.
圖10是展示在實施例涉及的半導體裝置中在注入鉑時與未注入鉑時的順向電壓VF與順向電流IF之間關係的曲線圖。10 is a graph showing the relationship between the forward voltage VF and the forward current IF when platinum is injected and when no platinum is injected in the semiconductor device according to the embodiment.
圖11是可在本發明的第二實施例中使用的半導體裝置的截面圖。FIG. 11 is a cross-sectional view of a semiconductor device that can be used in the second embodiment of the present invention.
11:高濃度第一導電型半導體層 11: High concentration first conductivity type semiconductor layer
12:低濃度第一導電型半導體層 12: Low-concentration first conductivity type semiconductor layer
13:第二導電型半導體層 13: Second conductivity type semiconductor layer
20:第一電極 20: first electrode
30:第二電極 30: second electrode
50:玻璃膜 50: glass film
61、62:絕緣膜 61, 62: Insulating film
65:檯面槽 65: Countertop slot
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020025740A JP7505892B2 (en) | 2020-02-19 | 2020-02-19 | Semiconductor device and method for manufacturing the same |
JP2020-025740 | 2020-02-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202135170A true TW202135170A (en) | 2021-09-16 |
TWI806005B TWI806005B (en) | 2023-06-21 |
Family
ID=77275670
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW110105553A TWI806005B (en) | 2020-02-19 | 2021-02-18 | Semiconductor device and method for manufacturing semiconductor device |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP7505892B2 (en) |
CN (1) | CN113284938B (en) |
TW (1) | TWI806005B (en) |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4965181A (en) * | 1972-10-25 | 1974-06-24 | ||
JPS6011467B2 (en) * | 1976-08-11 | 1985-03-26 | 株式会社日立製作所 | Glass-coated semiconductor device and its manufacturing method |
JPH09199733A (en) * | 1996-01-16 | 1997-07-31 | Hitachi Ltd | Semiconductor device and its manufacture |
JP2002373897A (en) * | 2001-06-14 | 2002-12-26 | Nippon Inter Electronics Corp | Method for fabricating diode |
JP2004006664A (en) * | 2002-04-10 | 2004-01-08 | Sanken Electric Co Ltd | Manufacturing method of semiconductor device |
KR100898655B1 (en) * | 2004-08-27 | 2009-05-22 | 파나소닉 주식회사 | Semiconductor device for surge protection |
JP4965181B2 (en) | 2006-07-31 | 2012-07-04 | 有限会社鈴木軽合金 | Molding device for spherical mold |
-
2020
- 2020-02-19 JP JP2020025740A patent/JP7505892B2/en active Active
-
2021
- 2021-01-28 CN CN202110117781.2A patent/CN113284938B/en active Active
- 2021-02-18 TW TW110105553A patent/TWI806005B/en active
Also Published As
Publication number | Publication date |
---|---|
JP7505892B2 (en) | 2024-06-25 |
CN113284938A (en) | 2021-08-20 |
CN113284938B (en) | 2024-09-06 |
JP2021132082A (en) | 2021-09-09 |
TWI806005B (en) | 2023-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9905666B2 (en) | Trench schottky rectifier device and method for manufacturing the same | |
CN107331616A (en) | Trench junction barrier Schottky diode and manufacturing method thereof | |
US6576973B2 (en) | Schottky diode on a silicon carbide substrate | |
CN108346688B (en) | SiC trench junction barrier Schottky diode with CSL transport layer and manufacturing method thereof | |
JP2000516767A (en) | SiC semiconductor device including pn junction having voltage absorbing edge | |
JP2004515080A5 (en) | ||
CN106876256B (en) | SiC double-groove UMOSFET device and preparation method thereof | |
JP4126359B2 (en) | Silicon carbide Schottky diode and manufacturing method thereof | |
CN210349845U (en) | Silicon carbide junction barrier Schottky diode | |
CN114122150A (en) | Preparation method and application of silicon carbide power diode | |
CN113140612A (en) | Terminal structure of silicon carbide power device and preparation method thereof | |
TWI806005B (en) | Semiconductor device and method for manufacturing semiconductor device | |
JP2005135972A (en) | Manufacturing method of semiconductor device | |
CN114497181B (en) | In-vivo composite terminal structure of power device and preparation method | |
CN106876471B (en) | Dual trench UMOSFET device | |
CN111799336B (en) | SiC MPS diode device and preparation method thereof | |
CN111799338B (en) | Groove type SiC JBS diode device and preparation method thereof | |
CN211828777U (en) | Silicon carbide power diode | |
CN114171607A (en) | Silicon carbide junction barrier schottky diode | |
CN109449213B (en) | Preparation method of Schottky junction diamond diode device with field plate | |
JP3067034B2 (en) | Schottky barrier semiconductor device | |
JP2005079233A (en) | Schottky diode and its manufacturing method | |
CN210956680U (en) | Terminal structure of silicon carbide power device | |
JP7528963B2 (en) | Semiconductor Device | |
CN118367011A (en) | Fast recovery diode and preparation method thereof |