TW202132981A - Electrical device and communication method - Google Patents

Abstract

An electrical device is coupled to another electrical device via a communication interface. The electrical device executes a writing process to the another electrical device via the communication interface. If a writing failure occurs, the electrical device establishes a related address list associated with the writing process, verifies multiple related addresses in the related address list, and executes the writing process again.

Description

Electronic device and communication method

The content of the embodiment described in this case relates to a communication technology, particularly an electronic device and a communication method.

With the development of communication technology, signals can be transmitted between two electronic devices through various communication interfaces. However, due to some factors, interference may occur in the signal transmission process. These interferences will affect the correctness of the signal. If the transmitted signal or received signal is incorrect, the system will operate abnormally.

Some embodiments of this case are related to an electronic device. The electronic device is coupled to another electronic device through a communication interface. The electronic device executes a writing process to another electronic device through the communication interface. If a write failure occurs, the electronic device creates a related address list related to the write process, verifies the plural related addresses in the related address list, and executes the write process again.

Some implementations of this case are related to a communication method. The communication method includes: using an electronic device to execute a writing process to another electronic device through a communication interface; if a writing failure occurs, creating a related address list related to the writing process by the electronic device; and The electronic device verifies a plurality of related addresses in the related address list, and re-executes the writing process.

In summary, the electronic device and communication method of this case can be verified by software, and the relevant addresses in the relevant address list are verified first. Compared with verifying all addresses, the electronic device and communication method in this case can shorten the verification time without changing the hardware architecture.

100: Communication system

700: Communication method

E1: Electronic device

E2: Electronic device

IF: Communication interface

CS: Select signal

SCLK: clock signal

SI: Input data

SO: output data

CM1: Command

CM2: Command

AD1: address

AD2: address

DATA1: data

DATA2: data

S410: Operation

S420: Operation

S510: Operation

S520: Operation

S530: Operation

S540: Operation

S550: Operation

S610: Operation

S620: Operation

S630: Operation

S640: Operation

S710: Operation

S720: Operation

S730: Operation

In order to make the above and other purposes, features, advantages and embodiments of this case more obvious and understandable, the description of the attached drawings is as follows:

Figure 1 is a schematic diagram of a communication system according to some embodiments of the present case;

FIG. 2 is a schematic diagram of a reading procedure according to some embodiments of the present case;

FIG. 3 is a schematic diagram of a writing procedure according to some embodiments of the present case;

Figure 4 is a flow chart of the verification and reading procedure shown in some embodiments of the present case;

Figure 5 is a flow chart of the verification write program according to some embodiments of the present case;

Figure 6 is a flow chart of an inversion procedure according to some embodiments of the present case; and

Figure 7 is a flowchart of a communication method according to some embodiments of the present case.

The term "coupled" used in this article can also refer to "electrical coupling", and the term "connected" can also refer to "electrical connection". "Coupling" and "connection" can also refer to two or more components cooperating or interacting with each other.

Refer to Figure 1. Fig. 1 is a schematic diagram of a communication system 100 according to some embodiments of the present case. Taking the example of FIG. 1 as an example, the communication system 100 includes an electronic device E1 and an electronic device E2.

In some embodiments, the electronic device E1 is a master device, and the electronic device E2 is a slave device. The electronic device E1 can be coupled to the electronic device E2 through the communication interface IF to communicate with the electronic device E2. Accordingly, the electronic device E1 can communicate with the electronic device E2 through the communication interface IF. For example, the electronic device E1 can perform a reading process or a writing process on the electronic device E2 through the communication interface IF. In other words, the electronic device E1 can write data into the electronic device E2 or read the data in the electronic device E2 through the communication interface IF. In some embodiments, there may be a plurality of electronic devices E2, and the electronic device E1 is coupled to the electronic devices E2 through the communication interface IF.

In some embodiments, the communication interface IF can be implemented by a serial peripheral interface (SPI), and the electronic device E1 and the electronic device E2 can be implemented by a serial peripheral interface device. Due to order Serial peripheral interface technology only occupies four signal lines, so the use of serial peripheral interface technology can save chip area.

FIG. 2 is a schematic diagram of a reading procedure according to some embodiments of the present application. As mentioned earlier, the serial peripheral interface chip only occupies four signal lines. Accordingly, the electronic device E1 (or the electronic device E2) may include four signal pins. One is the selection pin, which is used to receive the selection signal CS. One is the clock pin for receiving the clock signal SCLK. One is a data input pin for receiving input data SI. One is the data output pin, which is used to output the output data SO.

In some embodiments, when the electronic device E1 is coupled to a plurality of electronic devices E2, the selection signal CS can be used to determine which electronic device E2 is selected and the electronic device E1 can perform signal transmission with the selected electronic device E2. Taking the example of Figure 2, if Figure 2 shows the signals of the four signal pins of one of the electronic devices E2, when the selection signal CS has a low logic level, it means that the electronic device E2 is selected . The input data SI is the data received by the electronic device E2. The output data SO is the data output by the electronic device E2. The clock signal SCLK is used to control data reception/transmission. For example, the input data SI received by the electronic device E2 can be received at the rising edge or falling edge of the clock signal SCLK, or the output data SO output by the electronic device E2 can be received at The rising edge or falling edge of the clock signal SCLK is output.

Taking the example of FIG. 2 as an example, if the electronic device E1 executes the reading process, the electronic device E1 will output the input signal SI to the electronic device E2. The input signal SI includes the command CM1 (0x01) and the address AD1. Accordingly, electronic equipment Setting E2 can output the data DATA1 corresponding to the address AD1 to the electronic device E1 according to the command CM1 and the address AD1, so as to complete the reading procedure executed by the electronic device E1.

Refer to Figure 3. FIG. 3 is a schematic diagram of a writing process according to some embodiments of the present application.

Taking the example of FIG. 3 as an example, if the electronic device E1 executes the writing process, the electronic device E1 will output the input signal SI to the electronic device E2. The input signal SI includes command CM2 (0x02), address AD2 and data DATA2. Accordingly, according to the command CM2, the data DATA2 from the electronic device E1 will be written into the address AD2 of the electronic device E2 to complete the writing process executed by the electronic device E1.

However, during the signal transmission process, the signal may change due to interference. In this case, the communication system 100 may operate abnormally.

Refer to Figure 2 and Figure 4 together. Figure 4 is a flow chart of the verification and reading procedure shown in some embodiments of the present case. During the reading process, if the potential of the command CM1, address AD1 or data DATA1 changes, it may cause errors in the data read. In response to this, the communication system 100 of this case can use software to verify the reading program.

In operation S410, the electronic device E1 executes a reading procedure on the electronic device E2 to read the written data in the address AD1 of the electronic device E2 at two time points, respectively.

In operation S420, it is determined whether the two read data respectively read at the first time point and the second time point are the same to determine the reading procedure whether succeed. For example, if the read data at the two time points are the same, it means that the read process is successful. If the reading data at the two time points are not the same, it means that the reading procedure has failed. In the case that the reading procedure fails, operation S410 will be entered again to re-execute the reading procedure. In other words, the electronic device E1 will read the written data of the address AD1 of the electronic device E2 again at the next two time points. Then, enter operation S420 again.

Refer to Figure 3 and Figure 5 together. Figure 5 is a flow chart of the verification write procedure according to some embodiments of the present case. During the writing and fetching process, if the potential of the command CM2 or the data DATA2 changes, it may cause the written data error. If the potential of the address AD2 changes, it may cause data to be written to the wrong address. In response to this, the communication system 100 of this case can verify the writing program by means of software.

In operation S510, the electronic device E1 transmits the command CM2, the address AD2, and the preset data DATA2 to be written to the electronic device E2. Based on the command CM2, the preset data DATA2 to be written is written into the address AD2 of the electronic device E2.

In operation S520, the electronic device E1 determines whether the writing is successful. For example, the electronic device E1 reads the written data in the address AD2, and determines whether the written data is the same as the preset data DATA2 to be written. If the written data in the address AD2 is the same as the preset data DATA2 to be written, it is judged that the writing is successful. In this case, the writing procedure ends. If the written data in the address AD2 is different from the preset data DATA2 to be written, it is judged that the writing has failed. In this case, proceed to operation S530.

In operation S530, the electronic device E1 further determines whether the written data in the address AD2 is the same as the original data in the address AD2. If the written data in the address AD2 is different from the original data in the address AD2, operation S510 is entered again. The electronic device E1 rewrites the data DATA2 into the address AD2 of the electronic device E2 according to the command CM2. In other words, when it is judged that the written data in the address AD2 is different from the original data in the address AD2, the rewriting is directly performed. If the written data is the same as the original data at the address AD2, enter operation S540.

In operation S540, based on the address AD2, a list of related addresses related to the writing process is established. Specifically, if the address AD2 of the write program has N (for example: 8) bits, the N (for example: 8) bits will be inverted respectively to generate the N of the electronic device E2. (For example: 8) related addresses. The N (for example: 8) related addresses are used to create a list of related addresses for the writing process.

Refer to Figure 6. Figure 6 is a flow chart of an inversion procedure according to some embodiments of the present case. In operation S610, n corresponds to the nth bit of the address AD2 and n is set to 1. In operation S620, the logic value of the nth bit is inverted (for example, logic value 1 is converted to logic value 0, and logic value 0 is converted to logic value 1). In operation S630, n+1 is set as a new n. In operation S640, it is determined whether the new n (original n+1) is greater than N. If yes, the inversion procedure ends. If not, return to operation S620 to perform an inversion procedure on the nth bit according to the updated n, and then analyze at least one relevant address.

For example. If the address AD2 is 0 0 0 0 1 0 0 1, the first bit is inverted and the first related address is 0 0 0 0 1 0 0 0, and the second After inverting one bit, the second related address is 0 0 0 0 1 0 1 1. Inverting the third bit, the third related address is 0 0 0 0 1 1 0 1 , After inverting the 4th bit, the fourth relevant address is generated as 0 0 0 0 0 0 0 1. Inverting the 5th bit, the fifth relevant address is generated as 0 0 0 1 1 0 0 1. Invert the 6th bit to generate the sixth relevant address as 0 0 1 0 1 0 0 1. Invert the 7th bit to generate the seventh relevant address as 0 1 0 0 1 0 0 1. Invert the eighth bit to generate the eighth related address 1 0 0 0 1 0 0 1. Equivalently speaking, one of the bits in the related address generated above is different from the corresponding bit of the address AD2, and the other bits in the related address are the same as other corresponding bits of the address AD2. The above 8 related addresses can be used to build a list of related addresses. In other words, the related address list contains the above 8 related addresses.

Refer to Figure 5 again. In operation S550, the electronic device E1 reads the related addresses in the related address list to determine whether the N related addresses have data abnormalities. If one of the related addresses is judged to have a data abnormality, the written data of the related address is restored to the original data of the related address, and operation S510 is entered again. In some implementations, the original data of the relevant address or all addresses will be backed up, and the corresponding content of the address AD2 in the backup will be updated to the data DATA2 when it is determined that the writing is successful in operation S520.

The electronic device E1 rewrites the data DATA2 into the address AD2 of the electronic device E2 according to the command CM2. That is to say, after judging that the write failure has occurred and the related address list is established, the electronic device E1 will verify the related address These (for example: 8) related addresses in the list, and re-execute the writing procedure.

In some related technologies, additional verification circuits are configured to perform verification. However, most protocols or devices do not support additional verification circuits. In addition, the configuration of an additional verification circuit will cause the problem of increased cost and larger circuit area. Compared with these related technologies, the communication system 100 in this case uses software to verify the correctness of the signal. In other words, the communication system 100 in this case does not need to be equipped with additional verification circuits.

Furthermore, the electronic device E1 in this case first checks the relevant addresses in the relevant address list instead of checking all addresses. In some embodiments, since the probability of signal error is very low, most of the errors can be confirmed after checking the relevant addresses in the relevant address list (for example, the above-mentioned 8 relevant addresses). Accordingly, the communication system 100 of this case can confirm write errors without having to verify all addresses, thereby shortening the verification time.

Refer to Figure 7. FIG. 7 is a flowchart of a communication method 700 according to some embodiments of this case. The communication method 700 includes operations S710, S720, and S730. In some embodiments, the communication method 700 is applied to the communication system 100 in FIG. 1, but this case is not limited to this. For ease of understanding, the communication method 700 will be discussed in conjunction with Figure 1.

In operation S710, the electronic device E1 performs a writing process on the electronic device E2 through the communication interface IF. In some embodiments, the communication interface IF is implemented by a serial peripheral interface.

In operation S720, if a writing failure occurs, the electronic device E1 is used to create a related address list related to the writing process. In some embodiments In the process, the N (for example: 8) bits of the address AD2 written in the program are respectively inverted to generate N (for example: 8) related addresses, and then according to the N (for example: 8) A) related addresses to establish a list of related addresses.

In operation S730, the electronic device E1 verifies the N related addresses in the related address list, and re-executes the writing process.

In summary, the electronic device and communication method of this case can be verified by software, and the relevant addresses in the relevant address list are verified first. Compared with verifying all addresses, the electronic device and communication method in this case can shorten the verification time without changing the hardware architecture.

Various functional elements and blocks have been disclosed here. For those skilled in the art, functional blocks can be implemented by circuits (whether dedicated circuits or general-purpose circuits operated under the control of one or more processors and coded instructions), which generally include corresponding The functions and operations described here are transistors or other circuit elements that control the operation of an electrical circuit. As will be further understood, in general, the specific structure and interconnection of circuit elements can be determined by a compiler (compiler), such as a register transfer language (RTL) compiler. The register transfer language compiler operates on scripts that are quite similar to assembly language codes, and compiles the scripts into a form used for layout or making final circuits. Indeed, the register transfer language is known for its role and use in facilitating the design of electronic and digital systems.

Although this case has been disclosed as above by way of implementation, it is not intended to limit the case. Anyone with ordinary knowledge in the field will not deviate from the spirit of the case. Within the scope and scope, various changes and modifications can be made. Therefore, the scope of protection in this case shall be subject to the scope of the attached patent application.

100: Communication system

E1: Electronic device

E2: Electronic device

IF: Communication interface

Claims (10)

An electronic device is coupled to another electronic device through a communication interface, wherein the electronic device executes a writing process to the other electronic device through the communication interface, wherein if a writing failure occurs, the electronic device establishes a correlation with A related address list of the writing procedure is checked, the plural related addresses in the related address list are verified, and the writing procedure is executed again. The electronic device according to claim 1, wherein if the bit address corresponding to the write failure has N bits, the number of the related addresses is N, where N is a positive integer. The electronic device according to claim 1, wherein the electronic device writes a preset data into an address of the other electronic device during the writing process, reads a written data in the address, and Determine whether the written data is the same as the preset data to determine whether the write failure occurs. The electronic device according to claim 3, wherein if the written data is different from the preset data, it is determined that the write failure has occurred, and the electronic device determines whether the written data is the same as an original address of the address. material. The electronic device according to claim 4, wherein if the written data is the same as the original data, each of the N bits of the address performs an inversion procedure to generate the N of the other electronic device. Related addresses, where the related address list is established based on the N related addresses, where N Is a positive integer. The electronic device according to claim 5, wherein the electronic device reads the N related addresses to determine whether a data abnormality occurs in one of the N related addresses, and if the N related addresses The data abnormality occurs in one of the ones, the written data corresponding to the one of them is restored, and the electronic device rewrites the preset data into the address of the other electronic device. The electronic device according to claim 4, wherein if the written data is different from the original data, the electronic device rewrites the preset data to the address of the another electronic device. The electronic device according to claim 1, wherein the electronic device executes a reading procedure to the other electronic device through the communication interface, wherein in the reading procedure, the electronic device is at a first time point and a At the second time point, read a written data of one address of the other electronic device, and determine whether the two read data respectively read at the first time point and the second time point are the same, to Determine whether the reading procedure is successful. The electronic device according to claim 1, wherein the communication interface is a serial peripheral interface (Serial Peripheral Interface, SPI). A communication method including: A writing process is executed by an electronic device to another electronic device through a communication interface; If a writing failure occurs, use the electronic device to create a related address list related to the writing process; and The electronic device verifies a plurality of related addresses in the related address list, and re-executes the writing process.

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