TWI762900B - Electrical device and communication method - Google Patents

Abstract

An electrical device is coupled to another electrical device via a communication interface. The electrical device executes a writing process to the another electrical device via the communication interface. If a writing failure occurs, the electrical device establishes a related address list associated with the writing process, verifies multiple related addresses in the related address list, and executes the writing process again.

Description

Electronic device and communication method

The content of the embodiments described in this case relates to a communication technology, especially an electronic device and a communication method.

With the development of communication technology, signals can be transmitted between two electronic devices through various communication interfaces. However, due to some factors, the process of signal transmission may be disturbed. These disturbances can affect the correctness of the signal. If the transmitted signal or the received signal is incorrect, the system will function abnormally.

Some embodiments of the present case relate to an electronic device. The electronic device is coupled to another electronic device through a communication interface. The electronic device executes a writing program to another electronic device through the communication interface. If a write failure occurs, the electronic device creates a related address list related to the write process, verifies the plural related addresses in the related address list, and re-executes the write process.

Some embodiments of the present case relate to a method of communication. The communication method includes: executing a writing procedure by an electronic device to another electronic device through a communication interface; if a writing failure occurs, establishing a relevant address list related to the writing procedure by the electronic device; and The plurality of related addresses in the related address list are checked by the electronic device, and the writing procedure is re-executed.

To sum up, the electronic device and the communication method in this case can be verified by software, and the related addresses in the related address list can be checked first. Compared with verifying all addresses, the electronic device and communication method of the present application can shorten the verification time without changing the hardware structure.

100: Communication System

700: Communication method

E1: Electronic device

E2: Electronic Devices

IF: communication interface

CS: select signal

SCLK: clock signal

SI: input data

SO: output data

CM1: Command

CM2: Command

AD1: address

AD2: address

DATA1: data

DATA2: data

S410: Operation

S420: Operation

S510: Operation

S520: Operation

S530: Operation

S540: Operation

S550: Operation

S610: Operation

S620: Operation

S630: Operation

S640: Operation

S710: Operation

S720: Operation

S730: Operation

In order to make the above and other objects, features, advantages and embodiments of the present case more clearly understood, the accompanying drawings are described as follows:

FIG. 1 is a schematic diagram of a communication system according to some embodiments of the present application;

FIG. 2 is a schematic diagram of a reading process according to some embodiments of the present application;

FIG. 3 is a schematic diagram of a writing process according to some embodiments of the present application;

FIG. 4 is a flowchart of a verification reading procedure according to some embodiments of the present application;

FIG. 5 is a flowchart of a verification writing procedure according to some embodiments of the present application;

FIG. 6 is a flowchart of an inversion process according to some embodiments of the present application; and

FIG. 7 is a flowchart of a communication method according to some embodiments of the present application.

As used herein, the term "coupled" may also refer to "electrically coupled," and the term "connected" may also refer to "electrically connected." "Coupled" and "connected" may also refer to two or more elements cooperating or interacting with each other.

Refer to Figure 1. FIG. 1 is a schematic diagram of a communication system 100 according to some embodiments of the present application. In the example of FIG. 1, the communication system 100 includes an electronic device E1 and an electronic device E2.

In some embodiments, electronic device E1 is a master device and electronic device E2 is a slave device. The electronic device E1 can be coupled to the electronic device E2 through the communication interface IF to communicate with the electronic device E2. Accordingly, the electronic device E1 can communicate with the electronic device E2 through the communication interface IF. For example, the electronic device E1 can execute a reading process or a writing process on the electronic device E2 through the communication interface IF. That is, the electronic device E1 can write data into the electronic device E2 or read data in the electronic device E2 through the communication interface IF. In some embodiments, the electronic devices E2 may be plural, and the electronic devices E1 are coupled to the electronic devices E2 through the communication interface IF.

In some embodiments, the communication interface IF can be implemented by a serial peripheral interface (SPI), and the electronic device E1 and the electronic device E2 can be implemented by a serial peripheral interface device. due to the order The column peripheral interface technology only occupies four signal lines, so the use of the serial peripheral interface technology can save the chip area.

FIG. 2 is a schematic diagram of a reading process according to some embodiments of the present application. As mentioned earlier, the serial peripheral interface chip occupies only four signal lines. Accordingly, the electronic device E1 (or the electronic device E2 ) may include four signal pins. One is a selection pin for receiving the selection signal CS. One is a clock pin for receiving the clock signal SCLK. One is a data input pin for receiving input data SI. One is the data output pin, which is used to output the output data SO.

In some embodiments, when the electronic device E1 is coupled to a plurality of electronic devices E2, the selection signal CS can be used to determine which electronic device E2 is selected and the electronic device E1 can perform signal transmission with the selected electronic device E2. Taking the example of Figure 2 as an example, if Figure 2 shows the signals of the four signal pins of one of the electronic devices E2, when the selection signal CS has a low logic level, it means that the electronic device E2 is selected . The input data SI is the data received by this electronic device E2. The output data SO is the data output by the electronic device E2. The clock signal SCLK is used to control the reception/transmission of data. For example, the input data SI received by the electronic device E2 may be received at the rising edge or the falling edge of the clock signal SCLK, or the output data SO output by the electronic device E2 may be at The rising edge or falling edge of the clock signal SCLK is output.

Taking the example of FIG. 2 as an example, if the electronic device E1 executes the reading procedure, the electronic device E1 will output the input signal SI to the electronic device E2. The input signal SI includes the command CM1 (0x01) and the address AD1. Accordingly, electronic equipment The setting E2 can output the data DATA1 corresponding to the address AD1 to the electronic device E1 according to the command CM1 and the address AD1, so as to complete the reading procedure executed by the electronic device E1.

Refer to Figure 3. FIG. 3 is a schematic diagram of a writing process according to some embodiments of the present application.

Taking the example of FIG. 3 as an example, if the electronic device E1 executes the writing procedure, the electronic device E1 will output the input signal SI to the electronic device E2. The input signal SI includes the command CM2 (0x02), the address AD2 and the data DATA2. Accordingly, according to the command CM2, the data DATA2 from the electronic device E1 will be written into the address AD2 of the electronic device E2, so as to complete the writing procedure executed by the electronic device E1.

However, during the signal transmission process, the signal may be changed due to interference. In this case, the communication system 100 may operate abnormally.

Refer to Fig. 2 and Fig. 4 together. FIG. 4 is a flow chart of a verification reading procedure according to some embodiments of the present application. During the reading process, if the potential of the command CM1, the address AD1 or the data DATA1 changes, the read data may be wrong. In view of this, the communication system 100 of the present case can verify the reading program by means of software.

In operation S410, the electronic device E1 executes a reading procedure on the electronic device E2 to read the written data in the address AD1 of the electronic device E2 at two time points respectively.

In operation S420, it is determined whether the two read data respectively read at the first time point and the second time point are the same, so as to determine the read procedure whether succeed. For example, if the read data at the two time points are the same, the read procedure is successful. If the read data at the two time points are different, it means that the read procedure fails. In the case that the reading procedure fails, operation S410 will be entered again to re-execute the reading procedure. That is to say, the electronic device E1 will read the written data of the address AD1 of the electronic device E2 again at the next two time points respectively. Next, enter operation S420 again.

Refer to Fig. 3 and Fig. 5 together. FIG. 5 is a flowchart of a verification writing procedure according to some embodiments of the present application. In the process of writing and reading, if the electric potential of the command CM2 or the data DATA2 changes, the written data may be wrong. If the potential of the address AD2 changes, it may cause data to be written to the wrong address. In view of this, the communication system 100 of the present application can verify the writing program by means of software.

In operation S510, the electronic device E1 transmits the command CM2, the address AD2 and the preset data DATA2 to be written to the electronic device E2. Based on the command CM2, the predetermined data DATA2 to be written is written to the address AD2 of the electronic device E2.

In operation S520, the electronic device E1 determines whether the writing is successful. For example, the electronic device E1 reads the written data in the address AD2, and determines whether the written data is the same as the preset data DATA2 to be written. If the written data in the address AD2 is the same as the preset data DATA2 to be written, it is judged that the writing is successful. In this case, the writing procedure ends. If the written data in the address AD2 is different from the preset data DATA2 to be written, it is judged that the writing fails. In this case, it proceeds to operation S530.

In operation S530, the electronic device E1 further determines whether the written data in the address AD2 is the same as the original data in the address AD2. If the written data in the address AD2 is different from the original data in the address AD2, operation S510 is entered again. The electronic device E1 rewrites the data DATA2 to the address AD2 of the electronic device E2 according to the command CM2. That is to say, when it is judged that the written data in the address AD2 is different from the original data in the address AD2, rewriting is performed directly. If the written data is the same as the original data at the address AD2, go to operation S540.

In operation S540, based on the address AD2, a related address list related to the write program is established. Specifically, if the address AD2 of the writing procedure has N (eg: 8) bits, the N (eg: 8) bits will perform an inversion procedure respectively to generate the N (eg: 8) bits of the electronic device E2 (eg: 8) associated addresses. The N (eg: 8) related addresses are used to create the related address list of the write procedure.

Refer to Figure 6. FIG. 6 is a flowchart of an inversion process according to some embodiments of the present application. In operation S610, n corresponds to the n-th bit of the address AD2 and n is set to 1. In operation S620, the logical value of the n-th bit is inverted (eg, logical value 1 is converted to logical value 0, and logical value 0 is converted to logical value 1). In operation S630, n+1 is set as a new n. In operation S640, it is determined whether the new n (original n+1) is greater than N. If so, the inversion procedure ends. If not, go back to operation S620 to perform an inversion procedure on the n-th bit according to the updated n, and then analyze at least one relevant address.

For example. If the address AD2 is 0 0 0 0 1 0 0 1, invert the first bit to generate the first related address as 0 0 0 0 1 0 0 0, and the second After inverting the bits, the second relative address is 0 0 0 0 1 0 1 1, and the third bit is inverted to produce the third relative address 0 0 0 0 1 1 0 1 , invert the fourth bit to generate the fourth related address as 0 0 0 0 0 0 0 1, and invert the fifth bit to generate the fifth related address as 0 0 0 1 1 0 0 1, invert the sixth bit to generate the sixth related address as 0 0 1 0 1 0 0 1, invert the seventh bit to generate the seventh related address as 0 1 0 0 1 0 0 1, invert the eighth bit to generate the eighth related address 1 0 0 0 1 0 0 1. Equivalently speaking, one of the bits in the above-generated relevant address is different from the corresponding bit in the address AD2, and the other bits in the relevant address are the same as the other corresponding bits in the address AD2. The above 8 related addresses can be used to build a related address list. In other words, the relevant address list contains the above 8 relevant addresses.

Refer again to Figure 5. In operation S550, the electronic device E1 reads the relevant addresses in the relevant address list to determine whether data abnormality occurs in the N relevant addresses. If it is determined that a data abnormality occurs in one of the relevant addresses, the written data of the relevant address is returned to the original data of the relevant address, and operation S510 is entered again. In some implementations, the original data of the relevant address or all the addresses will be backed up. When operation S520 determines that the writing is successful, the corresponding content of the address AD2 in the backup will be updated to the data DATA2.

The electronic device E1 rewrites the data DATA2 to the address AD2 of the electronic device E2 according to the command CM2. That is to say, after judging that the write failure has occurred and the related address list is established, the electronic device E1 will verify the related address The (eg: 8) associated addresses in the list, and the write procedure is re-executed.

In some related technologies, additional verification circuits are configured for verification. However, most protocols or devices do not support additional verification circuits. In addition, there are problems in that the additional verification circuit is configured and the cost increases and the circuit area becomes large. Compared with these related technologies, the communication system 100 of the present application uses software to verify the correctness of the signal. That is to say, the communication system 100 of the present case does not need to configure an additional verification circuit.

Furthermore, the electronic device E1 of the present case preferentially checks the relevant addresses in the relevant address list instead of checking all the addresses. In some embodiments, since the probability of signal error is very low, most errors can be confirmed after checking the relevant addresses in the relevant address list (eg, the above 8 relevant addresses). Accordingly, the communication system 100 of the present application can confirm write errors without verifying all addresses, thereby shortening the verification time.

Refer to Figure 7. FIG. 7 is a flowchart of a communication method 700 according to some embodiments of the present application. The communication method 700 includes operations S710, S720 and S730. In some embodiments, the communication method 700 is applied to the communication system 100 of FIG. 1 , but the present application is not limited thereto. For ease of understanding, the communication method 700 will be discussed in conjunction with FIG. 1 .

In operation S710, the electronic device E1 executes the writing procedure to the electronic device E2 through the communication interface IF. In some embodiments, the communication interface IF is implemented by a serial peripheral interface.

In operation S720, if the writing failure occurs, the electronic device E1 creates a related address list related to the writing procedure. In some embodiments , perform an inversion procedure on the N (eg: 8) bits of the address AD2 written in the program, respectively, to generate N (eg: 8) related addresses, and then according to the N (eg: 8) bits ) related addresses to create a list of related addresses.

In operation S730, the N relevant addresses in the relevant address list are checked by the electronic device E1, and the writing procedure is re-executed.

To sum up, the electronic device and the communication method in this case can be verified by software, and the related addresses in the related address list can be checked first. Compared with verifying all addresses, the electronic device and communication method of the present application can shorten the verification time without changing the hardware structure.

Various functional elements and blocks have been disclosed herein. To those of ordinary skill in the art, functional blocks may be implemented by circuits (whether special purpose circuits or general purpose circuits operating under the control of one or more processors and coded instructions), which generally include means for corresponding A transistor or other circuit element that controls the operation of an electrical circuit with the functions and operations described herein. As will be further understood, in general the specific structure and interconnection of circuit elements can be determined by a compiler, such as a Register Transfer Language (RTL) compiler. Scratchpad-pass language compilers operate on scripts that are fairly similar to assembly language code, compiling the script into a form that is used to place or make final circuits. Indeed, the register transfer language is known for its role and use in facilitating the design process of electronic and digital systems.

Although the present case has been disclosed above in terms of implementation, it is not intended to limit the present case. Anyone with ordinary knowledge in the art will not depart from the spirit of the present case. Various alterations and modifications can be made within the scope of the patent application and the scope of protection in this case.

100: Communication System

E1: Electronic device

E2: Electronic Devices

IF: communication interface

Claims (10)

An electronic device is coupled to another electronic device through a communication interface, wherein the electronic device executes a writing procedure to the other electronic device through the communication interface, wherein if a writing failure occurs, the electronic device establishes a related A related address list of the write procedure, the plurality of related addresses in the related address list are checked, and the write procedure is re-executed. The electronic device of claim 1, wherein if an address corresponding to the write failure has N bits, the number of the relevant addresses is N, where N is a positive integer. The electronic device of claim 1, wherein the electronic device writes a preset data into an address of the other electronic device in the writing procedure, reads a written data in the address, and It is judged whether the written data is the same as the default data, so as to judge whether the write failure occurs. The electronic device of claim 3, wherein if the written data is different from the default data, it is determined that the write failure occurs, and the electronic device determines whether the written data is the same as an original of the address material. The electronic device of claim 4, wherein if the written data is the same as the original data, each of the N bits of the address separately performs an inversion process to generate N of the other electronic device related addresses, where the list of related addresses is built based on the N related addresses, where N is a positive integer. The electronic device according to claim 5, wherein the electronic device reads the N related addresses to determine whether a data abnormality occurs in one of the N related addresses, wherein if the N related addresses of which the data exception occurs, the written data corresponding to the one is restored, and the electronic device rewrites the default data to the address of the other electronic device. The electronic device of claim 4, wherein if the written data is different from the original data, the electronic device rewrites the default data to the address of the other electronic device. The electronic device of claim 1, wherein the electronic device executes a reading procedure to the other electronic device through the communication interface, wherein in the reading procedure, the electronic device is at a first time point and a A written data of an address of the other electronic device is read at a second time point, and it is determined whether the two read data respectively read at the first time point and the second time point are the same, so as to Determine whether the read procedure is successful. The electronic device of claim 1, wherein the communication interface is a Serial Peripheral Interface (SPI). A method of communication comprising: Execute a writing procedure to another electronic device through a communication interface by an electronic device; If a write failure occurs, establishing, by the electronic device, a related address list related to the write procedure; and The plurality of related addresses in the related address list are checked by the electronic device, and the writing procedure is re-executed.

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