CN113312294B

CN113312294B - Electronic device and communication method

Info

Publication number: CN113312294B
Application number: CN202010122202.9A
Authority: CN
Inventors: 王凤林; 邢征北; 崔涛; 陈兵
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2020-02-27
Filing date: 2020-02-27
Publication date: 2024-06-18
Anticipated expiration: 2040-02-27
Also published as: TWI762900B; CN113312294A; TW202132981A

Abstract

The present disclosure relates to electronic devices and communication methods. An electronic device is coupled with another electronic device through a communication interface. The electronic device executes a writing program to another electronic device through the communication interface. If a write failure occurs, the electronic device establishes a related address list related to the write program, verifies a plurality of related addresses in the related address list, and re-executes the write program.

Description

Electronic device and communication method

Technical Field

The embodiments described herein relate to a communication technology, and more particularly, to an electronic device and a communication method.

Background

With the development of communication technology, signal transmission can be performed between two electronic devices through various communication interfaces. However, the process of signal transmission may be disturbed based on a number of factors. These disturbances affect the signal accuracy. If the transmitted signal or the received signal is incorrect, the system will be abnormal.

Disclosure of Invention

Some embodiments of the present disclosure relate to an electronic device. The electronic device is coupled with another electronic device through a communication interface. The electronic device executes a writing program to another electronic device through the communication interface. If a write failure occurs, the electronic device establishes a related address list related to the write procedure, verifies a plurality of related addresses in the related address list, and re-executes the write procedure.

Some embodiments relate to a communication method. The communication method comprises the following steps: executing a writing program on another electronic device through a communication interface by the electronic device; if a write failure occurs, establishing a related address list related to the write program by the electronic device; and checking the plural related addresses in the related address list by the electronic device, and re-executing the writing procedure.

In summary, the electronic device and the communication method of the present disclosure can utilize a software method to check, and preferably check the related address in the related address list. Compared with checking all addresses, the electronic device and the communication method can shorten the checking time without changing the hardware architecture.

Drawings

The above and other objects, features, advantages and embodiments of the present invention will become more apparent by reading the following description of the accompanying drawings in which:

FIG. 1 is a schematic diagram of a communication system according to some embodiments of the present disclosure;

FIG. 2 is a schematic diagram of a read process according to some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of a write process according to some embodiments of the present disclosure;

FIG. 4 is a flow chart of a verification read process according to some embodiments of the present disclosure;

FIG. 5 is a flow chart of a verify write process according to some embodiments of the present disclosure;

FIG. 6 is a flow chart of an inversion process according to some embodiments of the present disclosure; and

FIG. 7 is a flow chart of a communication method according to some embodiments of the present disclosure.

Detailed Description

The term "coupled" as used herein may also refer to "electrically coupled" and the term "connected" may also refer to "electrically connected". "coupled" or "connected" may also mean that two or more elements cooperate or interact with each other.

Reference is made to fig. 1. Fig. 1 is a schematic diagram of a communication system 100 according to some embodiments of the present disclosure. For example, in fig. 1, the communication system 100 includes an electronic device E1 and an electronic device E2.

In some embodiments, the electronic device E1 is a master (master) apparatus and the electronic device E2 is a slave (slave) apparatus. The electronic device E1 is coupled to the electronic device E2 through the communication interface IF to be communicatively connected to the electronic device E2. Accordingly, the electronic device E1 can communicate with the electronic device E2 through the communication interface IF. For example, the electronic device E1 can execute a reading procedure or a writing procedure on the electronic device E2 through the communication interface IF. That is, the electronic device E1 can write data into the electronic device E2 or read data from the electronic device E2 through the communication interface IF. In some embodiments, the electronic devices E2 may be plural, and the electronic device E1 is coupled to the electronic devices E2 through the communication interface IF.

In some embodiments, the communication interface IF may be implemented by a serial peripheral interface (SERIAL PERIPHERAL INTERFACE, SPI), and the electronic device E1 and the electronic device E2 may be implemented by a serial peripheral interface apparatus. Because the serial peripheral interface technology only occupies four signal lines, the chip area can be saved by adopting the serial peripheral interface technology.

FIG. 2 is a schematic diagram of a read process according to some embodiments of the present disclosure. As mentioned above, the serial peripheral interface chip occupies only four signal lines. Accordingly, the electronic device E1 (or the electronic device E2) may include four signal pins (pins). One is a selection pin for receiving the selection signal CS. One is a clock pin for receiving the clock signal SCLK. One is a data input pin for receiving input data SI. One is a data output pin for outputting output data SO.

In some embodiments, when the electronic device E1 is coupled to a plurality of electronic devices E2, the selection signal CS can be used to determine which electronic device E2 is selected and the electronic device E1 can perform signal transmission with the selected electronic device E2. For example, in fig. 2, if the signals of four signal pins of one electronic device E2 are shown in fig. 2, when the selection signal CS has a low logic level, it represents that the electronic device E2 is selected. The input data SI is data received by the electronic device E2. The output data SO is data output by the electronic device E2. The clock signal SCLK is used to control the receiving/transmitting of data. For example, the input data SI received by the electronic device E2 may be received at the rising edge (RISING EDGE) or the falling edge (FALLING EDGE) of the clock signal SCLK, or the output data SO output by the electronic device E2 may be output at the rising edge or the falling edge of the clock signal SCLK.

For example, in fig. 2, if the electronic device E1 executes the reading procedure, the electronic device E1 outputs the input signal SI to the electronic device E2. The input signal SI includes the command CM1 (0 x 01) and the address AD1. Accordingly, the electronic device E2 outputs the DATA1 corresponding to the address AD1 to the electronic device E1 according to the command CM1 and the address AD1, so as to complete the reading procedure executed by the electronic device E1.

Reference is made to fig. 3. FIG. 3 is a schematic diagram of a writing process according to some embodiments of the present disclosure.

For example, in fig. 3, if the electronic device E1 performs the writing procedure, the electronic device E1 outputs the input signal SI to the electronic device E2. The input signal SI includes the command CM2 (0 x 02), the address AD2, and the DATA DATA2. Accordingly, the DATA2 from the electronic device E1 is written into the address AD2 of the electronic device E2 according to the command CM2, so as to complete the writing procedure executed by the electronic device E1.

However, during the signal transmission process, the signal may be changed due to interference. In this case, the communication system 100 may be abnormally operated.

Reference is made to fig. 2 and 4 together. FIG. 4 is a flow chart of a verification read process according to some embodiments of the present disclosure. During the reading process, if the potential of the command CM1, the address AD1 or the DATA1 changes, the read DATA may be erroneous. In this regard, the communication system 100 of the present disclosure may verify the read procedure by using software.

In operation S410, the electronic device E1 performs a reading procedure on the electronic device E2 to read the written data in the address AD1 of the electronic device E2 at two time points, respectively.

In operation S420, it is determined whether the two read data respectively read at the first time point and the second time point are the same, so as to determine whether the read procedure is successful. For example, if the read data at the two time points are the same, it means that the read process is successful. If the read data at the two time points are different, the read program fails. In case of failure of the read program, operation S410 will be re-entered to re-execute the read program. That is, the electronic device E1 reads the written data of the address AD1 of the electronic device E2 again at two time points. Next, operation S420 is again entered.

Reference is made to fig. 3 and 5 together. FIG. 5 is a flow chart of a verify write process according to some embodiments of the present disclosure. During the write operation, if the potential of the command CM2 or the DATA2 changes, the written DATA may be erroneous. If the potential of the address AD2 changes, it may cause the wrong address to write data. In this regard, the communication system 100 of the present disclosure may verify the writing procedure by using software.

In operation S510, the electronic device E1 transmits the command CM2, the address AD2, and the DATA2 to be written in advance to the electronic device E2. Based on the instruction CM2, the DATA2 preset to be written is written to the address AD2 of the electronic device E2.

In operation S520, the electronic device E1 determines whether the writing is successful. For example, the electronic device E1 reads the written DATA in the address AD2, and determines whether the written DATA is identical to the DATA2 to be written. If the written DATA in the address AD2 is the same as the DATA DATA2 to be written, the writing is judged to be successful. In this case, the writing procedure ends. If the written DATA in the address AD2 is different from the DATA DATA2 to be written in advance, the writing failure is judged. In this case, operation S530 is entered.

In operation S530, the electronic device E1 further determines whether the written data in the address AD2 is identical to the original data of the address AD2. If the written data in the address AD2 is different from the original data of the address AD2, the operation S510 is performed again. The electronic device E1 rewrites the DATA2 into the address AD2 of the electronic device E2 according to the command CM 2. That is, when it is judged that the written data in the address AD2 is different from the original data of the address AD2, the overwriting is directly performed. If the written data is identical to the original data of the address AD2, operation S540 is performed.

In operation S540, a related address list related to the writing program is established based on the address AD 2. Specifically, if the address AD2 of the writing procedure has N (e.g., 8) bits, the N (e.g., 8) bits will be respectively subjected to the inverting procedure to generate N (e.g., 8) related addresses of the electronic device E2. The N (e.g., 8) associated addresses are used to build a list of associated addresses for the write process.

Refer to fig. 6. FIG. 6 is a flow chart of an inversion process according to some embodiments of the present disclosure. In operation S610, n corresponds to the nth bit of the address AD2 and is set to 1. In operation S620, the logical value of the nth bit is inverted (e.g., logical value 1 is changed to logical value 0, logical value 0 is changed to logical value 1). In operation S630, n+1 is set to a new n. In operation S640, it is determined whether the new N (original n+1) is greater than N. If so, the inversion process ends. If not, returning to operation S620, performing the inversion procedure on the n-th bit according to the updated n, and analyzing at least one related address.

For example. If the address AD2 is 00001001, the 1 st bit is inverted to generate a first correlation address of 00001000, the 2 nd bit is inverted to generate a second correlation address of 00001011, the 3 rd bit is inverted to generate a third correlation address of 00001101, the 4 th bit is inverted to generate a fourth correlation address of 00000001, the 5 th bit is inverted to generate a fifth correlation address of 00011001, the 6 th bit is inverted to generate a sixth correlation address of 00101001, the 7 th bit is inverted to generate a seventh correlation address of 01001001, and the 8 th bit is inverted to generate an eighth correlation address 10001001. Equivalently, one bit of the generated related address is different from the corresponding bit of the address AD2, and the other bits of the related address are the same as the other corresponding bits of the address AD 2. The 8 related addresses may be used to build a related address list. In other words, the related address list contains the above 8 related addresses.

Reference is again made to fig. 5. In operation S550, the electronic device E1 reads the related addresses in the related address list to determine whether the N related addresses are abnormal. If one of the related addresses is judged to be abnormal, the written data of the related address is recovered to the original data of the related address, and operation S510 is performed again. In some implementations, the original DATA of the relevant address or all addresses is backed up, and the corresponding contents of the address AD2 in the backup are updated to the DATA2 after the writing success is determined in operation S520.

The electronic device E1 rewrites the DATA2 into the address AD2 of the electronic device E2 according to the command CM 2. That is, after determining that the writing failure occurs and the related address list is established, the electronic device E1 verifies the (e.g. 8) related addresses in the related address list and re-executes the writing procedure.

In some related art, an additional verification circuit is configured to perform verification. However, most protocols or devices do not support additional verification circuitry. In addition, the additional verification circuit is configured, which increases the cost and increases the circuit area. In contrast to these related art, the communication system 100 uses software to verify the correctness of the signal. That is, the communication system 100 of the present invention does not require an additional calibration circuit.

Furthermore, the electronic device E1 preferably checks the related addresses in the related address list, rather than checking all the addresses. In some embodiments, since the probability of signal errors is low, most of the errors can be confirmed after verifying the related addresses (e.g., the 8 related addresses) in the related address list. Accordingly, the communication system 100 can confirm the write-in error without checking all addresses, thereby shortening the checking time.

Refer to fig. 7. Fig. 7 is a flow chart of a communication method 700 according to some embodiments of the present disclosure. The communication method 700 includes operations S710, S720, and S730. In some embodiments, the communication method 700 is applied to the communication system 100 of fig. 1, but the present application is not limited thereto. For ease of understanding, the communication method 700 will be discussed in conjunction with FIG. 1.

In operation S710, the electronic device E1 performs a writing procedure on the electronic device E2 through the communication interface IF. In some embodiments, the communication interface IF is implemented by a serial peripheral interface.

In operation S720, if the writing failure occurs, the electronic device E1 establishes a related address list related to the writing procedure. In some embodiments, N (e.g., 8) bits of address AD2 of the write program are respectively subjected to an inversion process to generate N (e.g., 8) associated addresses, and an associated address list is established according to the N (e.g., 8) associated addresses.

In operation S730, the electronic device E1 verifies the N related addresses in the related address list, and re-executes the writing procedure.

Various functional components and blocks have been disclosed herein. It will be appreciated by those of ordinary skill in the art that the functional blocks may be implemented by circuits, whether special purpose circuits or general purpose circuits operating under the control of one or more processors and code instructions, and typically include transistors or other circuit elements that control the operation of the electrical circuit in accordance with the functions and operations described herein. As will be further appreciated, the specific structure and interconnection of circuit elements in general may be determined by a compiler (compiler), such as a Register Transfer Language (RTL) compiler. The scratch pad language compiler operates on a script (script) that is quite similar to the assembly language code (assembly language code), compiling the script into a form for layout or making the final circuit. Indeed, register transfer languages are known for their role and purpose in facilitating the design of electronic and digital systems.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but may be modified or altered in various ways without departing from the spirit and scope of the invention.

[ Symbolic description ]

100 Communication system

700 Communication method

E1. Electronic device

E2:electronic device

IF-communication interface

CS: select Signal

SCLK, clock signal

SI input data

SO: output data

CM1 instruction

CM2 instruction

AD1: address

AD2 address

DATA1 DATA

DATA2 DATA

S410 operation

S420 operation

S510 operation

S520 operation

S530 operation

S540 operation

S550 operation

S610 operation

S620 operation

S630 operation

S640 operation

S710 operation

S720 operation

S730 operation

Claims

1. An electronic device coupled to another electronic device via a communication interface, wherein the electronic device executes a writing procedure to the other electronic device via the communication interface, wherein if a writing failure occurs, the electronic device establishes a related address list related to the writing procedure, verifies a plurality of related addresses in the related address list, and re-executes the writing procedure,

If an address corresponding to the write failure has N bits, the number of the related addresses is N, and each of the N bits of the address performs an inversion procedure to generate N related addresses of the other electronic device, wherein the related address list is established based on the N related addresses, where N is a positive integer.

2. The electronic device according to claim 1, wherein the electronic device writes a predetermined data to an address of the other electronic device by the writing program, reads a written data in the address, and determines whether the written data is identical to the predetermined data to determine whether the writing failure occurs.

3. The electronic device of claim 2, wherein if the written data is different from the predetermined data, determining that the write failure occurred, the electronic device determines whether the written data is identical to an original data of the address.

4. The electronic device of claim 3, wherein if the written data is identical to the original data, the electronic device reads the N related addresses to determine whether one of the N related addresses is abnormal in data, wherein if one of the N related addresses is abnormal in data, the written data corresponding to the one of the N related addresses is replied to, and the electronic device rewrites the preset data to the address of the other electronic device.

5. The electronic device of claim 3, wherein if the written data is different from the original data, the electronic device rewrites the preset data to the address of the other electronic device.

6. The electronic device according to claim 1, wherein the electronic device performs a reading procedure on the other electronic device through the communication interface, wherein in the reading procedure, the electronic device reads a written data of an address of the other electronic device at a first time point and a second time point respectively, and determines whether two read data respectively read at the first time point and the second time point are the same, so as to determine whether the reading procedure is successful.

7. The electronic device of claim 1, wherein the communication interface is a serial peripheral interface, SPI.

8. A method of communication, comprising:

Executing a writing program on another electronic device through a communication interface by the electronic device;

If a write failure occurs, establishing a related address list related to the write procedure by the electronic device; and

Checking a plurality of related addresses in the related address list by the electronic device, and re-executing the writing procedure,