CN113886158A - Automatic FPGA fault injection test system and method - Google Patents
Automatic FPGA fault injection test system and method Download PDFInfo
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Abstract
The invention relates to an automatic FPGA fault injection test system and method, the method includes reading the circuit file to be tested through the upper computer software; extracting input and output signals and other user design related information; automatically generating a user design control circuit according to the extracted information, and automatically generating a complete fault injection system file by interconnection and combination with a predefined fault injection control circuit; automatically executing the comprehensive implementation process of the lower computer hardware through the Tcl script; therefore, automatic generation of the fault injection system is realized. The invention reduces the development difficulty and the use threshold of the fault injection system, saves the complexity of manually building the fault injection system, ensures that designers can conveniently develop and build the fault injection system without deeply researching a complex FPGA design method and having a circuit design basis, improves the use range of the fault injection system, and can quickly and conveniently evaluate the reliability of the FPGA circuit.
Description
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to an automatic FPGA fault injection method.
Background
The SRAM type FPGA has the characteristics of repeated programming, high flexibility and the like, so that the SRAM type FPGA is more and more widely applied to aerospace electronic equipment. The SRAM memory cell used by the SRAM type FPGA provides great flexibility, and has the defect of being easily influenced by radiation effect, and the operation of the SRAM memory cell in a space radiation environment is easily interfered by single event upset effect, namely, cosmic high-energy particles are shot into a sensitive area of the SRAM cell, so that the logic of the memory cell in the FPGA can be overturned, thereby generating soft errors, and even damaging a hardware circuit in serious cases. Particularly, as the size of the FPGA transistor is continuously reduced, the influence of the radiation particles on the SRAM type FPGA is more and more increased. Therefore, evaluation of SEU sensitivity for SRAM type FPGA based systems is highly desirable. Therefore, the sensitivity of the circuit to the SEU can be mastered in the design stage, and the aims of guiding the design and judging the reliability of the designed circuit are fulfilled. In addition, as more and more fault-tolerant methods for relieving the SEU effect are proposed and applied to aerospace electronic equipment, such as error correction codes, triple modular redundancy and the like, it is inevitable to test and evaluate the SEU relief effect of the fault-tolerant designs.
However, not only the organization structure and configuration of the FPGA need to be mastered to build a complete set of fault injection system, but also the problem of low universality exists in the fault injection system designed and built for a certain user. Therefore, in order to make the reliability evaluation faster and more convenient, and to adapt to various designs, it is necessary to automate the fault injection evaluation process.
Disclosure of Invention
The technical problem solved by the invention is as follows: the defects of the prior art are overcome, an automatic FPGA fault injection testing system and method are provided, the development difficulty of a fault injection system is reduced, designers are assisted to quickly build the fault injection system, and the efficiency of evaluating the reliability of a circuit is improved.
The technical scheme for solving the technical problem is as follows: an automatic FPGA fault injection test system comprises an upper computer and a lower computer fault injection hardware system, wherein the lower computer fault injection hardware system comprises a user designed control circuit and a fault injection control circuit; wherein:
the user design control circuit comprises a circuit to be tested, a reference circuit, an excitation generating circuit and a result comparing circuit;
the reference circuit is a copy of the circuit to be tested and comprises m-bit input buses and n-bit output buses, the m-bit input buses are simultaneously connected to the excitation generating circuit, the n-bit output ports are simultaneously connected to the result comparing circuit, and m and n are both more than or equal to 1;
a stimulus generation circuit for receiving a stimulus start signal and then initializing, and after initialization, randomly generating m-bit data in each clock cycle, as a test stimulus, and simultaneously transmitting the m-bit data to the reference circuit and the circuit to be tested, 2mOne clock cycle traversing 2 of m-bit input busmA piece of data;
the result comparison circuit is used for comparing whether the data on the output bus after the reference circuit and the circuit to be tested are excited and driven are the same or not, if the data are different, the injection fault counting value is accumulated, otherwise, the injection fault counting value is kept unchanged, and then the injection fault counting value is sent to the serial port communication circuit; in an initial state or after receiving a fault injection test starting signal, resetting an injection fault count;
the fault injection control circuit comprises a process control circuit, a reconfiguration interface control circuit and a serial port communication circuit;
the process control circuit receives the fault injection command message through the serial port communication circuit, analyzes the fault injection command message to obtain a first address and a last address of a fault injection test, sends a fault injection test starting signal to the user design control circuit, traverses the test addresses from the first address, reads back frame data of a corresponding address through the reconfiguration interface control circuit for each test address, turns over the read back frame data according to bits to obtain reconfiguration frame data, writes the reconfiguration frame data into the corresponding address through the reconfiguration interface control circuit, turns over one data bit once for the frame data of each address, traverses all the data bits, writes the reconfiguration frame data once, and sends an excitation starting signal once to the user design control circuit.
Preferably, the lower computer fault injection hardware system is automatically realized by the following method:
s1, reading and analyzing a source code file of the circuit to be tested, and extracting the name and interface design information of a top module, wherein the interface design information comprises the name, type and bit width information of a user IO interface used by the top module;
s2, automatically constructing a user design control circuit according to the name and interface design information of the top module of the circuit to be tested;
s3, the automatically generated user design control circuit and the preset general fault injection control circuit are connected and combined to generate a hardware description file of the fault injection system, the process of synthesizing, laying out and wiring of the fault injection system is automatically completed through the Tcl script to obtain an executable file of the fault injection system, and the executable file of the fault injection system is loaded into the FPGA used by the circuit to be tested to complete the automatic construction of the lower computer fault injection hardware system.
Preferably, the step S2 of automatically constructing the user designed control circuit includes the specific steps of:
automatically instantiating a circuit to be tested and a reference circuit according to the name of the top module of the circuit to be tested;
analyzing an input port and an output port according to the name, type and bit width information of a user IO interface in the interface design information of the circuit to be tested;
generating an excitation generating circuit matched with the input port;
a result comparison circuit is generated that matches the output port.
Preferably, the automatic building process of the lower computer fault injection hardware system is realized in the upper computer.
Preferably, the excitation generating circuit generates pseudo random numbers as test excitations by means of a linear feedback shift register.
The other technical scheme of the invention is as follows: an automatic FPGA fault injection test method comprises the following steps:
s1, reading and analyzing a source code file of the circuit to be tested, and extracting the name and interface design information of a top module, wherein the interface design information comprises the name, type and bit width information of a user IO interface used by the top module;
s2, automatically constructing a user design control circuit according to the name and interface design information of the top module of the circuit to be tested;
s3, the automatically generated user design control circuit and the preset general fault injection control circuit are connected and combined to generate a hardware description file of the fault injection system, the process of synthesizing, laying out and wiring of the fault injection system is automatically completed through the Tcl script to obtain an executable file of the fault injection system, and the executable file of the fault injection system is loaded into the FPGA used by the circuit to be tested to complete the automatic construction of the lower computer fault injection hardware system.
S4, executing fault injection test: sending a fault injection command message to a lower computer fault injection hardware system by an upper computer, turning data frames in a preset address range of a circuit to be tested bit by bit, detecting output results of the circuit to be tested and a reference circuit under the same test excitation, judging whether the circuit to be tested has a fault, and counting the frequency of the fault;
and S5, after the preset addresses of the waiting circuit are all tested, uploading the counted failure times to an upper computer, and ending the process.
Preferably, the fault injection test procedure of the method is as follows: :
s4.1, the serial port communication circuit sends the fault injection command message received from the upper computer to the process control circuit;
s4.2, the process control circuit analyzes the fault injection command message, obtains the first address and the last address of the fault injection test from the fault injection command message, then sends a fault injection test starting signal to a user design control circuit, and the step S3 is entered;
s4.3, after the user design control circuit receives the fault injection test starting signal, the control result comparison circuit clears the injection fault count value;
s4.4, the process control circuit calculates the current test address and sends the read-back command and the test address to the reconfiguration interface control circuit;
s4.5, reconfiguring the interface control circuit, reading back frame data according to the test address after receiving the read-back command, and returning the frame data to the process control circuit;
s4.6, the process control circuit receives the read-back frame data fed back by the reconfiguration interface control circuit and then enters the step S7;
s4.7, performing bit flipping on the frame data, sending the frame data and the test address after the bit flipping to a reconfiguration interface control circuit through a reconfiguration command, and then sending an excitation starting signal to a user design control circuit;
s4.8, reconfiguring the interface control circuit, and reconfiguring the frame data after bit reversal into the circuit to be tested according to the test address after receiving the reconfiguration command;
s4.9, an excitation generating circuit receives an excitation starting signal and then initializes the excitation starting signal, and after initialization, m-bit data are randomly generated in each clock period and used as test excitation and sent to the parameterLighting circuit and circuit under test, 2mOne clock cycle traversing 2 of m-bit input busmData, wait for traversal 2mAfter the data, sending a data traversal end mark to a process control circuit;
s4.10, a result comparison circuit compares whether the data on the output bus after the reference circuit and the circuit to be tested are excited and driven are the same or not, if the data are different, the injected fault count is accumulated, otherwise, the injected fault count is kept unchanged, and then the injected fault count value is sent to the serial port communication circuit;
s4.11, the process control circuit enters the step S4.12 after receiving the data traversal end mark fed back by the excitation generating circuit;
s4.12, repeating the steps S4.7-S4.12 until all the bits of the same address frame data are turned over, re-executing the steps S4.4-S4.12 until the address traversal is finished, and sending a fault injection finishing identifier to the serial communication circuit;
and S4.13, the serial port communication circuit sends the fault count value to the upper computer.
Compared with the prior art, the invention has the beneficial effects that:
(1) according to the invention, through the analysis and research of the circuit to be tested, the information related to user design is extracted and used for constructing the user design control circuit, and the user design control circuit and the fault injection control circuit are interconnected to automatically generate a complete fault injection system, so that the complexity of manually constructing the fault injection system is saved, a large amount of time and energy of designers are saved, the application range of the fault injection system is enlarged, and the designers can quickly and conveniently evaluate the reliability of the FPGA circuit.
(2) The method and the device can adaptively and automatically build the fault injection system for various user circuits, simplify the process of building the fault injection system for each circuit and accelerate the large-scale circuit reliability evaluation when the reliability evaluation is carried out on a huge circuit set.
Drawings
FIG. 1 is a system architecture of an automated FPGA fault injection method according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating the implementation of an automated fault injection method according to an embodiment of the present invention;
fig. 3 is an execution flow of the fault injection system implemented by the embodiment of the present invention.
Detailed Description
The invention is further illustrated by the following examples.
The invention provides an automatic FPGA fault injection test system and a fault injection method.
An upper computer: reading and analyzing a circuit to be tested, extracting information, and automatically generating a lower computer hardware system; in the fault injection process, sending a command and an address to a lower computer;
the lower computer fault is injected into the hardware system: the method comprises the steps of designing a control circuit and a fault injection control circuit by a user, and controlling the readback, the turnover, the reconfiguration, the excitation generation and the result comparison of the fault injection.
The user design control circuit comprises a circuit to be tested, a reference circuit, an excitation generating circuit and a result comparing circuit;
the reference circuit is a copy of the circuit to be tested and comprises m-bit input buses and n-bit output buses, the m-bit input buses are simultaneously connected to the excitation generating circuit, the n-bit output ports are simultaneously connected to the result comparing circuit, and m and n are both more than or equal to 1;
a stimulus generation circuit for receiving a stimulus start signal and then initializing, and after initialization, randomly generating m-bit data in each clock cycle, as a test stimulus, and simultaneously transmitting the m-bit data to the reference circuit and the circuit to be tested, 2mOne clock cycle traversing 2 of m-bit input busmA piece of data; the excitation generating circuit generates pseudo random numbers as test excitation by adopting a linear feedback shift register mode.
The result comparison circuit is used for comparing whether the data on the output bus after the reference circuit and the circuit to be tested are excited and driven are the same or not, if the data are different, the injection fault counting value is accumulated, otherwise, the injection fault counting value is kept unchanged, and then the injection fault counting value is sent to the serial port communication circuit; in an initial state or after receiving a fault injection test starting signal, resetting an injection fault count;
the fault injection control circuit comprises a process control circuit, a reconfiguration interface control circuit and a serial port communication circuit;
the process control circuit receives the fault injection command message through the serial port communication circuit, analyzes the fault injection command message to obtain a first address and a last address of a fault injection test, sends a fault injection test starting signal to the user design control circuit, traverses the test addresses from the first address, reads back frame data of a corresponding address through the reconfiguration interface control circuit for each test address, turns over the read back frame data according to bits to obtain reconfiguration frame data, writes the reconfiguration frame data into the corresponding address through the reconfiguration interface control circuit, turns over one data bit once for the frame data of each address, traverses all the data bits, writes the reconfiguration frame data once, and sends an excitation starting signal once to the user design control circuit.
In addition to the fault injection command message, the upper computer can also send a read-back command and a reconfiguration command to the lower computer fault injection hardware system, wherein the read-back command is used for reading back data in the specified frame address; the reconfiguration command reconfigures the data into the specified frame address. The address refers to an address of a configuration frame in the FPGA, and is composed of 26 bits and used for positioning a row position and a column position configured in the FPGA.
In order to realize automatic testing, the lower computer fault injection hardware system is automatically realized by the following method:
s1, reading and analyzing a source code file of the circuit to be tested, and extracting information related to user design in the source code file, wherein the information related to user design comprises the name of a top-level module and interface design information, and the interface design information comprises the name, type and bit width information of a user IO interface used by the top-level module;
s2, automatically constructing a user design control circuit according to the name and interface design information of the top module of the circuit to be tested;
the specific steps of automatically constructing the user designed control circuit include:
automatically instantiating a circuit to be tested and a reference circuit according to the name of the top module of the circuit to be tested;
analyzing an input port and an output port according to the name, type and bit width information of a user IO interface in the interface design information of the circuit to be tested;
generating an excitation generating circuit matched with the input port;
a result comparison circuit is generated that matches the output port.
S3, the automatically generated user design control circuit and the preset general fault injection control circuit are connected and combined to generate a hardware description file of the fault injection system, the process of synthesizing, laying out and wiring of the fault injection system is automatically completed through the Tcl script to obtain an executable file of the fault injection system, and the executable file of the fault injection system is loaded into the FPGA used by the circuit to be tested to complete the automatic construction of the lower computer fault injection hardware system.
Further, in step S1, the circuit to be tested is a circuit designed by a user and implemented on an FPGA. The information related to user design refers to name and position information of a top module in the circuit and name and bit width information of input and output signals.
And the automatic building process of the lower computer fault injection hardware system is realized in the upper computer.
Based on the fault injection test system, the invention also provides an automatic FPGA fault injection method, which comprises the following steps:
s1, reading and analyzing a source code file of the circuit to be tested, and extracting the name and interface design information of a top module, wherein the interface design information comprises the name, type and bit width information of a user IO interface used by the top module;
s2, automatically constructing a user design control circuit according to the name and interface design information of the top module of the circuit to be tested;
s3, the automatically generated user design control circuit and the preset general fault injection control circuit are connected and combined to generate a hardware description file of the fault injection system, the process of synthesizing, laying out and wiring of the fault injection system is automatically completed through the Tcl script to obtain an executable file of the fault injection system, and the executable file of the fault injection system is loaded into the FPGA used by the circuit to be tested to complete the automatic construction of the lower computer fault injection hardware system.
S4, executing fault injection test: sending a fault injection command message to a lower computer fault injection hardware system by an upper computer, turning data frames in a preset address range of a circuit to be tested bit by bit, detecting output results of the circuit to be tested and a reference circuit under the same test excitation, judging whether the circuit to be tested has a fault, and counting the frequency of the fault;
and S5, after the preset addresses of the waiting circuit are all tested, uploading the counted failure times to an upper computer, and ending the process.
The fault injection test process is as follows: :
s4.1, the serial port communication circuit sends the fault injection command message received from the upper computer to the process control circuit;
s4.2, the process control circuit analyzes the fault injection command message, obtains the first address and the last address of the fault injection test from the fault injection command message, then sends a fault injection test starting signal to a user design control circuit, and the step S3 is entered;
s4.3, after the user design control circuit receives the fault injection test starting signal, the control result comparison circuit clears the injection fault count value;
s4.4, the process control circuit calculates the current test address and sends the read-back command and the test address to the reconfiguration interface control circuit;
s4.5, reconfiguring the interface control circuit, reading back frame data according to the test address after receiving the read-back command, and returning the frame data to the process control circuit;
s4.6, the process control circuit receives the read-back frame data fed back by the reconfiguration interface control circuit and then enters the step S7;
s4.7, performing bit flipping on the frame data, sending the frame data and the test address after the bit flipping to a reconfiguration interface control circuit through a reconfiguration command, and then sending an excitation starting signal to a user design control circuit;
s4.8, reconfiguring the interface control circuit, and reconfiguring the frame data after bit reversal into the circuit to be tested according to the test address after receiving the reconfiguration command;
s4.9, an excitation generating circuit receives an excitation starting signal and then initializes the excitation starting signal, after initialization, m-bit data are randomly generated in each clock period and serve as test excitation to be sent to a reference circuit and a circuit to be tested at the same time, 2mOne clock cycle traversing 2 of m-bit input busmData, wait for traversal 2mAfter the data, sending a data traversal end mark to a process control circuit;
s4.10, a result comparison circuit compares whether the data on the output bus after the reference circuit and the circuit to be tested are excited and driven are the same or not, if the data are different, the injected fault count is accumulated, otherwise, the injected fault count is kept unchanged, and then the injected fault count value is sent to the serial port communication circuit;
s4.11, the process control circuit enters the step S4.12 after receiving the data traversal end mark fed back by the excitation generating circuit;
s4.12, repeating the steps S4.7-S4.12 until all the bits of the same address frame data are turned over, re-executing the steps S4.4-S4.12 until the address traversal is finished, and sending a fault injection finishing identifier to the serial communication circuit;
and S4.13, the serial port communication circuit sends the fault count value to the upper computer.
The user design control circuit refers to a circuit related to user design, and cannot be reused along with the change of a circuit to be tested.
The fault injection control circuit is a circuit which is not influenced by user design and can be repeatedly used and is used for controlling the read-back, turnover and reconfiguration processes of fault injection and the interaction with an upper computer.
Example (b):
the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The FPGA development board used by the invention is Nexyz 4 of Xilinx company, and the FPGA model is Artix-7xc7a100tcsg 324.
The first embodiment is as follows:
the structure of the automatic FPGA fault injection system is shown in FIG. 1: the method comprises the steps that upper computer control software and a lower computer fault injection hardware system are included;
the upper computer controls software to be realized at a PC end, and in the process of establishing a fault injection system, a circuit to be tested is read and analyzed, information is extracted, and a lower computer hardware system is automatically generated; in the fault injection process, sending a control command and an address of fault injection to a lower computer;
the lower computer hardware system is realized on an FPGA and comprises a user designed control circuit and a fault injection control circuit, and controls the read-back, the turnover, the reconfiguration, the excitation generation and the result comparison of the fault injection;
fig. 2 shows a complete execution flow of the automatic FPGA fault injection method of this embodiment, which is specifically explained as follows:
step S1, reading and analyzing Verilog file of the circuit to be tested, extracting information related to user design, including name and position information of top module in the circuit and name and bit width information of input and output signals;
and step S2, automatically generating a user design control circuit according to the extracted information, and generating a complete hardware description file of the fault injection system by interconnecting and combining the user design control circuit and the fault injection control circuit. The user design control circuit is a circuit related to user design, can not be multiplexed along with the change of a circuit to be tested, and mainly comprises a circuit to be tested, a reference circuit, an excitation generating circuit and a result comparing circuit, wherein the circuit to be tested is used for generating a test excitation and driving circuit and comparing circuit results; the excitation generating circuit generates pseudo-random number excitation in a linear feedback shift register mode; the fault injection control circuit is a circuit which is not influenced by user design and can be repeatedly used, and mainly comprises a process control circuit, a reconfiguration interface control circuit and a serial port communication circuit, and is used for controlling the read-back, turnover and reconfiguration processes of fault injection and the interaction with an upper computer;
step S3, automatically completing the comprehensive implementation process of fault injection hardware through the Tcl script, and completing the automatic construction of a fault injection system; the Tcl script defines the automation processes of engineering creation, synthesis, layout and wiring and the like, and downloads the fault injection system to the FPGA to complete the automatic construction of the fault injection system;
step S4, fault injection is executed, the configuration bits are turned over bit by bit, the output states of the circuit to be tested and the reference circuit are detected, and whether an error occurs is judged; the specific process is shown in fig. 3: after receiving the command and the address, the lower computer reconfigures the single-frame data containing a bit-flipping configuration bit to the circuit to be tested; the same test excitation is used for driving the circuit to be tested and the reference circuit, the operation results of the circuit to be tested and the reference circuit are compared, and whether the circuit to be tested has a fault or not is judged; if the results are the same, the circuit to be tested does not have a fault; if the results are different, the circuit to be tested has a fault, and the address and fault information of the configuration bit are transmitted back to the upper computer; and repairing the configuration bit, turning over the next configuration bit, repeating the process until the address is at the end, and finishing the fault injection process.
And step S5, counting results after fault injection of all the configuration bits is finished, and ending the process.
Example two:
this example tests the following circuits: the Fin filter circuit and the three-mode redundant circuit Fin-TMR circuit thereof, the Sobel edge detection circuit and the three-mode redundant circuit Sobel-TMR circuit thereof, the Qsort quick sorting circuit and the three-mode redundant circuit Qsort-TMR thereof. The Fir filter is a finite-length single-bit impulse response filter and has wide application in the fields of communication, image processing, pattern recognition and the like. Sobel edge detection is used to compute an approximation of the gray scale of the image function. Triple Modular Redundancy (TMR) is the most common fault tolerant design technique, where three modules perform the same operation at the same time, with the most identical output as the correct output for the voting system.
The test results are shown in tables 1 and 2.
Table 1 fault injection system generated results
Table 2 fault injection test results
As can be seen from the data in table 1: the method of the invention is that the fault injection system with complete functions is successfully and automatically generated for 6 circuits in the embodiment; the average time for building the fault injection system by using the method is also far shorter than the average time for manually building the fault injection system.
As can be seen from the data in table 2: the sensitivity of the triple-modular redundancy circuit is greatly reduced compared with that of a common circuit, and the fault evaluation effect of the method is good.
In summary, the invention adaptively designs and generates the whole set of fault injection system for the user by analyzing the input circuit file to be tested, reduces the development difficulty of the fault injection system, assists the designer to quickly set up the fault injection system, and improves the efficiency of evaluating the reliability of the circuit.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Claims (7)
1. An automatic FPGA fault injection test system is characterized by comprising an upper computer and a lower computer fault injection hardware system, wherein the lower computer fault injection hardware system comprises a user designed control circuit and a fault injection control circuit; wherein:
the user design control circuit comprises a circuit to be tested, a reference circuit, an excitation generating circuit and a result comparing circuit;
the reference circuit is a copy of the circuit to be tested and comprises m-bit input buses and n-bit output buses, the m-bit input buses are simultaneously connected to the excitation generating circuit, the n-bit output ports are simultaneously connected to the result comparing circuit, and m and n are both more than or equal to 1;
a stimulus generation circuit for receiving a stimulus start signal and then initializing, and after initialization, randomly generating m-bit data in each clock cycle, as a test stimulus, and simultaneously transmitting the m-bit data to the reference circuit and the circuit to be tested, 2mOne clock cycle traversing 2 of m-bit input busmA piece of data;
the result comparison circuit is used for comparing whether the data on the output bus after the reference circuit and the circuit to be tested are excited and driven are the same or not, if the data are different, the injection fault counting value is accumulated, otherwise, the injection fault counting value is kept unchanged, and then the injection fault counting value is sent to the serial port communication circuit; in an initial state or after receiving a fault injection test starting signal, resetting an injection fault count;
the fault injection control circuit comprises a process control circuit, a reconfiguration interface control circuit and a serial port communication circuit;
the process control circuit receives the fault injection command message through the serial port communication circuit, analyzes the fault injection command message to obtain a first address and a last address of a fault injection test, sends a fault injection test starting signal to the user design control circuit, traverses the test addresses from the first address, reads back frame data of a corresponding address through the reconfiguration interface control circuit for each test address, turns over the read back frame data according to bits to obtain reconfiguration frame data, writes the reconfiguration frame data into the corresponding address through the reconfiguration interface control circuit, turns over one data bit once for the frame data of each address, traverses all the data bits, writes the reconfiguration frame data once, and sends an excitation starting signal once to the user design control circuit.
2. The automated FPGA fault injection test system of claim 1, wherein the lower computer fault injection hardware system is automatically implemented by:
s1, reading and analyzing a source code file of the circuit to be tested, and extracting the name and interface design information of a top module, wherein the interface design information comprises the name, type and bit width information of a user IO interface used by the top module;
s2, automatically constructing a user design control circuit according to the name and interface design information of the top module of the circuit to be tested;
s3, the automatically generated user design control circuit and the preset general fault injection control circuit are connected and combined to generate a hardware description file of the fault injection system, the process of synthesizing, laying out and wiring of the fault injection system is automatically completed through the Tcl script to obtain an executable file of the fault injection system, and the executable file of the fault injection system is loaded into the FPGA used by the circuit to be tested to complete the automatic construction of the lower computer fault injection hardware system.
3. The automated FPGA fault injection testing system of claim 2, wherein the specific step of automatically constructing the user designed control circuit in step S2 comprises:
automatically instantiating a circuit to be tested and a reference circuit according to the name of the top module of the circuit to be tested;
analyzing an input port and an output port according to the name, type and bit width information of a user IO interface in the interface design information of the circuit to be tested;
generating an excitation generating circuit matched with the input port;
a result comparison circuit is generated that matches the output port.
4. The automated FPGA fault injection testing system of claim 1, wherein the automatic set-up process of the lower computer fault injection hardware system is implemented in the upper computer.
5. The automated FPGA fault injection test system of claim 1, wherein said stimulus generation circuit employs a linear feedback shift register to generate pseudo-random numbers as test stimuli.
6. An automated FPGA fault injection test method based on the system of claim 1, characterized by comprising the steps of:
s1, reading and analyzing a source code file of the circuit to be tested, and extracting the name and interface design information of a top module, wherein the interface design information comprises the name, type and bit width information of a user IO interface used by the top module;
s2, automatically constructing a user design control circuit according to the name and interface design information of the top module of the circuit to be tested;
s3, the automatically generated user design control circuit and the preset general fault injection control circuit are connected and combined to generate a hardware description file of the fault injection system, the process of synthesizing, laying out and wiring of the fault injection system is automatically completed through the Tcl script to obtain an executable file of the fault injection system, and the executable file of the fault injection system is loaded into the FPGA used by the circuit to be tested to complete the automatic construction of the lower computer fault injection hardware system.
S4, executing fault injection test: sending a fault injection command message to a lower computer fault injection hardware system by an upper computer, turning data frames in a preset address range of a circuit to be tested bit by bit, detecting output results of the circuit to be tested and a reference circuit under the same test excitation, judging whether the circuit to be tested has a fault, and counting the frequency of the fault;
and S5, after the preset addresses of the waiting circuit are all tested, uploading the counted failure times to an upper computer, and ending the process.
7. The automated FPGA fault injection method of claim 6, wherein the fault injection test procedure is as follows: :
s4.1, the serial port communication circuit sends the fault injection command message received from the upper computer to the process control circuit;
s4.2, the process control circuit analyzes the fault injection command message, obtains the first address and the last address of the fault injection test from the fault injection command message, then sends a fault injection test starting signal to a user design control circuit, and the step S3 is entered;
s4.3, after the user design control circuit receives the fault injection test starting signal, the control result comparison circuit clears the injection fault count value;
s4.4, the process control circuit calculates the current test address and sends the read-back command and the test address to the reconfiguration interface control circuit;
s4.5, reconfiguring the interface control circuit, reading back frame data according to the test address after receiving the read-back command, and returning the frame data to the process control circuit;
s4.6, the process control circuit receives the read-back frame data fed back by the reconfiguration interface control circuit and then enters the step S7;
s4.7, performing bit flipping on the frame data, sending the frame data and the test address after the bit flipping to a reconfiguration interface control circuit through a reconfiguration command, and then sending an excitation starting signal to a user design control circuit;
s4.8, reconfiguring the interface control circuit, and reconfiguring the frame data after bit reversal into the circuit to be tested according to the test address after receiving the reconfiguration command;
s4.9, excitation generating circuit, which receives excitation starting signal and then carries outInitialization, after which m-bit data are randomly generated every clock cycle, as test stimuli, and sent to the reference circuit and the circuit under test simultaneously, 2mOne clock cycle traversing 2 of m-bit input busmData, wait for traversal 2mAfter the data, sending a data traversal end mark to a process control circuit;
s4.10, a result comparison circuit compares whether the data on the output bus after the reference circuit and the circuit to be tested are excited and driven are the same or not, if the data are different, the injected fault count is accumulated, otherwise, the injected fault count is kept unchanged, and then the injected fault count value is sent to the serial port communication circuit;
s4.11, the process control circuit enters the step S4.12 after receiving the data traversal end mark fed back by the excitation generating circuit;
s4.12, repeating the steps S4.7-S4.12 until all the bits of the same address frame data are turned over, re-executing the steps S4.4-S4.12 until the address traversal is finished, and sending a fault injection finishing identifier to the serial communication circuit;
and S4.13, the serial port communication circuit sends the fault count value to the upper computer.
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