CN106802645A - A kind of FPGA single particle overturns fault simulation system and method - Google Patents
A kind of FPGA single particle overturns fault simulation system and method Download PDFInfo
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- CN106802645A CN106802645A CN201611193066.2A CN201611193066A CN106802645A CN 106802645 A CN106802645 A CN 106802645A CN 201611193066 A CN201611193066 A CN 201611193066A CN 106802645 A CN106802645 A CN 106802645A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0208—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterized by the configuration of the monitoring system
- G05B23/0213—Modular or universal configuration of the monitoring system, e.g. monitoring system having modules that may be combined to build monitoring program; monitoring system that can be applied to legacy systems; adaptable monitoring system; using different communication protocols
Abstract
The invention discloses a kind of FPGA single particle upset fault simulation system and method, wherein, the system includes：Including TCL Script controlling module host computers, and, including circuit under test, contrast circuit and supervisory circuit slave computer；TCL Script controlling modules, the acquisition for carrying out single-particle inversion fault simulation and monitored results data；Circuit under test, for being run under the single-particle inversion failure environment of simulation；Contrast circuit, for running in normal circumstances；Supervisory circuit, is monitored for the circuit operations conditions to circuit under test and contrast circuit.In the present invention, the TCL Script controllings module positioned at host computer directly controls the flow of single-particle inversion fault simulation, and the auxiliary of circuit is controlled without lower computer hardware；The design of slave computer circuit does not rely on the characteristic of target FPGA device, unrelated with device architectures, and user's design need not be changed when being transplanted to other FPGA devices.
Description
Technical field
The invention belongs to technical field of measurement and test, more particularly to a kind of FPGA single particle upset fault simulation system and method.
Background technology
FPGA (Field Programmable Gate Array, field programmable gate array) is under radiation environment by single
Particle overturns the influence of effect, and the logic state of configuration bit easily overturns in configuration bit stream, so as to destroy circuit function.Simple grain
Son upset fault simulation is the reliability that a kind of artificial upset configuration bit stream is worked with assessment circuit under Single event upset effecf
Method.Conventional mode is to set up the single-particle inversion fault simulation system being made up of host computer and slave computer (hardware circuit)
System.The host computer of the single-particle inversion fault simulation system provides user interface, is responsible for transmission, the storage of data of operational order
And display；Objective circuit of the slave computer comprising fault simulation and control circuit, control circuit receive the operational order of host computer, directly
Connect the flow of control fault simulation.
The mode of operation of existing single-particle inversion fault simulation system, the initiative of control is grasped by hardware circuit, on
Position machine is only the role of manager.However, because control circuit function is complicated, circuit scale is big, generally independently of reality
Realized on another fpga chip of the fpga chip of existing objective circuit, so, the hardware spending of system will be improved.
Secondly, in existing single-particle inversion fault simulation system, host computer uses serial communication protocol with slave computer
Interact, the data of exchange include the circuit service data of Row control order and collection.Slave computer receives life in serial ports
Corresponding function could be performed after order, and fault simulation is carried out in units of configuration bit, therefore to each configuration bit
Fault simulation all with serial ports receive order for start, serial ports upload data for terminate, afterwards continue next bit fault simulation,
The speed of service of circuit is largely limited by communication pattern.
Additionally, also there is a system portability in existing single-particle inversion fault simulation system：Hardware system
The intrinsic exclusiveness of system and control circuit cause opening for single-particle inversion fault simulation system to the dependence of target devices characteristic
The hair cycle is long, and system portability is poor, and only the FPGA device to target model is applicable.
The content of the invention
Technology solve problem of the invention：Overcome the deficiencies in the prior art, there is provided a kind of FPGA single particle overturns failure mould
Intend system and method, the TCL Script controllings module positioned at host computer directly controls the flow of single-particle inversion fault simulation, without
Lower computer hardware controls the auxiliary of circuit；The design of slave computer circuit does not rely on the characteristic of target FPGA device, with device frame
Structure is unrelated, and user's design need not be changed when being transplanted to other FPGA devices.
In order to solve the above-mentioned technical problem, the invention discloses a kind of FPGA single particle upset fault simulation system, including：
Host computer and slave computer；Wherein, the host computer, including：TCL Script controlling modules；The slave computer, including：Circuit under test,
Contrast circuit and supervisory circuit；
TCL Script controlling modules, for choosing an address element from the address set of target configuration bit stream；And,
Frame address and position skew in the address element, carries out single-particle inversion fault simulation；
Circuit under test, for being run under the single-particle inversion failure environment of simulation；
Contrast circuit, for running in normal circumstances；
Supervisory circuit, is monitored for the circuit operations conditions to circuit under test and contrast circuit；
TCL Script controlling modules, are additionally operable to obtain the monitored results data of supervisory circuit.
In above-mentioned FPGA single particle upset fault simulation system, the TCL Script controllings module, including：
Retaking of a year or grade submodule, for performing retaking of a year or grade function according to the frame address, obtains retaking of a year or grade frame data from slave computer；
Code stream overturns submodule, for according to institute's rheme skew, being carried out to the target configuration bit in the retaking of a year or grade frame data
Logic overturns, and obtains overturning frame data；
Submodule is reconfigured, for performing and reconfiguring function according to the frame address and upset frame data, slave computer is entered
Row single-particle inversion fault simulation.
In above-mentioned FPGA single particle upset fault simulation system, the TCL Script controllings module also includes：
Direct fault location interface, for receiving address element；
Communication interface, for carrying out data interaction with slave computer；Wherein, interactive data include：Frame address, retaking of a year or grade frame number
According to upset frame data, and, boundary scan command, retaking of a year or grade configuration order and reconfigure order；And, the supervisory circuit
Monitored results data.
In above-mentioned FPGA single particle upset fault simulation system, the communication interface, for the boundary scan to be ordered
Make, retaking of a year or grade configuration order and frame address are sent to the jtag interface of slave computer, and receive the retaking of a year or grade frame data of jtag interface return；
And, by the boundary scan command, reconfigure order, frame address and upset frame data send to the jtag interface of slave computer；
And, the monitored results data of the supervisory circuit that reception is reported by the telecommunication circuit of slave computer.
In above-mentioned FPGA single particle upset fault simulation system, the contrast circuit is the backup electricity of the circuit under test
Road.
In above-mentioned FPGA single particle upset fault simulation system, the TCL Script controllings module is additionally operable to start TCL
Script running environment, and, to initialization system parameter；Wherein, the systematic parameter includes：FPGA device model, frame length,
Location index and configuration order form in JTAG chains.
The invention also discloses a kind of FPGA single particle upset failure simulation method, including：
An address element is chosen from the address set of target configuration bit stream；Wherein, the address element includes：Frame ground
Location and position offset；
Offset according to the frame address and position, carry out single-particle inversion fault simulation；
The circuit operations conditions that circuit under test is run under the single-particle inversion failure environment of simulation are obtained, and, contrast
The circuit operations conditions that circuit runs in normal circumstances, determine the comparing of the circuit operations conditions of circuit under test and contrast circuit
As a result；
The whole address elements in the address set are traveled through successively, determine the corresponding circuit operation shape of each address element
The comparative result of state, and export.
It is described to be offset according to the frame address and position in above-mentioned FPGA single particle upset failure simulation method, carry out list
Particle overturns fault simulation, including：
Retaking of a year or grade function is performed according to the frame address, retaking of a year or grade frame data are obtained from slave computer；
According to institute's rheme skew, logic upset is carried out to the target configuration bit in the retaking of a year or grade frame data, obtain overturning frame
Data；
Perform and reconfigure function according to the frame address and upset frame data, single-particle inversion failure mould is carried out to slave computer
Intend.
In above-mentioned FPGA single particle upset failure simulation method, the FPGA single particle upset failure simulation method is based on
TCL scripts are realized.
The present invention has advantages below：
(1) in the present invention, positioned at TCL (Tool Command Language, Tool Command Language) script of host computer
Control module directly controls the flow of single-particle inversion fault simulation, and the auxiliary of circuit is controlled without lower computer hardware；Slave computer
The design of circuit does not rely on the characteristic of target FPGA device, unrelated with device architectures, need not when being transplanted to other FPGA devices
Change user's design.
(2), compared to existing single-particle inversion fault simulation system, control circuit function is simple, circuit scale for the present invention
It is small, it is the circuit arrangement being capable of achieving in slave computer using fpga chip, reduce the hardware spending of system.
(3) present invention employs TCL shell scripts, compared with hardware control circuit, the construction cycle greatly shortens；Meanwhile,
Communication transfer circuit service data between host computer and slave computer, it is no longer necessary to transmission flow control command, reduces and is
The time overhead of system.
(4) in the present invention, flexible configuration can be carried out to sorts of systems parameter by TCL shell scripts, e.g., the system
System parameter is included but are not limited to：FPGA device model, frame length and configuration order form, and FPGA device is in JTAG
Location index in (Joint Test Action Group, joint test working group) chain etc., makes to present invention can be suitably applied to various
SRAM (Static Random Access Memory, static RAM) type FPGA device, and, slave computer circuit
Device architectures of each sub-circuit with FPGA device it is unrelated, it is ensured that the portability of system.
Brief description of the drawings
Fig. 1 is a kind of structural representation of FPGA single particle upset fault simulation system in the embodiment of the present invention；
The step of Fig. 2 is a kind of FPGA single particle upset failure simulation method in embodiment of the present invention flow chart.
Specific embodiment
It is public to the present invention below in conjunction with accompanying drawing to make the object, technical solutions and advantages of the present invention clearer
Implementation method is described in further detail.
Reference picture 1, shows a kind of structural representation of FPGA single particle upset fault simulation system in the embodiment of the present invention
Figure.In the present embodiment, the FPGA single particle upset fault simulation system, including：Host computer 100 and slave computer 200.Its
In, the host computer 100 includes：TCL Script controllings module 110.The slave computer 200 (namely FPGA device) includes：It is to be measured
Circuit 210, contrast circuit 220 and supervisory circuit 230.
TCL Script controllings module 110, for choosing an address element from the address set of target configuration bit stream；With
And, frame address and the position skew in the address element carry out single-particle inversion fault simulation.
In the present embodiment, two special position attributions due to configuration bit in configuration memory are frame address and position
Skew, therefore, unique configuration bit can be positioned according to frame address and position skew.User can be with the event of a previously given single-particle inversion
Hinder the address set of the target configuration bit stream of simulation, the address set is actually the address information of code stream, each in set
Element (address element) all includes：Frame address and position offset two attributes, that is, element form can be：(fa, bo)；Wherein
Fa is frame address, and bo is position skew.Frame address and position skew in the address element, can carry out single-particle inversion event
The simulation of barrier.
Circuit under test 210, for being run under the single-particle inversion failure environment of simulation；Contrast circuit 220, for just
Run under normal environment.
In the present embodiment, contrast circuit 220 can be the fallback circuit of circuit under test 210, circuit under test 210 and contrast
Circuit 220 is separately operable under the single-particle inversion failure environment of simulation and under home, to two circuit operations of circuit
State is observed, and result can determine whether the configuration bit of current single-particle inversion changes circuit function according to the observation.
Supervisory circuit 230, is monitored for the circuit operations conditions to circuit under test 210 and contrast circuit 220.
TCL Script controllings module 110, is additionally operable to obtain the monitored results data of supervisory circuit.
In the preferred embodiment of the present invention, as shown in figure 1, TCL Script controllings module 110, can specifically include：Return
Read submodule 111, code stream upset submodule 112, reconfigure submodule 113, direct fault location interface 114 and communication interface 115.Institute
Stating slave computer 200 can also include：Telecommunication circuit 240 and jtag interface 250；Wherein, each circuit in slave computer 200 can be with cloth
Put on same fpga chip.
Preferably,
Direct fault location interface 114 overturns submodule 112 and matches somebody with somebody again towards configuration bit stream with reference to retaking of a year or grade submodule 111, code stream
Submodule 113 is put, single-particle inversion fault simulation is realized.The brow-down position machine 200 of communication interface 115, realizes host computer 100 with
The interaction of data between the machine 200 of position；Wherein, interactive data are included but are not limited to：Frame address, retaking of a year or grade frame data and upset frame
The configuration datas such as data；And, boundary scan command, retaking of a year or grade configuration order and reconfigure the configuration orders such as order；And, monitoring
The monitored results data of circuit 230.Wherein, when communication interface 115 is that slave computer 200 carries out data interaction, specifically can be with base
Communicated with slave computer 200 in jtag interface 250, the friendship of configuration order and configuration data between realization and slave computer 200
Mutually；And, the telecommunication circuit 240 based on serial ports configuration is communicated with slave computer 200, is realized and the prison between slave computer 200
Control the interaction of result data.
In the present embodiment, specifically：
Direct fault location interface 114, for receiving address element.
As it was previously stated, the address set of the target configuration bit stream can be pre-stored in host computer 100, and e.g., document 1
In.Direct fault location interface 114 can read the address element in address set from document 1, the frame ground in address element
Location and position are offset, and the single-particle inversion of fixed point is realized on the configuration bit stream for having obtained.
Retaking of a year or grade submodule 111, for performing retaking of a year or grade function according to the frame address, obtains retaking of a year or grade frame from slave computer 200
Data.
In the present embodiment, the frame address that retaking of a year or grade submodule 111 can receive direct fault location interface 114, and, border
Scan command and retaking of a year or grade configuration order are sent to jtag interface 250 by communication interface 115, perform retaking of a year or grade function；Slave computer 200
After frame address, boundary scan command and retaking of a year or grade configuration order is received, it may be determined that corresponding retaking of a year or grade frame data, slave computer
200 are sent to communication interface 115 retaking of a year or grade frame data by jtag interface 250, and then, retaking of a year or grade submodule 111 is from slave computer 200
Middle acquisition retaking of a year or grade frame data.
Code stream overturns submodule 112, for according to institute's rheme skew, entering to the target configuration bit in the retaking of a year or grade frame data
Row logic overturns, and obtains overturning frame data.
Submodule 113 is reconfigured, for performing and reconfiguring function according to the frame address and upset frame data, to slave computer
200 carry out single-particle inversion fault simulation.
In the present embodiment, reconfiguring submodule 113 can refer to the upset frame data that obtain of logic upset, boundary scan
Make, reconfigure order and frame address and sent to jtag interface 250 by communication interface 115, execution reconfigures function, realizes list
Particle overturns fault simulation.
As it was previously stated, TCL Script controllings module 110, is additionally operable to obtain the monitored results data of supervisory circuit 230.Specifically
, the monitored results data of supervisory circuit 240 can be uploaded to TCL scripts by telecommunication circuit 240 by the communication interface 115
Control module 110.Preferably, the monitored results data that TCL Script controllings module 110 will can be received can be stored in upper
Machine 100 is local, e.g., is stored in the document 2 in host computer 100.
In the preferred embodiment of the present invention, the TCL Script controllings module 110, can be also used for starting TCL scripts
Running environment, and, to initialization system parameter；Wherein, the systematic parameter is included but are not limited to：FPGA device model, frame
The long, location index in JTAG chains and configuration order form etc..
With reference to above-described embodiment, reference picture 2 shows a kind of FPGA single particle upset fault simulation in the embodiment of the present invention
The step of method flow chart.In the present embodiment, the FPGA single particle upset failure simulation method can be based on TCL script realities
Existing, methods described can specifically include：
Step 301, starts TCL script running environment.
In the present embodiment, the integrated software conditions with micro supporting with target FPGA device provides the running environment of TCL scripts,
The jtag interface of FPGA device can be accessed by TCL scripts, starts script running environment.
Step 302, Initialize installation.
In the present embodiment, before program operation, Initialize installation can be carried out to systematic parameter in the preparatory stage.
Such as, initialization JTAG configurations chain, initialize FPGA device location index in JTAG chains of model and frame length, FPGA device and
Configuration order form etc..Wherein, by Initialize installation, the compatible various SRAM type FPGA devices of scheme of the present invention can be made
Part.
Step 303, chooses an address element from the address set of target configuration bit stream.
In the present embodiment, each address element can include：Frame address and position offset.
Step 304, offsets according to the frame address and position, carries out single-particle inversion fault simulation.
In the present embodiment, implementing for single-particle inversion fault simulation can be as follows：Performed according to the frame address
Retaking of a year or grade function, obtains retaking of a year or grade frame data from slave computer；According to institute's rheme skew, to the target configuration in the retaking of a year or grade frame data
Position carries out logic upset, obtains overturning frame data；Perform and reconfigure function according to the frame address and upset frame data, to bottom
Machine carries out single-particle inversion fault simulation.
Step 305, runs circuit under various circumstances.
In the present embodiment, the circuit under test of slave computer is run under the single-particle inversion failure of simulation, circuit under test
Circuit runs fallback circuit under trouble-free normal mode of operation as a comparison；Wherein, circuit under test and contrast circuit are to use
Family circuit design interested.
Step 306, obtains the circuit operations conditions that circuit under test is run under the single-particle inversion failure environment of simulation, with
And, the circuit operations conditions that contrast circuit is run in normal circumstances determine the circuit operation shape of circuit under test and contrast circuit
The comparative result of state.
Step 307, travels through the whole address elements in the address set successively, determines the corresponding electricity of each address element
The comparative result of road running status, and export.
In the present embodiment, can be with repeat step 303-306 to all address elements traveled through in address set.Wherein,
Step 301-304 can control FPGA to realize by running TCL scripts；Step 305 is to be realized on hardware circuit completely.
Step 308, flow terminates, and host computer preserves comparative result.
For embodiment of the method, because it is corresponding with device embodiment, so description is fairly simple, correlation
Place referring to device embodiment part explanation.
Each embodiment in this explanation is described by the way of progressive, and what each embodiment was stressed is and it
The difference of his embodiment, between each embodiment identical similar part mutually referring to.
In sum, in embodiments of the present invention, the TCL Script controllings module positioned at host computer directly controls single-particle to turn over
Turn the flow of fault simulation, the auxiliary of circuit is controlled without lower computer hardware；The design of slave computer circuit does not rely on target
The characteristic of FPGA device, it is unrelated with device architectures, user's design need not be changed when being transplanted to other FPGA devices.
Secondly, compared to existing single-particle inversion fault simulation system, the control circuit function in the present invention is simple, electricity
Road small scale, is the circuit arrangement being capable of achieving in slave computer using fpga chip, reduces the hardware spending of system.
Again, compared with hardware control circuit, the construction cycle of TCL shell scripts is short；Meanwhile, host computer and slave computer it
Between communication transfer circuit service data, it is no longer necessary to transmission flow control command, reduce the time overhead of system.
Additionally, in the present invention, flexible configuration can be carried out to sorts of systems parameter by TCL shell scripts, it is e.g., described
Systematic parameter is included but are not limited to：FPGA device model, frame length and configuration order form, and FPGA device is in JTAG chains
In location index etc., make to present invention can be suitably applied to various SRAM type FPGA devices, and, each sub-circuit of slave computer circuit is equal
Device architectures with FPGA device are unrelated, it is ensured that the portability of system.
The above, optimal specific embodiment only of the invention, but protection scope of the present invention is not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can be readily occurred in,
Should all be included within the scope of the present invention.
The content not being described in detail in description of the invention belongs to the known technology of professional and technical personnel in the field.
Claims (9)
1. a kind of FPGA single particle overturns fault simulation system, it is characterised in that including：Host computer and slave computer；Wherein, it is described
Host computer, including：TCL Script controlling modules；The slave computer, including：Circuit under test, contrast circuit and supervisory circuit；
TCL Script controlling modules, for choosing an address element from the address set of target configuration bit stream；And, according to
Frame address and position skew in the address element, carries out single-particle inversion fault simulation；
Circuit under test, for being run under the single-particle inversion failure environment of simulation；
Contrast circuit, for running in normal circumstances；
Supervisory circuit, is monitored for the circuit operations conditions to circuit under test and contrast circuit；
TCL Script controlling modules, are additionally operable to obtain the monitored results data of supervisory circuit.
2. system according to claim 1, it is characterised in that the TCL Script controllings module, including：
Retaking of a year or grade submodule, for performing retaking of a year or grade function according to the frame address, obtains retaking of a year or grade frame data from slave computer；
Code stream overturns submodule, for according to institute's rheme skew, logic being carried out to the target configuration bit in the retaking of a year or grade frame data
Upset, obtains overturning frame data；
Submodule is reconfigured, for performing and reconfiguring function according to the frame address and upset frame data, list is carried out to slave computer
Particle overturns fault simulation.
3. system according to claim 2, it is characterised in that the TCL Script controllings module, also includes：
Direct fault location interface, for receiving address element；
Communication interface, for carrying out data interaction with slave computer；Wherein, interactive data include：Frame address, retaking of a year or grade frame data and
Upset frame data, and, boundary scan command, retaking of a year or grade configuration order and reconfigure order；And, the monitoring of the supervisory circuit
Result data.
4. system according to claim 3, it is characterised in that
The communication interface, for the boundary scan command, retaking of a year or grade configuration order and frame address to be sent to slave computer
Jtag interface, and receive the retaking of a year or grade frame data of jtag interface return；And, by the boundary scan command, reconfigure order, frame
Address and upset frame data are sent to the jtag interface of slave computer；And, the institute that reception is reported by the telecommunication circuit of slave computer
State the monitored results data of supervisory circuit.
5. system according to claim 1, it is characterised in that the contrast circuit is the backup electricity of the circuit under test
Road.
6. system according to claim 1, it is characterised in that the TCL Script controllings module, is additionally operable to start TCL pin
This running environment, and, to initialization system parameter；Wherein, the systematic parameter includes：FPGA device model, frame length, in JTAG
Location index and configuration order form in chain.
7. a kind of FPGA single particle overturns failure simulation method, it is characterised in that including：
An address element is chosen from the address set of target configuration bit stream；Wherein, the address element includes：Frame address and
Position skew；
Offset according to the frame address and position, carry out single-particle inversion fault simulation；
The circuit operations conditions that circuit under test is run under the single-particle inversion failure environment of simulation are obtained, and, contrast circuit
The circuit operations conditions for running in normal circumstances, determine the comparing knot of the circuit operations conditions of circuit under test and contrast circuit
Really；
The whole address elements in the address set are traveled through successively, determine the corresponding circuit operations conditions of each address element
Comparative result, and export.
8. method according to claim 7, it is characterised in that described to be offset according to the frame address and position, carries out simple grain
Son upset fault simulation, including：
Retaking of a year or grade function is performed according to the frame address, retaking of a year or grade frame data are obtained from slave computer；
According to institute's rheme skew, logic upset is carried out to the target configuration bit in the retaking of a year or grade frame data, obtain overturning frame data；
Perform and reconfigure function according to the frame address and upset frame data, single-particle inversion fault simulation is carried out to slave computer.
9. the method according to claim 7 or 8, it is characterised in that the FPGA single particle overturns failure simulation method base
Realized in TCL scripts.
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| CN108388147B (en) * | 2018-02-12 | 2021-03-16 | 中南大学 | Real-time fault injection timing sequence resource optimization method and system thereof |
| CN109858195A (en) * | 2019-03-22 | 2019-06-07 | 中国科学院光电技术研究所 | The on-line simulation system of necessary position single-particle inversion failure on a kind of SRAM type FPGA |
| CN109858195B (en) * | 2019-03-22 | 2022-11-08 | 中国科学院光电技术研究所 | Online simulation system for necessary bit single-particle upset fault on SRAM (static random Access memory) type FPGA (field programmable Gate array) |
| CN113886158A (en) * | 2021-09-28 | 2022-01-04 | 北京时代民芯科技有限公司 | Automatic FPGA fault injection test system and method |
| CN113886158B (en) * | 2021-09-28 | 2024-04-02 | 北京时代民芯科技有限公司 | Automatic FPGA fault injection test system and method |
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