CN106802645B - A kind of FPGA single particle overturning fault simulation system and method - Google Patents
A kind of FPGA single particle overturning fault simulation system and method Download PDFInfo
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- CN106802645B CN106802645B CN201611193066.2A CN201611193066A CN106802645B CN 106802645 B CN106802645 B CN 106802645B CN 201611193066 A CN201611193066 A CN 201611193066A CN 106802645 B CN106802645 B CN 106802645B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0208—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterized by the configuration of the monitoring system
- G05B23/0213—Modular or universal configuration of the monitoring system, e.g. monitoring system having modules that may be combined to build monitoring program; monitoring system that can be applied to legacy systems; adaptable monitoring system; using different communication protocols
Abstract
The invention discloses a kind of FPGA single particle overturning fault simulation system and methods, wherein the system comprises: including TCL Script controlling module host computer, and, including circuit under test, contrast circuit and the slave computer for monitoring circuit；TCL Script controlling module, for carrying out the acquisition of single-particle inversion fault simulation and monitored results data；Circuit under test, for being run under the single-particle inversion failure environment of simulation；Contrast circuit, for running in normal circumstances；Circuit is monitored, is monitored for the circuit operations conditions to circuit under test and contrast circuit.In the present invention, the process that single-particle inversion fault simulation is directly controlled positioned at the TCL Script controlling module of host computer, the auxiliary without lower computer hardware control circuit；Characteristic of the design of slave computer circuit independent of target FPGA device, it is unrelated with device architectures, without changing user's design when being transplanted to other FPGA devices.
Description
Technical field
The invention belongs to the field of test technology more particularly to a kind of FPGA single particle overturning fault simulation system and methods.
Background technique
FPGA (Field Programmable Gate Array, field programmable gate array) is under radiation environment by list
Particle overturns the influence of effect, and the logic state of configuration bit is easily flipped in configuration bit stream, to destroy circuit function.Simple grain
Son overturning fault simulation is a kind of reliability that artificial overturning configuration bit stream is worked under Single event upset effecf with assessment circuit
Method.Common mode is to establish the single-particle inversion fault simulation system being made of upper computer and lower computer (hardware circuit)
System.The host computer of the single-particle inversion fault simulation system provides user interface, is responsible for the transmission of operational order, the storage of data
And display；Slave computer includes the objective circuit and control circuit of fault simulation, and control circuit receives the operational order of host computer, directly
Connect the process of control fault simulation.
The operating mode of existing single-particle inversion fault simulation system, the initiative of control are grasped by hardware circuit, on
Position machine is only the role of a manager.However, circuit scale is big, usually independently of reality since control circuit function is complicated
It is realized on another fpga chip of the fpga chip of existing objective circuit, so, the hardware spending of system will improve.
Secondly, host computer and slave computer use serial communication protocol in existing single-particle inversion fault simulation system
It interacts, the data of exchange include the circuit operation data of Row control order and acquisition.Slave computer receives life in serial ports
Corresponding function could be executed after order, and fault simulation is carried out as unit of configuration bit, therefore to each configuration bit
Fault simulation all using serial ports receive order be start, serial ports upload data as end, later continuation next bit fault simulation,
The speed of service of circuit is largely limited by communication pattern.
In addition, existing single-particle inversion fault simulation system the problem of there is also a system portabilities: hardware system
The exclusiveness and control circuit for uniting intrinsic lead to opening for single-particle inversion fault simulation system to the dependence of target devices characteristic
It is long to send out the period, and system portability is poor, only the FPGA device of target model is applicable in.
Summary of the invention
Technology of the invention solves the problems, such as: overcoming the deficiencies of the prior art and provide a kind of FPGA single particle overturning failure mould
Quasi- system and method, the process of single-particle inversion fault simulation is directly controlled positioned at the TCL Script controlling module of host computer, is not necessarily to
The auxiliary of lower computer hardware control circuit；Characteristic of the design of slave computer circuit independent of target FPGA device, with device frame
Structure is unrelated, without changing user's design when being transplanted to other FPGA devices.
In order to solve the above-mentioned technical problem, the invention discloses a kind of FPGA single particles to overturn fault simulation system, comprising:
Upper computer and lower computer；Wherein, the host computer, comprising: TCL Script controlling module；The slave computer, comprising: circuit under test,
Contrast circuit and monitoring circuit；
TCL Script controlling module, for choosing an address element from the address set of target configuration bit stream；And
According in the address element frame address and position offset, carry out single-particle inversion fault simulation；
Circuit under test, for being run under the single-particle inversion failure environment of simulation；
Contrast circuit, for running in normal circumstances；
Circuit is monitored, is monitored for the circuit operations conditions to circuit under test and contrast circuit；
TCL Script controlling module is also used to obtain the monitored results data of monitoring circuit.
In above-mentioned FPGA single particle overturning fault simulation system, the TCL Script controlling module, comprising:
Readback submodule obtains read back frame data for executing readback function according to the frame address from slave computer；
Code stream overturns submodule, for being deviated according to institute's rheme, carries out to the target configuration bit in the read back frame data
Logic overturning obtains overturning frame data；
Reconfigure submodule, for according to the frame address and overturning frame data execution reconfigure function, to slave computer into
Row single-particle inversion fault simulation.
In above-mentioned FPGA single particle overturning fault simulation system, the TCL Script controlling module, further includes:
Direct fault location interface, for receiving address element；
Communication interface, for carrying out data interaction with slave computer；Wherein, interactive data include: frame address, readback frame number
According to overturning frame data, and, boundary scan command, readback configuration order and reconfigure order；And the monitoring circuit
Monitored results data.
In above-mentioned FPGA single particle overturning fault simulation system, the communication interface, for ordering the boundary scan
Enable, readback configuration order and frame address are sent to the jtag interface of slave computer, and receive jtag interface return read back frame data；
And by the boundary scan command, reconfigure order, frame address and overturning frame data and be sent to the jtag interface of slave computer；
And receive the monitored results data of the monitoring circuit reported by the telecommunication circuit of slave computer.
In above-mentioned FPGA single particle overturning fault simulation system, the contrast circuit is the backup electricity of the circuit under test
Road.
In above-mentioned FPGA single particle overturning fault simulation system, the TCL Script controlling module is also used to start TCL
Script running environment, and, to initialization system parameter；Wherein, the system parameter include: FPGA device model, frame length,
Location index and configuration order format in JTAG chain.
The invention also discloses a kind of FPGA single particles to overturn failure simulation method, comprising:
An address element is chosen from the address set of target configuration bit stream；Wherein, the address element includes: frame
Location and position offset；
It is deviated according to the frame address and position, carries out single-particle inversion fault simulation；
The circuit operations conditions that circuit under test is run under the single-particle inversion failure environment of simulation are obtained, and, comparison
The circuit operations conditions that circuit is run in normal circumstances determine the comparison of the circuit operations conditions of circuit under test and contrast circuit
As a result；
Whole address elements in the address set are successively traversed, determine the corresponding circuit operation shape of each address element
The comparison result of state, and export.
It is described to be deviated according to the frame address and position in above-mentioned FPGA single particle overturning failure simulation method, it carries out single
Particle overturns fault simulation, comprising:
Readback function is executed according to the frame address, read back frame data is obtained from slave computer；
It is deviated according to institute's rheme, logic overturning is carried out to the target configuration bit in the read back frame data, obtain overturning frame
Data；
Function is reconfigured according to the frame address and overturning frame data execution, single-particle inversion failure mould is carried out to slave computer
It is quasi-.
In above-mentioned FPGA single particle overturning failure simulation method, the FPGA single particle overturning failure simulation method is based on
TCL script is realized.
The invention has the following advantages that
(1) in the present invention, positioned at the TCL of host computer (Tool Command Language, Tool Command Language) script
Control module directly controls the process of single-particle inversion fault simulation, the auxiliary without lower computer hardware control circuit；Slave computer
Characteristic of the design of circuit independent of target FPGA device, it is unrelated with device architectures, it is not necessarily to when being transplanted to other FPGA devices
Change user's design.
(2) present invention is compared to existing single-particle inversion fault simulation system, and control circuit function is simple, circuit scale
It is small, the circuit arrangement in slave computer can be realized using a fpga chip, reduce the hardware spending of system.
(3) present invention employs TCL shell scripts, and compared with hardware control circuit, the development cycle is greatly shortened；Meanwhile
Communication transfer circuit operation data between host computer and slave computer, it is no longer necessary to which transmission flow control command reduces and is
The time overhead of system.
(4) in the present invention, flexible configuration, e.g., the system can be carried out to sorts of systems parameter by TCL shell script
System parameter includes but are not limited to: FPGA device model, frame length and configuration order format and FPGA device are in JTAG
Location index etc. in (Joint Test Action Group, joint test working group) chain, makes present invention can be suitably applied to a variety of
SRAM (Static Random Access Memory, static random access memory) type FPGA device, and, slave computer circuit
Each sub-circuit it is unrelated with the device architectures of FPGA device, it is ensured that the portability of system.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of FPGA single particle overturning fault simulation system in the embodiment of the present invention；
Fig. 2 is a kind of step flow chart of FPGA single particle overturning failure simulation method in the embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, public to the present invention below in conjunction with attached drawing
Embodiment is described in further detail.
Referring to Fig.1, a kind of structural representation of FPGA single particle overturning fault simulation system in the embodiment of the present invention is shown
Figure.In the present embodiment, the FPGA single particle overturns fault simulation system, comprising: host computer 100 and slave computer 200.Its
In, the host computer 100 includes: TCL Script controlling module 110.The slave computer 200 (namely FPGA device) includes: to be measured
Circuit 210, contrast circuit 220 and monitoring circuit 230.
TCL Script controlling module 110, for choosing an address element from the address set of target configuration bit stream；With
And according in the address element frame address and position deviate, carry out single-particle inversion fault simulation.
In the present embodiment, two dedicated position attributions due to configuration bit in configuration memory are frame address and position
Offset, therefore, unique configuration bit can be positioned according to frame address and position offset.User can be with previously given single-particle inversion event
Hinder the address set of the target configuration bit stream of simulation, which is actually the address information of code stream, each of set
Element (address element) all includes: that frame address and position deviate two attributes, that is, element form can be with are as follows: (fa, bo)；Wherein
Fa is frame address, and bo is position offset.According in the address element frame address and position offset, can carry out single-particle inversion therefore
The simulation of barrier.
Circuit under test 210, for being run under the single-particle inversion failure environment of simulation；Contrast circuit 220, for just
It is run under normal environment.
In the present embodiment, contrast circuit 220 can be the fallback circuit of circuit under test 210, circuit under test 210 and comparison
Circuit 220 is separately operable under the single-particle inversion failure environment of simulation under normal environment, is run to the circuit of two circuits
State is observed, and result can determine whether the configuration bit of current single-particle inversion changes circuit function according to the observation.
Circuit 230 is monitored, is monitored for the circuit operations conditions to circuit under test 210 and contrast circuit 220.
TCL Script controlling module 110 is also used to obtain the monitored results data of monitoring circuit.
In the preferred embodiment of the present invention, as shown in Figure 1, TCL Script controlling module 110, can specifically include: returning
It reads submodule 111, code stream overturning submodule 112, reconfigure submodule 113, direct fault location interface 114 and communication interface 115.Institute
Stating slave computer 200 can also include: telecommunication circuit 240 and jtag interface 250；Wherein, each circuit in slave computer 200 can be with cloth
It sets on same fpga chip.
Preferably,
Direct fault location interface 114 is towards configuration bit stream, in conjunction with readback submodule 111, code stream overturning submodule 112 and reconfiguration
Submodule 113 is set, realizes single-particle inversion fault simulation.115 brow-down position machine 200 of communication interface realizes host computer 100 under
The interaction of data between the machine 200 of position；Wherein, interactive data include but are not limited to: frame address, read back frame data and overturning frame
The configuration datas such as data；And boundary scan command, readback configuration order and reconfigure the configuration orders such as order；And monitoring
The monitored results data of circuit 230.It wherein, specifically can be with base when communication interface 115 is that slave computer 200 carries out data interaction
It is communicated in jtag interface 250 with slave computer 200, realizes the friendship of the configuration order and configuration data between slave computer 200
Mutually；And the telecommunication circuit 240 based on serial ports configuration is communicated with slave computer 200, realizes the prison between slave computer 200
Control the interaction of result data.
In the present embodiment, specific:
Direct fault location interface 114, for receiving address element.
As previously mentioned, the address set of the target configuration bit stream can be pre-stored in host computer 100, and e.g., document 1
In.Direct fault location interface 114 can be from the address element read in address set from document 1, according to the frame in address element
Location and position offset, realize the single-particle inversion of fixed point on the configuration bit stream obtained.
Readback submodule 111 obtains readback frame for executing readback function according to the frame address from slave computer 200
Data.
In the present embodiment, readback submodule 111 can by the received frame address of direct fault location interface 114, and, boundary
Scan command and readback configuration order pass through communication interface 115 and are sent to jtag interface 250, execute readback function；Slave computer 200
After receiving frame address, boundary scan command and readback configuration order, corresponding read back frame data, slave computer can be determined
Read back frame data is sent to communication interface 115 by jtag interface 250 by 200, and in turn, readback submodule 111 is from slave computer 200
Middle acquisition read back frame data.
Code stream overturn submodule 112, for according to institute's rheme deviate, to the target configuration bit in the read back frame data into
The overturning of row logic obtains overturning frame data.
Submodule 113 is reconfigured, for reconfiguring function according to the frame address and overturning frame data execution, to slave computer
200 carry out single-particle inversion fault simulation.
In the present embodiment, overturning frame data that logic is overturn, boundary scan can be referred to by reconfiguring submodule 113
It enables, reconfigure order and frame address jtag interface 250 is sent to by communication interface 115, execution reconfigures function, realizes list
Particle overturns fault simulation.
As previously mentioned, TCL Script controlling module 110, is also used to obtain the monitored results data of monitoring circuit 230.Specifically
, the monitored results data for monitoring circuit 240 can be uploaded to TCL script by the communication interface 115 by telecommunication circuit 240
Control module 110.Preferably, the monitored results data received can be stored in upper by TCL Script controlling module 110
Machine 100 is local, e.g., is stored in the document 2 in host computer 100.
In the preferred embodiment of the present invention, the TCL Script controlling module 110 can be also used for starting TCL script
Running environment, and, to initialization system parameter；Wherein, the system parameter includes but are not limited to: FPGA device model, frame
The long, location index in JTAG chain and configuration order format etc..
In conjunction with above-described embodiment, referring to Fig. 2, a kind of FPGA single particle overturning fault simulation in the embodiment of the present invention is shown
The step flow chart of method.In the present embodiment, the FPGA single particle overturning failure simulation method can be real based on TCL script
Existing, the method can specifically include:
Step 301, start TCL script running environment.
In the present embodiment, integrated software conditions with micro matched with target FPGA device provides the running environment of TCL script,
The jtag interface that FPGA device can be accessed by TCL script, starts script running environment.
Step 302, Initialize installation.
In the present embodiment, before program operation, Initialize installation can be carried out to system parameter in the preparation stage.
Such as, initialization JTAG configures chain, initialize location index in JTAG chain of the model and frame length, FPGA device of FPGA device and
Configuration order format etc..Wherein, by Initialize installation, the compatible a variety of SRAM type FPGA devices of scheme of the present invention can be made
Part.
Step 303, an address element is chosen from the address set of target configuration bit stream.
In the present embodiment, each address element can include: frame address and position offset.
Step 304, it is deviated according to the frame address and position, carries out single-particle inversion fault simulation.
In the present embodiment, the specific implementation of single-particle inversion fault simulation can be such that executes according to the frame address
Readback function, obtains read back frame data from slave computer；It is deviated according to institute's rheme, the target in the read back frame data is configured
Position carries out logic overturning, obtains overturning frame data；Function is reconfigured according to the frame address and overturning frame data execution, to bottom
Machine carries out single-particle inversion fault simulation.
Step 305, circuit is run under various circumstances.
In the present embodiment, the circuit under test of slave computer is run under the single-particle inversion failure of simulation, circuit under test
Circuit is run fallback circuit under trouble-free normal mode of operation as a comparison；Wherein, circuit under test and contrast circuit are to use
The interested circuit design in family.
Step 306, the circuit operations conditions that circuit under test is run under the single-particle inversion failure environment of simulation are obtained, with
And the circuit operations conditions that contrast circuit is run in normal circumstances, determine the circuit operation shape of circuit under test and contrast circuit
The comparison result of state.
Step 307, whole address elements in the address set are successively traversed, determine the corresponding electricity of each address element
The comparison result of road operating status, and export.
In the present embodiment, all address elements of the step 303-306 into traversal address set can be repeated.Wherein,
Step 301-304 can control FPGA by operation TCL script and realize；Step 305 is realized on hardware circuit completely.
Step 308, process terminates, and host computer saves comparison result.
For embodiment of the method, since it is corresponding with Installation practice, so be described relatively simple, correlation
Place referring to Installation practice part explanation.
Various embodiments are described in a progressive manner in this explanation, the highlights of each of the examples are with its
The difference of his embodiment, the same or similar parts between the embodiments can be referred to each other.
In conclusion in embodiments of the present invention, directly controlling single-particle positioned at the TCL Script controlling module of host computer and turning over
The process for turning fault simulation, the auxiliary without lower computer hardware control circuit；The design of slave computer circuit is independent of target
The characteristic of FPGA device, it is unrelated with device architectures, without changing user's design when being transplanted to other FPGA devices.
Secondly, the control circuit function in the present invention is simple compared to existing single-particle inversion fault simulation system, electricity
Road small scale can be realized the circuit arrangement in slave computer using a fpga chip, reduce the hardware spending of system.
Again, compared with hardware control circuit, the development cycle of TCL shell script is short；Meanwhile host computer and slave computer it
Between communication transfer circuit operation data, it is no longer necessary to transmission flow control command reduces the time overhead of system.
In addition, in the present invention, flexible configuration can be carried out to sorts of systems parameter by TCL shell script, it is e.g., described
System parameter includes but are not limited to: FPGA device model, frame length and configuration order format and FPGA device are in JTAG chain
In location index etc., make to present invention can be suitably applied to a variety of SRAM type FPGA devices, and, each sub-circuit of slave computer circuit is equal
It is unrelated with the device architectures of FPGA device, it is ensured that the portability of system.
The above, optimal specific embodiment only of the invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.
The content that description in the present invention is not described in detail belongs to the well-known technique of professional and technical personnel in the field.
Claims (7)
1. a kind of FPGA single particle overturns fault simulation system characterized by comprising upper computer and lower computer；Wherein, described
Host computer, comprising: TCL Script controlling module；The slave computer, comprising: circuit under test, contrast circuit and monitoring circuit；
TCL Script controlling module, for choosing an address element from the address set of target configuration bit stream；And according to
Frame address and position offset in the address element, carry out single-particle inversion fault simulation；
Circuit under test, for being run under the single-particle inversion failure environment of simulation；
Contrast circuit, for running in normal circumstances；
Circuit is monitored, is monitored for the circuit operations conditions to circuit under test and contrast circuit；
TCL Script controlling module is also used to obtain the monitored results data of monitoring circuit；
Wherein, the TCL Script controlling module, comprising:
Readback submodule obtains read back frame data for executing readback function according to the frame address from slave computer；
Code stream overturns submodule, for deviating according to institute's rheme, carries out logic to the target configuration bit in the read back frame data
Overturning obtains overturning frame data；
Submodule is reconfigured, for reconfiguring function according to the frame address and overturning frame data execution, slave computer is carried out single
Particle overturns fault simulation.
2. system according to claim 1, which is characterized in that the TCL Script controlling module, further includes:
Direct fault location interface, for receiving address element；
Communication interface, for carrying out data interaction with slave computer；Wherein, interactive data include: frame address, read back frame data and
Frame data are overturn, and, boundary scan command, readback configuration order and reconfigure order；And the monitoring of the monitoring circuit
Result data.
3. system according to claim 2, which is characterized in that
The communication interface, for the boundary scan command, readback configuration order and frame address to be sent to slave computer
Jtag interface, and receive the read back frame data of jtag interface return；And by the boundary scan command, reconfigure order, frame
Address and overturning frame data are sent to the jtag interface of slave computer；And receive the institute reported by the telecommunication circuit of slave computer
State the monitored results data of monitoring circuit.
4. system according to claim 1, which is characterized in that the contrast circuit is the backup electricity of the circuit under test
Road.
5. system according to claim 1, which is characterized in that the TCL Script controlling module is also used to start TCL foot
This running environment, and, to initialization system parameter；Wherein, the system parameter includes: FPGA device model, frame length, in JTAG
Location index and configuration order format in chain.
6. a kind of FPGA single particle overturns failure simulation method characterized by comprising
An address element is chosen from the address set of target configuration bit stream；Wherein, the address element include: frame address and
Position offset；
It is deviated according to the frame address and position, carries out single-particle inversion fault simulation；
The circuit operations conditions that circuit under test is run under the single-particle inversion failure environment of simulation are obtained, and, contrast circuit
The circuit operations conditions run in normal circumstances determine the comparison knot of the circuit operations conditions of circuit under test and contrast circuit
Fruit；
Whole address elements in the address set are successively traversed, determine the corresponding circuit operations conditions of each address element
Comparison result, and export；
Wherein, described to be deviated according to the frame address and position, carry out single-particle inversion fault simulation, comprising:
Readback function is executed according to the frame address, read back frame data is obtained from slave computer；
It is deviated according to institute's rheme, logic overturning is carried out to the target configuration bit in the read back frame data, obtain overturning frame data；
Function is reconfigured according to the frame address and overturning frame data execution, single-particle inversion fault simulation is carried out to slave computer.
7. according to the method described in claim 6, it is characterized in that, FPGA single particle overturning failure simulation method is based on
TCL script is realized.
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| CN108388147B (en) * | 2018-02-12 | 2021-03-16 | 中南大学 | Real-time fault injection timing sequence resource optimization method and system thereof |
| CN109858195B (en) * | 2019-03-22 | 2022-11-08 | 中国科学院光电技术研究所 | Online simulation system for necessary bit single-particle upset fault on SRAM (static random Access memory) type FPGA (field programmable Gate array) |
| CN113886158B (en) * | 2021-09-28 | 2024-04-02 | 北京时代民芯科技有限公司 | Automatic FPGA fault injection test system and method |
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