TW202129722A - 半導體裝置的形成方法 - Google Patents

半導體裝置的形成方法 Download PDF

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TW202129722A
TW202129722A TW110101543A TW110101543A TW202129722A TW 202129722 A TW202129722 A TW 202129722A TW 110101543 A TW110101543 A TW 110101543A TW 110101543 A TW110101543 A TW 110101543A TW 202129722 A TW202129722 A TW 202129722A
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work function
layer
type
function layer
dielectric
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TW110101543A
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李欣怡
陳智城
洪正隆
張文
志安 徐
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台灣積體電路製造股份有限公司
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Abstract

一種形成方法，其包括：形成延伸到半導體基板中的隔離區域；以及使隔離區域凹入。在凹入的步驟之後，在介於隔離區域之間的半導體材料的部分高於隔離區域的頂表面突出，以形成半導體鰭片。前述方法進一步包括形成閘極堆疊物，其包括：形成閘極介電質於半導體鰭片的側壁以及頂表面上；以及沉積作為功函數層的氮化鈦層於第一閘極介電質之上。在介於大約300℃以及大約400℃之間的範圍的溫度下沉積氮化鈦層。形成源極區域以及汲極區域在閘極堆疊物的兩側上。

Description

半導體裝置的形成方法
本發明實施例是關於半導體裝置的形成方法，特別是關於能夠藉由調整沉積溫度來調整功函數的半導體裝置的形成方法。
金屬氧化物半導體(Metal-Oxide- Semiconductor，MOS)裝置一般包括金屬閘極，形成前述金屬閘極以解決習知多晶矽閘極中的多晶矽空乏效應(poly depletion effect)。當所施加的電場從靠近閘極介電質的閘極區域掃除載子時，產生多晶矽空乏效應，形成空乏層(depletion layers)。在n型摻雜的多晶矽層中，空乏層包括經離子化非移動的施體部位(ionized non-mobile donor sites)，其中在p型摻雜的多晶矽層中，空乏層包括經離子化非移動的受體部位(ionized non-mobile acceptor sites)。空乏效應導致有效閘極介電質厚度的增加，使得在半導體表面處產生反轉(inversion)層更為困難。藉由調整沉積溫度來調整功函數。
金屬閘極可以包括複數個層，從而可以滿足n型金屬氧化物半導體(n-type MOS，NMOS)裝置與p型金屬氧化物半導體(p-type MOS，PMOS)裝置的不同需求。金屬閘極的形成一般涉及到移除虛設閘極堆疊物以形成溝槽；沉積延伸到溝槽中的複數個金屬層；形成金屬區域以填充溝槽的剩餘部分；然後執行化學機械拋光(Chemical Mechanical Polish，CMP)製程，以移除金屬層的多餘部分。金屬層及金屬區域的剩餘部分形成金屬閘極。
一實施例是關於一種半導體裝置的形成方法。前述形成方法包括形成延伸到半導體基板中的隔離區域；以及使隔離區域凹入。其中，在凹入的步驟之後，在介於隔離區域之間的半導體材料的部分高於隔離區域的頂表面突出(protrudes higher)，以形成半導體鰭片。形成第一閘極堆疊物，其包括：形成第一閘極介電質於半導體鰭片的側壁以及頂表面上；以及沉積作為功函數層的第一氮化鈦(titanium nitride)層於第一閘極介電質之上。其中，第一氮化鈦層在介於大約300℃以及大約400℃之間的第一範圍的第一溫度下沉積。形成源極區域以及汲極區域。其中，源極區域以及汲極區域在第一閘極堆疊物的兩側上。
另一實施例是關於一種半導體裝置。前述半導體裝置包括第一電晶體及第二電晶體。第一電晶體包括第一半導體區域；在第一半導體區域之上的第一高k介電質；以及在第一高k介電質之上並與第一高k介電質接觸的第一功函數層。其中，第一功函數層具有第一功函數。第二電晶體包括第二半導體區域；在第二半導體區域之上並與第二半導體區域接觸的第二高k介電質；以及在第二高k介電質之上並與第二高k介電質接觸的第二功函數層。其中，第一功函數層及第二功函數層由相同的材料形成，且其中第二功函數層具有高於第一功函數的第二功函數。
又一實施例是關於一種半導體裝置。前述半導體裝置包括第一半導體區域、第一閘極堆疊物以及第一p型源極區域與第一p型汲極區域。第一閘極堆疊物在第一半導體區域上。第一閘極堆疊物包括：第一閘極介電質；以及在第一閘極介電質之上且與第一閘極介電質接觸的第一氮化鈦層。其中，第一氮化鈦層具有大於大約1.5的第一(200)/(111)訊號強度比值。第一p型源極區域與第一p型汲極區域在第一閘極堆疊物的兩側上。
以下的揭露內容提供許多不同的實施例或範例，以實施本揭露之不同部件(features)。以下敘述組件及排列方式的特定範例，以簡化本揭露。當然，這些特定的範例僅為示例，而非用以限定。舉例而言，若是本揭露書敘述了將一第一部件形成於一第二部件之上(over)或上(on)，即表示其可能包括上述第一部件與上述第二部件是直接接觸(in direct contact)的實施例，且亦可能包括了將其他部件形成於上述第一部件與上述第二部件之間，而使上述第一部件與第二部件可能未直接接觸的實施例。另外，本揭露在不同範例中可能重複使用相同的元件符號及/或標記。這些重複是為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或配置之間有特定的關係。
再者，在本文中所用的空間相關用詞，諸如「下層的(underlying)」、「之下(below)」、「較低的(lower)」、「上層的(overlying)」、「較高的(upper)」及類似的用詞，是為了便於描述圖式中一個元件(element)或部件與另一個(些)元件或部件之間的關係。除了在圖式中繪示的方位外，這些空間相關用詞意欲包括使用中或操作中的裝置之不同方位。設備可能被轉向不同方位(旋轉90度或其他方位)，則在本文中使用的空間相關用詞也可依此相同解釋。
根據一些實施例，提供了調節(tuning)電晶體中的金屬閘極的功函數的方法。根據一些實施例，描繪形成電晶體的中間階段。討論了一些實施例的一些變型。在全文中的各種視圖及說明性實施例，相似的元件符號用於指示相似的元件。根據一些實施例，鰭式場效電晶體(FinFET)的形成用作範例，以解釋本揭露的概念。也可以藉由應用本揭露的概念來形成其他類型的電晶體，諸如平面電晶體(planar transistors)、奈米片電晶體(nano-sheet transistors)、奈米線電晶體(nano-wire transistors)、全繞式閘極(Gate-All-Around，GAA)電晶體或其類似物。本文討論的實施例將提供範例，以使得能夠執行或使用本揭露之標的(subject matter)，且所屬技術領域中具有通常知識者將容易理解的是，可以進行修改，且同時保持在不同實施​​例的預期範圍內。儘管方法實施例可以被討論為以特定順序執行，但是其他方法實施例可以任何邏輯順序執行。
根據本揭露的一些實施例，為了調節不同電晶體的功函數，使用不同的溫度來形成電晶體的功函數層。較低的形成溫度導致第一PMOS電晶體的功函數較高，較高的形成溫度導致第二PMOS電晶體的功函數較低。
第1圖至第6圖、第7A圖、第7B圖、第8A圖、第8B圖、第9圖至第20圖、第21A圖以及第21B圖根據本揭露的一些實施例，描繪形成鰭式場效電晶體(FinFETs)的中間階段的剖面圖以及透視圖。這些圖式所示的製程也例示性地反映在第24圖所示的製程流程400中。
在第1圖中，提供了基板20。基板20可以是半導體基板，諸如塊材半導體基板(bulk semiconductor substrate)、絕緣體上覆半導體基板(Semiconductor-On-Insulator，SOI)或其類似物，半導體基板可以摻雜(例如，用p型或是n型摻質)或是未摻雜。半導體基板20可以是晶圓的一部分。一般而言，絕緣體上覆半導體基板是形成在絕緣層上的半導體材料層。絕緣層可以是舉例而言，埋入式氧化物(Buried Oxide，BOX)層、氧化矽(silicon oxide)層或其類似物。提供絕緣層在基板上，一般為提供在矽或是玻璃基板上。也可以使用諸如多層(multi-layered)基板或是漸變(gradient)基板的其他基板。在一些實施例中，半導體基板20的半導體材料可以包括矽(silicon)；鍺(germanium)；化合物半導體(compound semiconductor)，前述化合物半導體包括經碳摻雜的矽(carbon-doped silicon)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)及/或銻化銦(indium antimonide)；合金半導體(alloy semiconductor)，前述合金半導體包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、 GaInP及/或GaInAsP；或其組合。
進一步參照第1圖，形成井區22在基板20中。在第24圖所示的製程流程400中，對應的製程(respective process)繪示為製程402。根據本揭露的一些實施例，井區22是藉由植入p型摻質到基板20中而形成的p型井區，前述p型摻質可以是硼(boron)、銦(indium)或其類似物。根據本揭露的其他實施例，井區22是藉由植入n型摻質到基板20中而形成的n型井區，前述n型摻質可以是磷(phosphorus)、砷(arsenic)、銻(antimony)或其類似物。所形成的井區22可以延伸到基板20的頂表面。n型或p型摻質濃度可以等於或是小於1018cm-3，諸如在介於大約1017cm-3以及大約1018cm-3之間的範圍中。
參照第2圖，形成從基板20的頂表面延伸至基板20中的隔離區域。在下文中，隔離區域可替代地(alternatively)稱為淺溝槽隔離(Shallow Trench Isolation，STI)區域24。在第24圖所示的製程流程400中，對應的製程繪示為製程404。介於相鄰的STI區域24之間的基板20的一部分稱為半導體條(semiconductor strips)26。為了形成STI區域24，可以形成墊氧化層28以及硬遮罩層30在半導體基板20上，然後使墊氧化層28以及硬遮罩層30圖案化。墊氧化層28可以是由氧化矽所形成的薄膜。根據本揭露的一些實施例，墊氧化層28由熱氧化(thermal oxidation)製程形成，其中使半導體基板20的頂表面層氧化。墊氧化層28作為介於半導體基板20以及硬遮罩層30之間的黏合層。墊氧化層28還可以作為用於蝕刻硬遮罩層30的蝕刻停止層。根據本揭露的一些實施例，硬遮罩層30由氮化矽(silicon nitride)形成，舉例而言，使用低壓化學氣相沉積(Low-Pressure Chemical Vapor Deposition，LPCVD)。根據本揭露的其他實施例，硬遮罩層30藉由矽的熱氮化製程(thermal nitridation of silicon)、或是電漿輔助化學氣相沉積(Plasma-Enhanced Chemical Vapor Deposition，PECVD)形成。光阻(未顯示)形成在硬遮罩層30上，然後使光阻圖案化。然後，如第2圖所示，使用經圖案化的光阻作為蝕刻遮罩使硬遮罩層30圖案化，以形成硬遮罩層30。
接下來，將經圖案化的硬遮罩層30用作蝕刻遮罩，以蝕刻墊氧化層28以及基板20，接著以介電材料填充在基板20中所得到的溝槽。執行諸如化學機械拋光(Chemical Mechanical Polish，CMP)製程、或是機械研磨(Mechanical Grinding)製程的平坦化製程，以移除介電材料的多餘部分，且介電材料的剩餘部分為STI區域24。STI區域24可以包括襯層介電質(liner dielectric)(未示出)，前述襯層介電質可以是藉由熱氧化基板20的表面層所形成的熱氧化物。襯層介電質還可以是藉由使用諸如原子層沉積(Atomic Layer Deposition，ALD)、高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition，HDPCVD)、化學氣相沉積(Chemical Vapor Deposition，CVD)或其類似方法而沉積的氧化矽層、氮化矽層或其類似物。STI區域24還包括在襯層氧化物之上的介電材料，其中前述介電材料可以使用流動式化學氣相沉積(Flowable Chemical Vapor Deposition，FCVD)、旋轉塗佈法(spin-on coating)或其類似方法形成。根據一些實施例，在襯層介電質之上的介電材料可以包括氧化矽。
硬遮罩層30的頂表面以及STI區域24的頂表面可以實質上彼此齊平(level with)。半導體條26是介於相鄰的STI區域24之間。根據本揭露的一些實施例，半導體條26是原始基板20的一部分，且因此半導體條26的材料與基板20相同。根據本揭露的替代實施例，半導體條26是替換條(replacement strips)，前述替換條藉由蝕刻介於STI區域24之間的基板20的一部分以形成凹部，並執行磊晶以在凹部中重新生長其他半導體材料而形成。據此，半導體條26由與基板20不同的半導體材料形成。根據一些實施例，半導體條26由矽鍺(silicon germanium)、碳化矽(silicon carbon)、或是III-V族化合物半導體材料形成。
參照第3圖，使STI區域24凹入，使得半導體條26的頂部高於STI區域24的剩餘部分的頂表面24A突出，以形成突出鰭片36。在第24圖所示的製程流程400中，對應的製程繪示為製程406。蝕刻可以使用乾式蝕刻製程執行，其中舉例而言，將HF3 及NH3 用作蝕刻氣體。在蝕刻製程期間中，可能產生電漿。也可以包括氬氣(argon)。根據本揭露的替代實施例，使用濕式蝕刻製程來執行STI區域24的凹入。舉例而言，蝕刻化學品可以包括HF。
在上述實施例中，可以藉由任何合適的方法來圖案化鰭片。舉例而言，可以使用一或多種光微影(photolithography)製程來圖案化鰭片，前述光微影製程包括雙重圖案化(double-patterning)或多重圖案化(multi-patterning)製程。一般而言，雙重圖案化或多重圖案化製程將光微影製程及自對準(self-aligned)製程結合，從而允許產生舉例而言，間距(pitches)小於使用單次且直接光微影製程可獲得的間距的圖案。舉例而言，在一實施例中，形成犧牲層在基板之上，並使用光微影製程將犧牲層圖案化。使用自對準製程沿著經圖案化的犧牲層的側邊(alongside)形成間隔物。然後移除犧牲層，之後可以使用剩餘的間隔物或心軸(mandrels)來使鰭片圖案化。
參照第4圖，虛設閘極堆疊物38形成為在突出鰭片36的頂表面及側壁上延伸。在第24圖所示的製程流程400中，對應的製程繪示為製程408。虛設閘極堆疊物38可以包括虛設閘極介電質40及虛設閘極介電質40之上的虛設閘極電極42。虛設閘極電極42可以使用舉例而言，多晶矽來形成，且也可以使用其他材料。每個虛設閘極堆疊物38還可包括在虛設閘極電極42之上的一個(或複數個)硬遮罩層44 。硬遮罩層44可以由氮化矽、氧化矽、碳氮化矽(silicon carbo-nitride)或其之多層來形成。虛設閘極堆疊物38可跨越(cross over)單一個或複數個突出鰭片36及/或STI區域24之上。虛設閘極堆疊物38還具有與突出鰭片36的長度方向垂直的長度方向。
接下來，形成閘極間隔物46在虛設閘極堆疊物38的側壁上。在第24圖所示的製程流程400中，對應的製程亦繪示為製程408。根據本揭露的一些實施例，閘極間隔物46由諸如氮化矽、碳氮化矽或其類似物的介電材料來形成，且可以具有單層結構或包括複數個介電層的多層結構。
然後，執行蝕刻製程以蝕刻突出鰭片36的一部分，且虛設閘極堆疊物38及閘極間隔物46未覆蓋突出鰭片36的前述部分，從而得到第5圖所顯示的結構。在第24圖所示的製程流程400中，對應的製程繪示為製程410。凹入可以是非等向性的，並且因此保護直接位於虛設閘極堆疊物38及閘極間隔物46下層的(underlying)突出鰭片36的一部分，並且未蝕刻直接位於虛設閘極堆疊物38及閘極間隔物46下層的突出鰭片36的一部分。根據一些實施例，經凹入的半導體條26的頂表面可以低於STI區域24的頂表面24A。相應地形成凹部50。凹部50包括位於虛設閘極堆疊物38的兩側上的一部分以及在介於突出鰭片36的剩餘部分之間的一部分。
接下來，藉由在凹部50中選擇性地(selectively)生長(藉由磊晶)半導體材料來形成磊晶區域(源極/汲極區域)54，得到第6圖中的結構。在第24圖所示的製程流程400中，對應的製程繪示為製程412。根據所得的FinFET是p型FinFET(p-type FinFET)還是n型FinFET(n-type FinFET)，隨著磊晶的進行，可以原位(in-situ)摻雜p型或n型摻質。舉例而言，當所得的FinFET是p型FinFET時，可以生長矽鍺硼(silicon germanium boron，SiGeB)、矽硼(silicon boron，SiB)或其類似物。相反地，當所得的FinFET是n型FinFET時，可以生長矽磷(silicon phosphorous，SiP)、矽碳磷(silicon carbon phosphorous，SiCP)或其類似物。根據本揭露的替代實施例，磊晶區域54包括III-V族化合物半導體，諸如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、其組合或其多層。在以磊晶區域54填充凹部50之後，磊晶區域54的進一步磊晶生長導致磊晶區域54水平擴展(expand horizontally)，且可以形成刻面(facets)。磊晶區域54的進一步生長還可以引起相鄰的磊晶區域54彼此合併(merge)。可能產生空隙(voids)(氣隙(air gaps))56。
在磊晶製程之後，可以用p型或n型摻質進一步植入磊晶區域54，以形成源極區域及汲極區域，其也使用元件符號54表示。根據本揭露的替代實施例，在磊晶期間中當磊晶區域54是以p型或n型摻質原位摻雜，跳過植入步驟。
第7A圖顯示在形成接觸蝕刻停止層(Contact Etch Stop Layer，CESL)58及層間介電質(Inter-Layer Dielectric，ILD)60之後的結構的透視圖。在第24圖所示的製程流程400中，對應的製程繪示為製程414。CESL 58可以由氧化矽、氮化矽、碳氮化矽或其類似物來形成，且可以使用CVD、ALD或其類似製程來形成。ILD 60可以包括使用舉例而言FCVD、旋轉塗佈、CVD或其他種沉積方法形成的介電材料。ILD 60可以由含氧的(oxygen-containing)介電材料形成，前述含氧的介電材料可以是氧化矽類(silicon-oxide based)的材料，諸如氧化矽、磷矽酸鹽玻璃(Phospho-Silicate Glass，PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass ，BSG)、硼摻雜磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass，BPSG)或其類似物。可以執行諸如CMP製程或機械研磨製程的平坦化製程，以使ILD 60、虛設閘極堆疊物38及閘極間隔物46的頂表面彼此齊平。
第7B圖顯示在同一基板20上形成第一p型FinFET、第二p型FinFET及n型FinFET(在第21A圖中分別表示為FinFET 198、298及398)的中間結構的剖面圖。根據一些實施例，第一FinFET、第二FinFET及第三FinFET分別形成在裝置區域100P、200P及300N中，其中字母「P」代表「p型電晶體」；且字母「N」代表「n型電晶體」。根據一些實施例，將在裝置區域100P及200P中形成的FinFET具有功函數層，且前述功函數層具有不同功函數。第一FinFET、第二FinFET及第三FinFET中的任一個的剖面圖可以對應於從包含在第7A圖中的線段7B-7B的垂直平面獲得的剖面圖。
為了區分在第一FinFET、第二FinFET及第三FinFET中的部件，可以使用在第7A圖中相應部件的元件符號加上數字100來表示在第7B圖中的第一p型FinFET中的部件，且可以使用在第7A圖中相應部件的元件符號加上數字200來表示在第7B圖中的第二p型FinFET中的部件。類似地，可以使用在第7A圖中相應部件的元件符號加上數字300來表示在第7B圖中的n型FinFET中的部件。舉例而言，在第7B圖中的源極/汲極區域154、254及354對應於第7A圖中的源極/汲極區域54，且在第7B圖中的閘極間隔物146、246及346對應於第7A圖中的閘極間隔物46。源極/汲極區域154及254摻雜有p型摻質或一些p型摻質(impurity or impurities)。源極/汲極區域354摻雜有n型摻質或一些n型摻質。在第一FinFET、第二FinFET及第三FinFET中的對應部件可以在共同的製程中形成，且在隨後的段落中將討論一些示例性製程，或者，可以在單獨的製程中形成。
在形成第7A圖及第7B圖所顯示的結構之後，如第8A圖、第8B圖及第9至20圖所示，將第7B圖中的虛設閘極堆疊物138、238及338替換為金屬閘極及替換閘極介電質(replacement gate dielectrics)。在這些圖式中，顯示STI區域24的頂表面24A，且半導體鰭片124’、224’及324’高於對應的相鄰STI區域24的頂表面24A突出。
為了形成替換閘極，先移除如第7A圖及第7B圖所顯示的硬遮罩層144、244及344；虛設閘極電極142、242及342；以及虛設閘極介電質140、240及340，從而形成如第8A圖所示的溝槽59。在第24圖所示的製程流程400中，對應的製程繪示為製程416。第8A圖中的溝槽59對應於在第8B圖中的裝置區域100P中的溝槽159、裝置區域200P中的溝槽259以及裝置區域300N中的溝槽359。突出鰭片124’、224’及324’的頂表面及側壁分別暴露於溝槽159、259及359。
接下來，參照第9圖，形成閘極介電質162、262及362，前述閘極介電質162、262及362分別延伸到溝槽159、259及359中。在第24圖所示的製程流程400中，對應的製程繪示為製程418。根據本揭露的一些實施例，閘極介電質162、262及362分別包括界面層(Interfacial Layers，IL) 164、264及364，前述IL 164、264及364分別形成在突出鰭片124’、224’及324’的經暴露表面上。IL 164、264及364中的每一個可包括諸如氧化矽層的氧化物層，前述氧化物層藉由突出鰭片124’、224’及324’的熱氧化、化學氧化製程或沉積製程來形成。閘極介電質162、262及362還可以分別包括分別對應IL 164、264及364的高介電常數(高k，high-k)介電層166、266及366。每個高k介電層166、266及366可以由高k介電材料形成，諸如氧化鉿(hafnium oxide)、氧化鑭(lanthanum oxide)、氧化鋁(aluminum oxide)、氧化鋯(zirconium oxide)或其類似物。高k介電材料的介電常數(k值) (dielectric constant)(k-value)高於3.9，且可以高於大約7.0。高k介電層166、266及366的厚度可以在介於大約5 Å及大約30 Å之間的範圍內。高k介電層166、266及366形成為共形層(conformal layers)，且分別在突出鰭片124’、224’及324’的側壁上及閘極間隔物146、246及346的頂表面及側壁上延伸。根據本揭露的一些實施例，使用ALD或CVD形成高k介電層166、266及366。高k介電層166、266及366可以是相同介電層的一部分，其使用相同的材料且具有相同的厚度來同時形成，或者分別地使用不同的材料及/或不同的厚度來形成。
第9圖進一步顯示第一p型功函數層67的形成，前述第一p型功函數層67包括p型功函數層(或一部分)167、267及367。p型功函數層167、267及367可以在共同的沉積製程或單獨的沉積製程中形成。在第24圖所示的製程流程400中，對應的製程繪示為製程420。p型功函數層67可以由TiN、TiSiN、包括TiSiN層及在TiSiN之上的TiN層的複合層或其類似物形成，或者p型功函數層67可以包括TiN、TiSiN、包括TiSiN層及在TiSiN之上的TiN層的複合層或其類似物。形成方法包括諸如原子層沉積(ALD)的共形沉積方法。p型功函數層67的厚度T1可以在大約10 Å至大約50 Å之間的範圍內。
根據一些實施例，p型功函數層67是使用ALD形成的TiN層。前驅物可以包括TiCl4 及NH3 。對應的ALD製程包括複數個循環，每個循環包括傳輸(conducting)TiCl4 ；吹入(purging)TiCl4 ；傳導NH3 ；然後吹入NH3 。可替代地，p型功函數層67是使用ALD形成的TiSiN層。前驅物可以包括TiCl4 、SiH4 及NH3 。對應的ALD製程包括複數個循環，每個循環包括傳輸TiCl4 ；吹入TiCl4 ；傳輸NH3 ；吹入NH3 ；傳輸SiH4 ；吹入SiH4 ；傳輸NH3 ；然後吹入NH3 。舉例而言，在每個循環中，TiCl4可以傳輸大約0.1秒至大約30分鐘，且流率(flow rate)在介於大約100每分鐘標準立方公分(standard cubic centimeter per minute，sccm)至大約9,000sccm之間。NH3 可以傳輸大約0.1秒至大約30分鐘，且流率在介於大約100 sccm至大約9,000 sccm之間。腔室壓力可以在介於大約0.5托(torr)至大約40托之間的範圍內。
在p型功函數層67的沉積期間，晶圓10的溫度處於相對較高的溫度，使得p型功函數層67的功函數相對較低。實驗表明的是，功函數層的功函數受到功函數層的沉積溫度的影響。舉例而言，第22圖顯示TiN的功函數與沉積溫度的關係。在T1處形成了三個樣品TiN層，T1是測試溫度中最高的，且對應的功函數為大約4.87 eV。當沉積溫度降低到較低的溫度T2、T3及T4，且其中T2＞T3＞T4時，對應的樣品TiN層的功函數分別增加到大約4.896 eV、大約4.9 eV及大約4.921 eV。據此，當沉積溫度從T1降低到T4時，功函數增加大約53mV。因此，藉由選擇適當的沉積溫度，可以調整功函數層的功函數。據此，還可以藉由調整功函數層的沉積溫度來調整電晶體的閾值電壓(threshold voltages)。根據一些實施例，在裝置區域100P中的FinFET具有在較高溫度下沉積的功函數層，以具有相對較低的功函數，且在裝置區域200P中的FinFET具有在較低溫度下沉積的功函數層，從而具有相對較高的功函數。結果，在裝置區域100P及200P中的FinFET的閾值電壓可以彼此不同。
根據一些實施例，在功函數層67的沉積中時的晶圓10的溫度相對較高，舉例而言，在介於大約400℃至大約500℃之間的範圍內，且可以在介於大約425℃至大約475℃之間的範圍內。如第22圖所示，這導致功函數層67的功函數相對較低。對在450℃下沉積的樣品TiN功函數層執行X光繞射(X-Ray Diffraction，XRD)分析。所得圖式(plot)在第23圖中顯示為線段202。Y軸表示訊號強度(signal intensity)，X軸是X光在樣品上的入射角。樣本具有特徵峰(111)及(200)。如線段202所示，當在450℃下沉積TiN樣品時，(200)/(111)訊號強度比值，也就是(200)訊號強度與(111)訊號強度的比值為大約0.95。作為比較，在350℃下沉積的TiN樣品的(200)/(111)訊號強度比值為1.64。據此，功函數層的(200)/(111)訊號強度比值可以用於識別功函數層的形成溫度。
當在功函數層67的沉積中時的晶圓10的溫度在介於大約400℃至大約500℃之間的範圍內時，對應的(200)/(111)訊號強度比值可以在介於大約0.9至大約0.99之間的範圍內。功函數層67的功函數可以在介於大約4.85 eV及大約4.88 eV之間的範圍內。此外，由於相對較高的沉積溫度，較少的殘餘氯(由於使用TiCl4 作為前驅物)留在所得的功函數層67(及最終的功函數層167)中。舉例而言，p型功函數層67或167中的氯原子百分比可以低於大約0.11%，且可以在介於大約0.01%至大約0.1%之間的範圍內。舉例而言，可以藉由使用X光光電子能譜儀(X-ray Photoelectron Spectroscopy，XPS)來確定氯(及其他元素)的原子百分比。
第9圖進一步顯示第一硬遮罩168、268及368的形成，前述第一硬遮罩168、268及368以共同的沉積製程形成。在第24圖所示的製程流程400中，對應的製程繪示為製程422。根據一些實施例，硬遮罩168、268及368是單層硬遮罩或多層硬遮罩。根據一些實施例，硬遮罩168、268及368包括金屬氧化物層，諸如氧化鋁層；以及在金屬氧化物層之上的金屬氮化物層，諸如氮化鈦層。可以使用諸如ALD、CVD或其類似製程的共形沉積方法來形成硬遮罩168、268及368。
第10圖分別顯示在裝置區域100P及300N中的蝕刻遮罩165及365的形成及圖案化。蝕刻遮罩165及365可以形成為延伸到裝置區域100P、200P及300N中，然後在圖案化製程中從裝置區域200P移除。結果是，暴露硬遮罩268，且蝕刻遮罩165及365分別覆蓋硬遮罩168及368。根據一些實施例，蝕刻遮罩165包括底部抗反射塗層(Bottom Anti-Reflective Coating，BARC)165A及光阻劑165B，且蝕刻遮罩365包括BARC 365A及光阻劑365B。在範例形成製程中，BARC 165A及365A以及光阻劑165B及365B的形成包括形成毯覆式BARC層，以及在毯覆式BARC層上形成光阻劑。使用微影(lithography)製程對光阻劑進行圖案化，以從裝置區域200P移除一部分。然後，使用光阻劑165B及365B作為蝕刻遮罩來蝕刻毯覆式BARC層。如第11圖所示，蝕刻毯覆式BARC層之後，移除光阻劑165B及365B，並暴露BARC 165A及365A。
根據替代實施例，蝕刻遮罩165及365由單一光阻劑或三層形成，前述三層包括底層、在底層之上的中間層以及在中間層之上的頂層。根據又一替代實施例，蝕刻遮罩165及365是單一光阻劑的一部分。可以在第11圖所顯示的製程之前或期間中，移除剩餘的光阻劑165B及365B。
接下來，在蝕刻製程中，移除硬遮罩268及p型功函數層267。在第24圖所示的製程流程400中，對應的製程繪示為製程424。在第11圖中顯示所得的結構。硬遮罩168及368由BARC 165A及365A保護，且將在蝕刻製程之後保留。在蝕刻硬遮罩268之後，暴露p型功函數層267。
然後，在蝕刻製程中移除經暴露的p型功函數層267，且在蝕刻製程之後，暴露高k介電層266。根據本揭露的一些實施例，藉由濕式蝕刻製程執行p型功函數層267的蝕刻。根據一些實施例，用於蝕刻硬遮罩268的相同濕式蝕刻化學品可以用於蝕刻p型功函數層267。可以理解的是，可以使用相同的蝕刻遮罩165及365(BARC 165A及365A)，來執行硬遮罩268及p型功函數層267之兩者的移除。雖然硬遮罩168及368不用作用於蝕刻p型功函數層267的蝕刻遮罩，但是具有控制p型功函數層267的蝕刻寬度的功能，以防止在橫向方向(lateral direction)上過度蝕刻(over-etching)p型功函數層267。
接下來，移除BARC 165A及365A。根據一些實施例，藉由灰化(ashing)，或者使用包括氫氣(hydrogen，H2 )及氮氣(nitrogen，N2 )的蝕刻氣體且在不施加偏置電壓(bias voltage)的情況下，來移除BARC 165A及365A。所得的結構在第12圖中顯示。相應地暴露硬遮罩168及368。然後，移除剩餘的硬遮罩168及368。在第24圖所示的製程流程400中，對應的製程繪示為製程426。蝕刻化學品可以包括氫氧化銨(ammonium hydroxide)、過氧化氫(hydrogen peroxide)、鹽酸(hydrochloric acid)、碳酸(carbonic acid)或其類似物。
第13圖至第16圖顯示第二p型功函數層72的沉積及圖案化，其中第二p型功函數層72分別在電晶體區域，亦即裝置區域100P、200P及300N中包括功函數層(或部分)172、272及372。參照第13圖，p型功函數層72(包括功函數層172、272及372)舉例而言是以相同的沉積製程形成。在第24圖所示的製程流程400中，對應的製程繪示為製程428。p型功函數層172、272及372的材料可以選自p型功函數層167的候選材料的相同群組，且可以與p型功函數層167的材料相同或不同。p型功函數層172、272及372的厚度T2可以在大約10 Å至大約50 Å的範圍內。根據一些實施例，p型功函數層67及72由諸如鈦及氮的相同元素形成，或包括諸如鈦及氮的相同的元素，且在p型功函數層67中的元素的原子百分比可以與在p型功函數層72中的相應元素的原子百分比相同(或不同)。
根據一些實施例，使用以TiCl4 及NH3 作為前驅物之ALD形成p型功函數層67。功函數層72的沉積溫度低於功函數層67的沉積溫度。功函數層72的沉積溫度與功函數層67的沉積溫度的差值可以大於大約50 ℃，或在介於大約50 ℃至大約150℃之間的範圍內，以便在功函數層67及72的功函數之間有充分的區隔(adequately distinction)。功函數層72的沉積溫度不能太高或太低。如果沉積溫度太低，舉例而言，低於大約300℃，則在所獲得的功函數層272中可能殘留過多的氯，這對所獲得的電晶體的性能產生不利影響。如果沉積溫度太高，舉例而言，高於大約400℃，則會降低提高功函數的效果，從而不利於使用單獨的製程及不同的溫度形成功函數層67及72的目的。根據一些實施例，功函數層72的沉積溫度在介於大約300℃及大約400℃之間的範圍內，且可以在介於大約325℃及大約375℃之間的範圍內。功函數層72的功函數可以在介於大約4.88 eV及大約4.51 eV之間的範圍內。功函數層72的功函數WF72 及功函數層67的功函數WF67 具有差值(WF72 -WF67 )，前述差值大於大約20 mV，且前述差值可在介於大約20 mV及大約70 mV之間。
由於用於沉積功函數層72的相對較低的沉積溫度，相較於在功函數層67中，在所得的功函數層72中留下更多的殘留氯(由於使用TiCl4 作為前驅物)。舉例而言，在功函數層72中的氯原子百分比可以高於大約1%，且可以在介於大約1%至大約4.5%之間的範圍內。
對在350℃下沉積的樣品TiN功函數層進行XRD分析。所得圖式在第23圖中顯示為線段204。如線段204所示，當在350℃沉積TiN樣品時，(200)/(111)訊號強度比值為大約1.64。根據一些實施例，當在功函數層72的沉積中時的晶圓10的溫度在介於大約300℃至大約400℃之間的範圍內時，對應的(200)/(111)訊號強度比值大於大約1.4，且可以在介於大約1.4至大約1.8之間的範圍內。此外，功函數層72的(200)/(111)訊號強度比值以一差值大於功函數層67的(200)/(111)訊號強度比值，前述差值可大於大約0.35，且可以在介於大約0.35至大約0.7之間的範圍內。訊號峰值及(200)/(111)訊號強度比值可以在最終產品中找到，舉例而言，已經封裝的相應晶片。
第14圖進一步顯示在共同沉積製程中形成的第二硬遮罩174、274及374的形成。在第24圖所示的製程流程400中，對應的製程繪示為製程430。硬遮罩174、274及374的材料、結構及形成方法可以選自硬遮罩168、268及368(第9圖)的候選材料、結後及形成方法的相同群組。硬遮罩174、274及374的厚度可以在介於大約5 Å及大約50 Å之間的範圍內。
第14圖還分別顯示在裝置區域100P及200P中的蝕刻遮罩176及276的形成及圖案化。蝕刻遮罩176及276可以形成為延伸到裝置區域100P、200P及300N中，然後，在圖案化製程中從裝置區域300N移除。蝕刻遮罩176可包括BARC 176A及在BARC 176A之上的光阻劑176B。蝕刻遮罩276可以包括BARC 276A及在BARC 276A之上的光阻劑276B。結果是，暴露硬遮罩374，且蝕刻遮罩176及276分別覆蓋硬遮罩174及274。蝕刻遮罩176及276的材料、結構及形成製程可以類似於蝕刻遮罩165及365(第10圖)的相應材料、結構及形成製程，在此不再贅述。
在隨後的製程中，可以移除光阻劑176B及276B。BARC 176A及276A用作蝕刻遮罩，以蝕刻及移除硬遮罩374及p型功函數層372及367。在第24圖所示的製程流程400中，對應的製程繪示為製程432。在第15圖中顯示所得的結構。硬遮罩374及p型功函數層372及367的蝕刻可以分別類似於硬遮罩268及p型功函數層267(第10圖)的蝕刻，且不討論細節。
如先前的圖案化製程所示，以與蝕刻p型功函數層372(第15圖)相同的製程，而不是以蝕刻p型功函數層267(第11圖)的相同製程，來蝕刻p型功函數層367。這具有將高k介電層366暴露於蝕刻化學品一次而不是暴露於蝕刻化學品兩次的有利特徵。這將減少在蝕刻製程中的高k介電層366中的損耗。如第15圖所示，因此暴露高k介電層366。接下來，使用與移除BARC 165A及365A(第11圖)相似的方法來移除BARC 176A及276A。類似於移除硬遮罩168及368(第11圖)，亦移除硬遮罩174及274。在第24圖所示的製程流程400中，對應的製程繪示為製程434。在第16圖中顯示所得的結構。
第17圖顯示n型功函數層82的形成，前述n型功函數層82包括分別在裝置區域100P、200P及300N中的n型功函數層(部分)182、282及382。在第24圖所示的製程流程400中，對應的製程繪示為製程436。根據一些實施例，功函數層82可以包括鋁基(aluminum-based)層，前述鋁基層可以舉例而言，由TiAl、TiAlN、TiAlC、TaAlN或TaAlC形成，或包括TiAl、TiAlN、TiAlC、TaAlN或TaAlC。功函數層82具有小於4.5eV的功函數。
接下來，根據一些實施例，形成複數個金屬層，以分別填充溝槽159、259及359，且在第18圖及第19圖中顯示所得的結構。在第24圖所示的製程流程400中，對應的製程繪示為製程438。參照第18圖，黏膠層84(包括可以同時形成的黏膠層(部分)184、284及384)形成為分別延伸到裝置區域100P、200P及300N中的共形層。根據一些實施例，黏膠層184、284及384包括可以使用諸如ALD、CVD或其類似製程的共形沉積方法來沉積的TiN、TaN或其類似物。根據一些範例實施例，黏膠層184、284及384包括使用ALD沉積的TiN，其中以TiCl4 及NH3 作為前驅物。沉積溫度高於p型功函數層72的沉積溫度，舉例而言，以介於大約50℃至大約150℃之間的溫度差值。根據一些實施例，黏膠層184、284及384的沉積溫度在介於大約400℃至大約500℃之間的範圍內。在高溫下沉積黏膠層184、284及384具有降低所獲得的黏膠層184、284及384中的氯原子百分比的有利特徵。舉例而言，氯原子百分比可以低於大約0.1%，或者可以在介於大約0.01%至大約0.1%之間的範圍內。作為比較，在p型功函數層272中的氯原子百分比可大於大約1%，且可以是在介於大約1%至大約4.5%之間的範圍內。
第19圖顯示金屬填充(filling-metal)區域86(包括金屬填充區域186、286及386)的形成。根據一些實施例，金屬填充區域186、286及386由可以使用ALD、CVD或其類似沉積方法來沉積的鎢(tungsten)、鈷(cobalt)或其類似物形成。根據替代實施例，黏膠層184、284及384完全填充相應的溝槽，且不形成金屬填充區域。
在完全填充溝槽之後，執行平坦化製程以移除複數個層的多餘部分，從而產生如第20圖所顯示的閘極堆疊物190、290及390。閘極堆疊物190、290及390分別包括閘極電極188、288及388。
第21A圖根據一些實施例，顯示自對準硬遮罩191、291及391的形成。形成製程可以包括執行蝕刻製程，以使閘極堆疊物190、290及390凹入，從而在閘極間隔物146、246及346之間形成凹部。然後，以介電材料填充凹部，接著執行平坦化製程，以移除介電材料的多餘部分。硬遮罩191、291及391可以由氮化矽、氮氧化矽(silicon oxy-nitride)、氧碳氮化矽(silicon oxy-carbo-nitride)或其類似物來形成。另外，形成源極/汲極接觸插塞196、296及396以及矽化物(silicide)區域195、295及395，以分別電性連接到源極/汲極區域154、254及354。形成閘極接觸插塞194、294及394，以分別電性連接到閘極電極188、288及388。因此，分別在裝置區域100P、200P及300N中形成p型FinFET 198及298以及n型FinFET 398。
FinFET 198的閘極電極188包括p型功函數層167、p型功函數層172及n型功函數層182。功函數層167的功函數主要影響(dominates)閘極電極188的功函數。FinFET 298的閘極電極288包括p型功函數層272及n型功函數層282。功函數層272的功函數主要影響閘極電極288的功函數。FinFET 398包括的閘極電極388包括n型功函數層382。因此，FinFET 198具有第一p型功函數WF1，且FinFET 298具有高於功函數WF1的第二p型功函數WF2。FinFET 398具有n型功函數，n型功函數小於功函數WF1及WF2之兩者。
第21B圖顯示FinFET 98的透視圖，FinFET 98可以表示如第21A圖所顯示的FinFET 198、298及398中的任一個。亦顯示閘極接觸插塞94(在第21A圖中表示為閘極接觸插塞194、294及394)；源極/汲極矽化物區域95(代表源極/汲極矽化物區域195、295及395)；以及源極/汲極接觸插塞96(代表源極/汲極接觸插塞196、296及396)。
在上面討論的範例實施例中，由於p型功函數層67的相對較高的沉積溫度，而在沉積p型功函數層72及n型功函數層82之前，沉積具有較低的功函數的p型功函數層67。根據其他實施例，可以採用任何其他順序來重新排列功函數層67、72及82的形成順序。
本揭露的實施例具有一些有利部件。藉由降低p型功函數層的沉積溫度，可以實現更高的功函數。藉由區分p型功函數層的沉積溫度，即使p型功函數層由相同材料形成，也可以對於不同的電晶體實現不同的功函數。
根據本揭露的一些實施例，一種方法包括形成延伸到半導體基板中的隔離區域；以及使隔離區域凹入。其中，在凹入的步驟之後，在介於隔離區域之間的半導體材料的一部分高於隔離區域的頂表面突出，以形成半導體鰭片。形成第一閘極堆疊物，其包括：形成第一閘極介電質在半導體鰭片的側壁及頂表面上；以及沉積作為功函數層的第一氮化鈦層在第一閘極介電質之上。其中，第一氮化鈦層在介於大約300℃以及大約400℃之間的第一範圍的第一溫度下沉積。形成源極區域與汲極區域。其中，源極區域及汲極區域位於第一閘極堆疊物的兩側上。在一實施例中，第一氮化鈦層是使用氯化鈦(titanium chloride，TiCl4 )及氨(ammonia，NH3 )作為前驅物而以原子層沉積來形成。在一實施例中，前述方法進一步包括沉積n型功函數層在第一氮化鈦層之上；以及沉積第二氮化鈦層在n型功函數層之上。其中，第二氮化鈦層在高於第一溫度的第二溫度下沉積。在一實施例中，前述方法進一步包括沉積第二氮化鈦層，其中第一氮化鈦層接觸第二氮化鈦層。其中，第二氮化鈦層在高於第一溫度的第二溫度下沉積。在一實施例中，第二溫度以大於大約50℃的差值高於第一溫度。在一實施例中，第二溫度在介於大約400℃及大約500℃之間的第二範圍內。在一實施例中，源極區域與汲極區域形成為p型區域。
根據本揭露的一些實施例，一種裝置包括第一電晶體及第二電晶體。第一電晶體包括第一半導體區域；在第一半導體區域之上的第一高k介電質；以及在第一高k介電質之上並與第一高k介電質接觸的第一功函數層。其中，第一功函數層具有第一功函數。第二電晶體包括第二半導體區域；在第二半導體區域之上並與第二半導體區域接觸的第二高k介電質；以及在第二高k介電質之上並與第二高k介電質接觸的第二功函數層。其中，第一功函數層及第二功函數層由相同的材料形成，且其中第二功函數層具有高於第一功函數的第二功函數。在一實施例中，第一電晶體及第二電晶體是p型電晶體，且第二功函數大於第一功函數為大於(more than)大約20 mV以上。在一實施例中，第一電晶體及第二電晶體是p型電晶體，且第一功函數層及第二功函數層包括氮化鈦。在一實施例中，前述裝置進一步包括在第一功函數層之上並與第一功函數層接觸的第三功函數層。其中，第三功函數層及第二功函數層由相同的材料形成，且其中第三功函數層具有第二功函數。在一實施例中，第一功函數層具有大於大約1.5的第一(200)/(111)訊號強度比值。在一實施例中，第二功函數層具有小於第一(200)/(111)訊號強度比值的第二(200)/(111)訊號強度比值。在一實施例中，前述裝置進一步包括在第二電晶體中且在第二功函數層之上的黏膠層。其中，黏膠層與第二功函數層由相同的材料形成，且其中膠層具有等於第二(200)/(111)訊號強度比值的第三(200)/(111)訊號強度比值。
根據本揭露的一些實施例，一種裝置包括：第一半導體區域、第一閘極堆疊物以及第一p型源極區域與第一p型汲極區域。第一閘極堆疊物在第一半導體區域上。第一閘極堆疊物包括：第一閘極介電質；以及在第一閘極介電質之上且與第一閘極介電質接觸的第一氮化鈦層。其中，第一氮化鈦層具有大於大約1.5的第一(200)/(111)訊號強度比值。第一p型源極區域與第一p型汲極區域在第一閘極堆疊物的兩側上。在一實施例中，前述裝置進一步包括在第一氮化鈦層之上的第二氮化鈦層。其中，第二氮化鈦層具有與第一(200)/(111)訊號強度比值不同的第二(200)/（(111)訊號強度比值。在一實施例中，第二(200)/(111)訊號強度比小於第一(200)/(111)訊號強度比。在一實施例中，前述裝置進一步包括在介於第一氮化鈦層及第二氮化鈦層之間的n型功函數層。在一實施例中，第一氮化鈦層與第二氮化鈦層物理上地接觸。在一實施例中，前述裝置進一步包括第二半導體區域、第二閘極堆疊物以及第二p型源極區域與第二p型汲極區域。第二閘極堆疊物於第二半導體區域上。第二閘極堆疊物包括第二閘極介電質；以及在第二閘極介電質之上且與第二閘極介電質接觸的第二氮化鈦層。第二氮化鈦層具有小於第一(200)/(111)訊號強度比值的第二(200)/(111)訊號強度比值。第二p型源極區域與第二p型汲極區域在第二閘極堆疊物的兩側上。
前述內文概述了各種實施例的部件，使所屬技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。所屬技術領域中具有通常知識者應可理解的是，他們可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在本文中介紹的各種實施例相同之優點。所屬技術領域中具有通常知識者也應理解的是，這些等效的構型並未背離本揭露的發明精神與範圍，且在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
10:晶圓 100P,200P,300N:裝置區域 124’,224’,324’,36:鰭片 138,238,338,38:虛設閘極堆疊物 140,240,340,40:虛設閘極介電質 142,242,342,42:虛設閘極電極 144,244,30,344,44:硬遮罩層 146,246,346,46:閘極間隔物 154,254,354:源極區域/汲極區域 159,259,359,59:溝槽 162,262,362:閘極介電質 164,264,364:界面層 165,176,276,365:蝕刻遮罩 165A,176A,276A,365A:底部抗反射塗層 165B,176B,276B,365B:光阻劑 166,266,366:高介電常數介電層 167,172,182,267,272,282,367,372,382,67,72,82:功函數層 168,174,191,268,274,291,368,374,391:硬遮罩 184,284,384,84:黏膠層 186,286,386,86:金屬填充區域 188,288,388:閘極電極 190,290,390:閘極堆疊物 194,294,394,94:閘極接觸插塞 195,295,395,95:矽化物區域 196,296,396,96:源極/汲極接觸插塞 198,298,398,98:鰭式場效電晶體 20:基板 202,204:線段 22:井區 24:淺溝槽隔離區域 24A:頂表面 26:半導體條 28:墊氧化層 400:製造流程 402,404,406,408,410,412,414,416,418,420,422,424,426,428,430,432,434,436, 438:製程 50:凹部 54:磊晶區域 56:孔隙 58:接觸蝕刻停止層 60:層間介電質 T1,T2:厚度
根據以下的詳細說明並配合所附圖式閱讀，能夠最好的理解本揭露的所有態樣。應注意的是，根據本產業的標準作業，各種部件並未必按照比例繪製。事實上，可能任意的放大或縮小各種部件的尺寸，以做清楚的說明。 第1圖至第6圖、第7A圖、第7B圖、第8A圖、第8B圖、第9圖至第20圖、第21A圖以及第21B圖是根據本揭露的一些實施例，描繪在形成鰭式場效電晶體(Fin Field-Effect Transistors，FinFETs)的中間階段的透視圖及剖面圖。 第22圖是根據本揭露的一些實施例，描繪氮化鈦層的功函數與形成溫度的函數關係。 第23圖是根據本揭露的一些實施例，描繪在350℃及450℃下形成的兩個氮化鈦層的X光繞射(X-Ray Diffraction，XRD)結果。 第24圖根據一些實施例，描繪用於形成FinFET的製程流程。
400:製造流程
402,404,406,408,410,412,414,416,418,420,422,424,426,428,430,432,434,436,438:製程

Claims (1)

  1. 一種半導體裝置的形成方法，其包括： 形成延伸到一半導體基板中的複數個隔離區域； 使該複數個隔離區域凹入，其中在該凹入的步驟之後，在介於該複數個隔離區域之間的一半導體材料的一部分高於該複數個隔離區域的頂表面突出(protrudes higher)，以形成一半導體鰭片； 形成一第一閘極堆疊物，其包括： 形成一第一閘極介電質於該半導體鰭片的複數個側壁以及一頂表面上；以及 沉積作為一功函數層的一第一氮化鈦(titanium nitride)層於該第一閘極介電質之上，其中該第一氮化鈦層在介於大約300℃以及大約400℃之間的一第一範圍的一第一溫度下沉積；以及 形成一源極區域以及一汲極區域，其中該源極區域以及該汲極區域在該第一閘極堆疊物的兩側上。
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Publication number Priority date Publication date Assignee Title
TWI850650B (zh) 2021-08-12 2024-08-01 台灣積體電路製造股份有限公司 記憶體單元結構及其製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8536660B2 (en) * 2008-03-12 2013-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid process for forming metal gates of MOS devices
US8637390B2 (en) * 2010-06-04 2014-01-28 Applied Materials, Inc. Metal gate structures and methods for forming thereof
US9012319B1 (en) * 2013-11-01 2015-04-21 Globalfoundries Inc. Methods of forming gate structures with multiple work functions and the resulting products
US9978601B2 (en) * 2015-10-20 2018-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for pre-deposition treatment of a work-function metal layer
US9748145B1 (en) * 2016-02-29 2017-08-29 Globalfoundries Inc. Semiconductor devices with varying threshold voltage and fabrication methods thereof
US10497811B2 (en) * 2016-12-15 2019-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET structures and methods of forming the same
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