TW202125728A - 半導體元件封裝結構 - Google Patents

半導體元件封裝結構 Download PDF

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TW202125728A
TW202125728A TW108148392A TW108148392A TW202125728A TW 202125728 A TW202125728 A TW 202125728A TW 108148392 A TW108148392 A TW 108148392A TW 108148392 A TW108148392 A TW 108148392A TW 202125728 A TW202125728 A TW 202125728A
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Taiwan
Prior art keywords
bonding
bonding pad
pad pattern
semiconductor device
pads
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TW108148392A
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English (en)
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TWI808292B (zh
Inventor
林明哲
郭忠幸
陳慧玲
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聯華電子股份有限公司
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Application filed by 聯華電子股份有限公司 filed Critical 聯華電子股份有限公司
Priority to TW108148392A priority Critical patent/TWI808292B/zh
Priority to US16/781,937 priority patent/US11450633B2/en
Priority to CN202010104189.4A priority patent/CN113130428A/zh
Priority to EP20164116.4A priority patent/EP3846201A1/en
Publication of TW202125728A publication Critical patent/TW202125728A/zh
Priority to US17/880,691 priority patent/US20220384376A1/en
Application granted granted Critical
Publication of TWI808292B publication Critical patent/TWI808292B/zh

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/381—Pitch distance

Abstract

一種半導體元件封裝結構，包括第一基板、第二基板以及接合層。接合層將所述第一基板與所述第二基板接合。所述接合層包含形成在介電層中的內部接合墊圖案與外部接合墊圖案，所述外部接合墊圖案圍繞所述內部接合墊圖案。所述外部接合墊圖案的第一接合墊密度是大於所述內部接合墊圖案的第二接合墊密度。

Description

半導體元件封裝結構
本發明是關於半導體製造技術，且是關於半導體元件封裝結構。
通過半導體製造技術，積體電路可以在一個基板上製造。積體電路的功能隨著整體電子產品的研發的需求也趨向更複雜的設計。積體電路所包含的元件以及內連線結構也因此大量增加。由於一個基板可用於製造形成元件的面積有其限制。因應積體電路所需要增大其功能而涉及的大量元件，積體電路的製造例如已往基板垂直的方向堆疊形成更多的元件與線路。
再進一步的製造研發，其可以將積體電路分為兩個部分，分別在其對應的基板上製造完成。基板的上層會形成有接合層(bonding layer)。接合層包含介電層以及在介電層中設置有多個接合墊。接合墊是與其基板上所形成的電路連接，用以接合到另一個基板上的電路。兩個基板的接合層的多個接合墊的位置是相同。在後續的封裝製程中，兩個基板是相對，且通過接合層的接合可以構成整體的積體電路。
在上述的封裝過程中，如果兩個基板之間的接合力不足時，在後續電路切割成單個的晶片(die)時，可能因為接合力不足造成接合墊的接觸不良或是甚至分離，其結果導致積體電路的製造失敗，降低製造的良率(yield)。兩個基板之間的接合力有需要提升來至少減少後續切割晶片時造成電路的損壞。
本發明提出在基板上的接合墊圖案的規劃，可以提升接合層的接合程度，減少兩個基板之間的接合層分離的現象。
在一實施例，本發明提出一種半導體元件封裝結構，包括第一基板、第二基板以及接合層。接合層將所述第一基板與所述第二基板接合。所述接合層包含形成在介電層中的內部接合墊圖案與外部接合墊圖案，所述外部接合墊圖案圍繞所述內部接合墊圖案。所述外部接合墊圖案的第一接合墊密度是大於所述內部接合墊圖案的第二接合墊密度。
在一實施例，對於所述的半導體元件封裝結構，所述外部接合墊圖案中的相鄰兩個接合墊之間在所述第一接合墊密度下有第一距離，所述內部接合墊圖案中的相鄰兩個接合墊之間在所述第二接合墊密度下有第二距離，其中所述第一距離小於所述第二距離。
在一實施例，對於所述的半導體元件封裝結構，所述第一基板包含第一接合層且所述第二基板包含第二接合層，其中所述第一接合層與所述第二接合層接合在一起成為所述接合層。
在一實施例，對於所述的半導體元件封裝結構，所述外部接合墊圖案是虛置圖案，所述內部接合墊圖案是連接於所述第一基板中的電路與所述第二基板中的電路之間。
在一實施例，對於所述的半導體元件封裝結構，所述內部接合墊圖案的多個接合墊是均勻分佈在正方形區域、長方形區域或是圓形區域中。
在一實施例，對於所述的半導體元件封裝結構，所述外部接合墊圖案的多個接合墊是分佈成至少一墊圈，圍繞所述內部接合墊圖案。
在一實施例，對於所述的半導體元件封裝結構，所述外部接合墊圖案的多個接合墊包含多個墊圈，圍繞所述內部接合墊圖案。
在一實施例，對於所述的半導體元件封裝結構，所述多個墊圈的所述多個接合墊，在水平方向或是垂直方向對準。
在一實施例，對於所述的半導體元件封裝結構，所述多個墊圈的所述多個接合墊，在水平方向或是垂直方向是交替位移。
在一實施例，對於所述的半導體元件封裝結構，所述外部接合墊圖案的多個接合墊是分佈成一個墊圈。
在一實施例，對於所述的半導體元件封裝結構，所述外部接合墊圖案是直角四邊形，所述直角四邊形的每一邊包含沿著所述邊的多個接合墊列。
在一實施例，對於所述的半導體元件封裝結構，在該些接合墊列的每一個中的多個接合墊的分佈是相同。
在一實施例，對於所述的半導體元件封裝結構，在該些接合墊列的每一個中的多個接合墊的分佈，對於相鄰兩個該接合墊列是不同。
在一實施例，對於所述的半導體元件封裝結構，所述外部接合墊圖案的多個接合墊是分佈成至少兩個墊圈，其中所述至少兩個墊圈的內圈的墊分佈包含不連續區域，在所述直角四邊形的角落處。
在一實施例，對於所述的半導體元件封裝結構，所述至少兩個墊圈的多個接合墊在所述直角四邊形的每一邊 是分佈成至少兩個接合墊列，所述至少兩個接合墊列的每一個的長度是等於對應邊的長度。
本發明是關於半導體的封裝技術。通過在基板上的接合墊圖案的規劃，本發明可以提升兩個基板之間的接合層的接合程度。本發明可以減少例如切個晶片時造成兩個基板之間的接合層分離的現象。
以下舉一些實施例來說明本發明，但是本發明不限於所舉的多個實施例。所舉的多個實施例之間也允許有是可能結合。
對於基板與基本板之間的接合技術有多種方式，其中例如是介電層對介電層(dielectric -to-dielectric)的接合技術。介電層對介電層接合的機制是利用介電層與介電層之間在相對較低溫下進行或化學反應，使介電材料接合。而介電層之間的接合墊(Bonding Pad)會接觸達到電性連接。其後會再進行較高溫的回火(annealing)過程，加強接合的強度，而接合墊之間的接合程度回進一步達到良好接合。
圖1A到圖1C是二個基板接合機制示意圖。參閱圖1A，載兩個基板50、50A中分別完成所預定的電路結構，在基板50、50A的上端例如也會分別形成內連線層52、52A，其也可以例如是重新分佈層(redistribution layer，RDL)，可以將連接端點較平均地重新分佈，使兩個內連線層52、52A之間預定要電性連接的端點配置在相同位置，以使在兩個基板50、50A的兩個電路連接成一個整體的電路。針對要連接的端點會通接合層(bonding layer)54、54A形成對應連接的端點的多個接合墊56、56A。接合層54、54A的材料包含介電層，而多個接合墊56、56A以相同的圖案分別形成在兩個基板50、50A的接合層54、54A中。接合墊56、56A例如是銅，或是所選擇的金屬或是導電材料。本發明的接合墊56、56A不限於特定材料。兩個基板50、50A上的電路結構是分別製造完成。
參閱圖1B，將兩個基板50、50A的接合層54、54A相互對準後進行第一階段的介電材料接合，例如是在相對較低溫下進行介電材料之間化學反應，使介電材料接合。屬於兩個基板50、50A的對應接合墊56、56A會接觸連接。介電材料一般例如是氧化矽，但是不限於此。介電材料又例如也可以是氮氧化矽、氮化矽、或是其相似材料等。
參閱圖1C，將兩個基板50、50A的接合層54、54A之間通過第一階段的接合後，再將行較高溫的回火 (annealing)得到接合層54B。回火的作用再強化介電材料之間的接合力，也同時促使接合墊56、56A有更良好的接合。
圖2是在基板上的接合墊圖案的示意圖。以基板50上的 接合層為例，本發明觀察到在接合層54中的多個接合墊56的密度即使經由內連線層52的重新規劃，其密度相對地仍是稀疏的分佈。這是因為兩個電路之間實際要連接的端點數量不多。於此，一個端點可能會配置多個接合墊56，但是其密度仍是相對地小，其可能會造成兩個基板之間的接合力不足，導致兩個基板在切割機片時分離。本發明至少探究(look into)在接合層54的接合墊56的問題後提出關於在接合層54中的接合墊的規劃。
圖3到圖6是依據本發明多個實施例，在基板上的接合墊圖案的示意圖。
參閱圖3，以下以基板50的接合層54為例來描述接合墊圖案(pattern)的規劃。在基板50A的接合層54A的接合墊圖案是與基板50的接合層54的接合墊圖案相同，其例如經由圖1A到圖1C的接合達到兩個電路的整體連接。
在一實施例，接合層54包含內部區域60與外部區域62。外部區域62是環繞內部區域60。內部區域60的幾何形狀例如是長方形或是正方形，但是不限於此。內部區域60的幾何形狀有可以是圓形或是其它圖形。以下以長方形或是正方形為例來說明。
在內部區域60中有多個接合墊56，其均勻分佈構成內部接合墊圖案57。在外部區域62中有多個接合墊58a、58b構成外部接合墊圖案58。接合層54包含介電層，其包圍內部的接合墊56與外部的接合墊58a、58b。內部接合墊圖案57是用於電路的實際接合。外部接合墊圖案58是虛置的接合墊58a、58b，位於在接合層54的外部區域62，可以增強接合後的接合力。
在切割晶片時，切割的外力會沿著切割線(scribe line)施加，此接合層54的邊緣會受到切割力的施加，容易破損。虛置的外部接合墊圖案58可以承受切割力。如此，外部接合墊圖案58的接合墊密度要大於內部接合墊圖案57的接合墊密度。
關於接合墊密度的大小，在一實施例，外部接合墊圖案58中的相鄰兩個接合墊之間，在預定的第一接合墊密度下有一距離d2。在內部接合墊圖案57中的相鄰兩個接合墊之間，在預定的第二接合墊密度下有一距離d1。高密度的距離d2是小於低密度的距離d1。由於外部接合墊圖案58的接合墊58a、58b的接合墊密度大，其機械強度以及結合力是較大，能夠承受切割外力。兩個接合層54、54A較不易分離。
在內部接合墊圖案57的多個接合墊56的分佈可以依照電路接合的實際需要來規劃。在外部接合墊圖案58的多個接合墊58a、58b採用較大密度來規劃。在一實施例，在外部接合墊圖案58的多個接合墊58a、58b例如以兩墊圈(pad ring)為例。多個接合墊58a構成內墊圈，接合墊58b構成外墊圈。基於內部區域60的幾何形狀，接合墊所構成的內墊圈或外墊圈可以是連續，也可以包含不連續的局部區域，例如是內墊圈在角落處會有局部區域是不連續。另外，內墊圈的接合墊58a與外墊圈的接合墊58b可以是交替移位的規劃。在垂直方向，例如長方形的寬邊的方向，接合墊58a與接合墊58b是左右移位。類似地，在水平方向，例如長方形的長邊的方向，接合墊58a與接合墊58b是上下移位。如此，內墊圈接合墊58a可以阻檔由外墊圈的接合墊58b之間通過的應力。在一實施例，外部接合墊圖案58的多個接合墊58a、58b不需要與內部接合墊圖案57的多個接合墊56的延伸方向對準。然而本發明不限於圖3的外部接合墊圖案58的多個接合墊58a、58b的規劃。
參閱圖4，在一實施例，外部接合墊圖案58的多個接合墊58a、58b所構成內墊圈的接合墊58a與外墊圈的接合墊58b也是可以對準。
在一實施例，以長方形的寬邊與長邊來看，其邊上可以疊置多個列(row)的接合墊58a、58b，其例如二列的接合墊58a、58b，但是如後面會描述，本發明不限於此規劃。圖4的接合墊58a、58b的規劃僅是所取用來說明的實施例。在一實施例，在角落(corner)的接合墊58a、58b也可以不需要設置。接合墊58a、58b的幾何形狀也例如可以是長方形多角形或是圓形，而不限於正方形。在一實施例，例如圖4A，接合墊58a、58b的幾何形狀是以圓形為例。在一實施例，例如圖4B，接合墊58a、58b的幾何形狀是以六角形為例。
在一實施例，參閱圖5，外部接合墊圖案58的多個接合墊也例如可以是單墊圈的規劃，其也能夠增強在周邊的接合力強度，不限於圖3、4的二個墊圈規劃。
在一實施例，參閱圖6，外部接合墊圖案58的多個接合墊也例如可以是多墊圈的規劃，例如是三圈的規劃，不限於圖3、4的二圈規劃。在三墊圈的接合墊58a、58b、58c是以圖3或圖4的二個墊圈規劃為基礎再加上接合墊58c的一個墊圈。
也就是說，外部接合墊圖案58的接合墊的規劃可以依照實際需要改變，以較大的接合墊密度來增強在周邊區域的機械強度以及接合力，減少在切割時兩個基板的分離。
圖7是依據本發明多個實施例，檢視接合層的接合品質示意圖。參閱圖7，本發明針對接合層54B的兩個接合層54、54A 之間接合力進行測試。例如使用刀工具64變化施加的外力，觀察可以使兩個接合層54、54A剝離施力大小來判斷接合力的大小。從測試資料來看，當周邊的密度增加時，產生剝離的應力也增加，且是大於線性的一次方(one-order)的增加率。也就是，本發明的外部接合墊圖案58的設置，可以有效防止兩個接合層54、54A的剝離。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
50、50A:基板 52、52A:內連線層 54、54A:接合層 56、56A:接合墊 57:內部接合墊圖案 58 :外部接合墊圖案 58a、58b、58c:接合墊 60:內部區域 62:外部區域 64:刀工具 d1、d2:距離
圖1A到圖1C是二個基板接合機制示意圖。 圖2是在基板上的接合墊圖案的示意圖。 圖3到圖6是依據本發明多個實施例，在基板上的接合墊圖案的示意圖。 圖7是依據本發明多個實施例，檢視接合層的接合品質示意圖。
54:接合層
56:接合墊
57:內部接合墊圖案
58:外部接合墊圖案
58a、58b:接合墊
60:內部區域
62:外部區域
d1、d2:距離

Claims (15)

  1. 一種半導體元件封裝結構，包括: 第一基板; 第二基板; 以及 接合層，將所述第一基板與所述第二基板接合，其中所述接合層包含形成在介電層中的內部接合墊圖案與外部接合墊圖案，所述外部接合墊圖案圍繞所述內部接合墊圖案， 其中所述外部接合墊圖案的第一接合墊密度是大於所述內部接合墊圖案的第二接合墊密度。
  2. 如申請專利範圍第1項所述的半導體元件封裝結構，其中所述外部接合墊圖案中的相鄰兩個接合墊之間在所述第一接合墊密度下有第一距離，所述內部接合墊圖案中的相鄰兩個接合墊之間在所述第二接合墊密度下有第二距離，其中所述第一距離小於所述第二距離。
  3. 如申請專利範圍第1項所述的半導體元件封裝結構，其中所述第一基板包含第一接合層且所述第二基板包含第二接合層，其中所述第一接合層與所述第二接合層接合在一起成為所述接合層。
  4. 如申請專利範圍第1項所述的半導體元件封裝結構，其中所述外部接合墊圖案是虛置圖案，所述內部接合墊圖案是連接於所述第一基板中的電路與所述第二基板中的電路之間。
  5. 如申請專利範圍第1項所述的半導體元件封裝結構，其中所述內部接合墊圖案的多個接合墊是均勻分佈在正方形區域、長方形區域或是圓形區域中。
  6. 如申請專利範圍第1項所述的半導體元件封裝結構，其中所述外部接合墊圖案的多個接合墊是分佈成至少一墊圈，圍繞所述內部接合墊圖案。
  7. 如申請專利範圍第1項所述的半導體元件封裝結構，其中所述外部接合墊圖案的多個接合墊包含多個墊圈，圍繞所述內部接合墊圖案。
  8. 如申請專利範圍第7項所述的半導體元件封裝結構，其中所述多個墊圈的所述多個接合墊，在水平方向或是垂直方向對準。
  9. 如申請專利範圍第7項所述的半導體元件封裝結構，其中所述多個墊圈的所述多個接合墊，在水平方向或是垂直方向是交替位移。
  10. 如申請專利範圍第1項所述的半導體元件封裝結構，其中所述外部接合墊圖案的多個接合墊是分佈成一個墊圈。
  11. 如申請專利範圍第1項所述的半導體元件封裝結構，其中所述外部接合墊圖案是直角四邊形，所述直角四邊形的每一邊包含沿著所述邊的多個接合墊列。
  12. 如申請專利範圍第11項所述的半導體元件封裝結構，其中在該些接合墊列的每一個中的多個接合墊的分佈是相同。
  13. 如申請專利範圍第11項所述的半導體元件封裝結構，其中在該些接合墊列的每一個中的多個接合墊的分佈，對於相鄰兩個該接合墊列是不同。
  14. 如申請專利範圍第11項所述的半導體元件封裝結構，其中所述外部接合墊圖案的多個接合墊是分佈成至少兩個墊圈，其中所述至少兩個墊圈的內圈的墊分佈包含不連續區域，在所述直角四邊形的角落處。
  15. 如申請專利範圍第11項所述的半導體元件封裝結構，其中所述至少兩個墊圈的多個接合墊在所述直角四邊形的每一邊 是分佈成至少兩個接合墊列，所述至少兩個接合墊列的每一個的長度是等於對應邊的長度。
TW108148392A 2019-12-30 2019-12-30 半導體元件封裝結構 TWI808292B (zh)

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CN202010104189.4A CN113130428A (zh) 2019-12-30 2020-02-20 半导体元件封装结构
EP20164116.4A EP3846201A1 (en) 2019-12-30 2020-03-19 Package structure of semiconductor device
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