TW202124251A - 矽穿孔及再分佈層 - Google Patents

矽穿孔及再分佈層 Download PDF

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TW202124251A
TW202124251A TW109133239A TW109133239A TW202124251A TW 202124251 A TW202124251 A TW 202124251A TW 109133239 A TW109133239 A TW 109133239A TW 109133239 A TW109133239 A TW 109133239A TW 202124251 A TW202124251 A TW 202124251A
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tsv
rdl
copper
metal
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湯瑪士 韋德納
泰瑞莎 伯特霍爾德
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德商艾克斯法柏半導體鑄造股份有限公司
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Abstract

本案提供一種半導體裝置，包括：具有前表面與後表面的矽基板；位於此前表面上的金屬層；從此後表面延伸穿過此矽基板至此前表面的矽穿孔(TSV)，其中此TSV在一末端連接至此金屬層；及再分佈層(RDL)，其中此RDL嵌入在此矽基板中。

Description

矽穿孔及再分佈層
本發明關於諸如互補式金氧半導體(CMOS)裝置及/或微機電系統(MEMS)裝置的半導體裝置中的矽穿孔(TSV)與再分佈層(RDL)。
矽穿孔(TSV)可用於提供連接從晶圓的背部至CMOS裝置，此賦予3D連接結構。為了製造TSV，穿過矽基板的孔洞被形成且被銅保角地沉積。銅再分佈層(RDL)含有金屬線與接合墊結構，其賦予連接性(例如，焊接凸塊)及功能性。
關於此處理的技術問題為在晶圓表面上的TSV與RDL的暴露銅。在晶圓表面的回蝕刻(濕式蝕刻)期間，需要過度蝕刻以避免金屬線之間的銅殘留，否則其會造成短路。過度蝕刻顯著地影響金屬線的形狀(縮減)，其會負面地影響裝置效能。
US 2011/05840敘述一種使用雙重鑲嵌型處理流程所形成的改善TSV與RDL連接結構。使用此處理，RDL銅嵌入在晶圓的背部上的氧化層中。隨後使用化學機械研磨(CMP)以替代移除過量銅及提供平坦晶圓表面。
本發明的態樣提供如隨附申請專利範圍中所述的半導體裝置與形成半導體裝置的方法。
現在將參照隨附圖式說明僅作為範例之本發明的優選實施例。
本發明的實施例提供諸如互補式金氧半導體(CMOS)裝置及/或微機電系統(MEMS)裝置的半導體裝置(例如，在CMOS/MEMS處理中製造的影像感測器、微處理器、微控制器、壓力感測器、IR感測器、等等)，包含矽穿孔(TSV)與再分佈層(RDL)，矽穿孔(TSV)與再分佈層(RDL)嵌入在裝置的矽基板中。半導體裝置可包含使用鑲嵌型處理形成的複數個此種TSV。與習知技術相反，本文所述的實施例將RDL埋藏在塊體矽中。
藉由將RDL(例如，金屬墊與金屬線)與TSV嵌入在基板中(而不是在基板上的介電層中)，以從後續的處理步驟及尤其從後續的濕式蝕刻保護RDL與TSV。濕式蝕刻可用以移除RDL中的金屬線與金屬墊之間的過剩銅。在已知的RDL形成處理中，此濕式蝕刻趨向縮減金屬線，其會負面地影響裝置效能(例如，由於增加的電阻或不一致的電阻)。藉由提供RDL與溝槽中的TSV的連接墊直接地形成在矽基板中，金屬線承受到濕式蝕刻的較少縮減/損害。將RDL嵌入在矽基板中也可提供更加平面/平滑的外表面，其可提供較佳品質的膜及防止基板上的起泡(blistering)。
在參照圖式之前，吾人首先以一般術語而不參照元件符號來描述圖式的半導體裝置。本文所述的半導體裝置包含金屬層，其可被稱為第一金屬層或金屬1(注意，並未在圖式中標示為1)。半導體裝置可包含形成在CMOS/MEMS後段製程(BEOL)處理中的複數個金屬層，其中金屬1是第一(最底下)金屬層(接下來為金屬2、金屬3、等等)。金屬層可連接至矽基板的前表面上的摻雜區以形成電晶體、二極體及半導體裝置的其他半導體結構。TSV從矽基板的後表面穿過前表面延伸至金屬層，以容許從矽基板的背部連接至金屬層。TSV具有在矽基板的後表面上的連接墊(也被稱為「金屬墊」或「再分佈墊」)。TSV的此連接墊也嵌入在矽基板中且可被當作RDL的一部分。
TSV包含孔洞，此孔洞具有在孔洞的側壁上與底部上的沉積銅層。較佳地， TSV未被銅所大量填充，其可節省花費與由於TSV的大深寬比之處理時間。RDL的金屬線與金屬墊可在如在TSV中提供銅層的相同步驟中被填充，例如使用電化學沉積(ECD)。TSV與RDL可包含阻障層(例如，氮化鈦)，其塗佈孔洞與溝槽的壁及將銅層與矽基板分隔開。
半導體裝置可進一步包含覆蓋RDL的保護層。保護層可包含一或多個鈍化層(例如，氧化物及/或氮化矽)。保護層可提供環境保護及電氣隔離予RDL和TSV。可以化學氣相沉積(CVD)或其他塗佈處理完成最終銅封裝以形成保護層。
也在此描述形成CMOS裝置的方法的實施例。RDL與TSV皆被使用鑲嵌型處理直接地提供在矽基板中。此方法包含以下步驟：提供具有前表面與後表面的矽基板及在前表面上形成金屬層。此方法進一步包含形成TSV及形成RDL之步驟，TSV從後表面延伸穿過矽基板至前表面，其中TSV在一末端連接至金屬層，及其中RDL嵌入在矽基板中。
形成TSV的步驟可包含在矽基板中蝕刻溝槽用以形成TSV的連接墊。較佳地，使用活性離子蝕刻(RIE)。RIE是一種乾式蝕刻，其具有與濕式蝕刻不同的特性。RIE蝕刻可具有提供非常異向性蝕刻基板的優點。可在第一處理步驟中使用RIE蝕刻用於金屬線與金屬墊的RDL溝槽。孔洞可接著被蝕刻(例如，使用RIE)穿過矽基板至金屬層(例如，金屬1)。孔洞通常延伸穿過形成用於TSV的連接墊之溝槽的中央。
此方法進一步包含在用於連接墊的溝槽中與孔洞中沉積銅層以形成TSV之步驟，其中銅層不完全地填充孔洞。在沉積銅層的步驟之前，可沉積阻障層，阻障層塗佈孔洞的壁。銅晶種層可被提供在阻障層上用於銅層的後續沉積。
此方法可進一步包含執行濕式蝕刻以移除過量銅之步驟。濕式蝕刻可用以移除RDL的金屬線與金屬墊之間的阻障層/晶種層上的銅以防止短路。
可提供保護層，其覆蓋RDL及保護包括RDL與TSV的基板的後表面。可藉由沉積一或多個鈍化層來提供保護層。例如，氮化矽層可沉積在後表面上。
第1圖顯示根據實施例之CMOS/MEMS裝置2的圖解剖面。裝置2包含具有前表面6與後表面8的矽基板4。TSV 10從後表面8延伸穿過基板4至前表面6。TSV 10包含在後表面8處的連接墊12及延伸穿過連接墊12而至CMOS裝置2的第一金屬層16的孔洞14。裝置2進一步包含RDL的金屬線18(包含多個層，如之後所述)。金屬線18嵌入在基板4中。TSV 10 (包括連接墊12)與金屬線18皆包含鄰接矽基板4的氧化物層20(例如，藉由氧化矽基板4而形成)、覆蓋氧化物層20的氮化鈦阻障層、及為ECD銅層的銅層24。銅層24填充RDL的金屬線18與TSV 10的連接墊12，但不完全地填充TSV 10的孔洞14。由於孔洞14的大深寬比，銅層24僅塗佈孔洞14的壁。實質上平坦的保護層26(例如，氮化矽層)覆蓋後表面8，包括金屬線18與TSV 10。
第2a至2d圖繪示形成諸如第1圖中繪示的裝置之CMOS/MEMS裝置2的方法的一些步驟。圖式中類似或對應特徵已被給定相同的元件符號以易於理解且不欲作為限制。
第2a圖顯示具有前表面6與後表面8的基板4的剖面，第一金屬層16在基板4之上。已使用RIE蝕刻矽基板的後表面8以形成適用於TSV的連接墊的溝槽28與用於RDL的金屬線的溝槽30。皆使用相同遮罩在相同處理步驟中形成溝槽28與30。TSV 10的連接墊12也可當作RDL的一部分。
第2b圖顯示已經被RIE蝕刻從後表面8穿過基板4的TSV的孔洞14，其穿過前表面6而至第一金屬層16。孔洞14被蝕刻穿過用於連接墊的溝槽28的中央。
第2c圖顯示已被沉積在矽基板4上的氧化物層20。氧化物層20是鈍化層，其提供某些保護與電氣隔離予基板4的下方矽。在孔洞14的末端處已經從金屬層16移除沉積的氧化物，以促進最終TSV與金屬層16之間的電氣連接。
第2d圖顯示沉積在氧化物層20上的氮化鈦阻障層22與沉積在阻障層上的ECD銅層24以形成TSV 10與RDL的金屬線18。已經完成阻障層22與晶種層(未示出)的回蝕刻(濕式蝕刻)以移除連接墊12與金屬線18之間中及RDL的其他金屬線與金屬墊(未示出)之間中的阻障層與晶種層。在一般鑲嵌處理後，已知在金屬沉積之後使用CMP以使表面平滑。使用取代CMP的濕式蝕刻會具有如已經存在/標準存在的處理步驟(例如，在CMOS與MEMS處理中)之迅速取得的優點，及因此不需要將晶圓移動至不同製造處理。在基板4中的RIE蝕刻溝槽提供對於執行濕式蝕刻的ECD銅的充足保護。在濕式蝕刻之後，矽基板的後表面8，包括暴露ECD銅層24與暴露氧化物層20，為相對地平坦及具有在1 µm至1.5 µm範圍中的表面粗糙度，其會使得任何潛在乾燥膜後處理變得更加可靠。
第2e圖顯示藉由在基板4的後表面8上沉積鈍化層堆疊26提供保護層28之後之具有RDL金屬線18與TSV 10的完成CMOS/MEMS裝置2。
儘管已在上方說明本發明的特定實施例，將領會到本發明可以不同於特定實施例所述的方式實行。上方的說明書意為示例性的，而非限制性。在不背離之後所述之申請專利範圍的範疇，熟習本領域者可修改所說明的實施例會是顯而易見。
本說明書中所揭示或繪示的各特徵可併入本發明中，無論是單獨的或以與本文所揭示或繪示的任何其他特徵之任何適當組合。
2:裝置 4:基板 6:前表面 8:後表面 10:矽穿孔(TSV) 12:連接墊 14:孔洞 16:第一金屬層 18:金屬線 20:氧化物層 22:阻障層 24:銅層 26:保護層 28:溝槽 30:溝槽
第1圖顯示具有嵌入在矽基板中的RDL與TSV的CMOS裝置的剖面的示意圖；
第2a圖顯示形成具有改善功能性與連接性的半導體裝置的方法的一步驟，其中RIE(活性離子蝕刻)溝槽已經形成在基板中用於RDL與後續的TSV；
第2b圖顯示形成CMOS裝置的方法的一後續步驟，其中用於TSV的孔洞已經被蝕刻穿過基板；
第2c圖顯示形成CMOS裝置的方法的一後續步驟，其中氧化層已經被沉積及建構；
第2d圖顯示形成CMOS裝置的方法的一後續步驟，其中阻障層與銅層已經被沉積；及
第2e圖顯示形成CMOS裝置的方法的最終步驟，其中保護層已經被提供在RDL與TSV銅上方。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
2:裝置
4:基板
6:前表面
8:後表面
10:矽穿孔(TSV)
12:連接墊
14:孔洞
16:第一金屬層
18:金屬線
20:氧化物層
22:阻障層
24:銅層
26:保護層

Claims (16)

  1. 一種半導體裝置，包含： 一矽基板，具有一前表面與一後表面； 一金屬層，位於該前表面上； 一矽穿孔(TSV)，從該後表面延伸穿過該矽基板至該前表面，其中該TSV在一末端連接至該金屬層；及 一再分佈層(RDL)，其中該RDL嵌入在該矽基板中。
  2. 如請求項1所述之半導體裝置，其中該TSV包含一孔洞與一銅層，及其中該銅層不完全地填充該孔洞。
  3. 如請求項1所述之半導體裝置，其中該TSV包含一層堆疊，該層堆疊至少包含一隔離層與一阻障層，該阻障層塗佈該孔洞的該等壁且將該銅層與該矽基板分隔開。
  4. 如請求項1所述之半導體裝置，進一步包含一保護層，該保護層覆蓋該RDL與TSV中的銅。
  5. 如請求項4所述之半導體裝置，其中該保護層包含至少一鈍化層。
  6. 如請求項1所述之半導體裝置，其中該半導體裝置是一互補式金氧半導體(CMOS)裝置及/或一微機電系統(MEMS)裝置。
  7. 一種形成一半導體裝置的方法，該方法包含以下步驟： 提供具有一前表面與一後表面的一矽基板； 在該前表面上形成一金屬層； 形成一矽穿孔(TSV)，該矽穿孔(TSV)從該後表面延伸穿過該矽基板至該前表面，其中該TSV在一末端連接至該金屬層；及 形成一再分佈層(RDL)，其中該RDL嵌入在該矽基板中。
  8. 如請求項7所述之方法，其中形成該TSV的該步驟包含： 在該矽基板中蝕刻一溝槽，用於形成該TSV的一連接墊； 蝕刻一孔洞穿過該矽基板至該金屬層； 在該溝槽與該孔洞中沉積一銅層以形成該TSV，其中該銅層不完全地填充該孔洞。
  9. 如請求項8所述之方法，其中形成該TSV的該步驟進一步包含：在沉積該銅層的該步驟之前，提供一層堆疊，該層堆疊至少包含一隔離層與一阻障層，該阻障層塗佈該孔洞的該等壁。
  10. 如請求項8所述之方法，其中沉積銅的該步驟包含執行電化學沉積(ECD)。
  11. 如請求項7所述之方法，其中形成該RDL的該步驟包含： 在該矽基板中蝕刻多個溝槽，用於形成該RDL的金屬線及/或金屬墊；及 以銅填充該等溝槽。
  12. 如請求項7所述之方法，進一步包含執行一濕式蝕刻以移除過量銅之步驟。
  13. 如請求項7所述之方法，進一步包含提供一保護層覆蓋該RDL與TSV中的銅的步驟。
  14. 如請求項13所述之方法，其中提供一保護層的該步驟包含沉積至少一鈍化層。
  15. 如請求項7所述之方法，其中該金屬層是在該半導體裝置的一後段堆疊中的一第一金屬層(金屬1)。
  16. 如請求項7所述之方法，形成一半導體裝置之步驟包含形成一互補式金氧半導體(CMOS)裝置及/或一微機電系統(MEMS)裝置。
TW109133239A 2019-09-25 2020-09-25 半導體裝置及形成半導體裝置的方法 TWI857146B (zh)

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