TW202113940A - Gaa電晶體中藉由選擇性頂部沉積製程之底部隔離形成方法 - Google Patents

Gaa電晶體中藉由選擇性頂部沉積製程之底部隔離形成方法 Download PDF

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TW202113940A
TW202113940A TW109116669A TW109116669A TW202113940A TW 202113940 A TW202113940 A TW 202113940A TW 109116669 A TW109116669 A TW 109116669A TW 109116669 A TW109116669 A TW 109116669A TW 202113940 A TW202113940 A TW 202113940A
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dielectric
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李炳讚
特金德 辛格
班徹奇 梅寶其
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美商應用材料股份有限公司
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Abstract

描述了一種在一對閘極堆疊之間形成具有底部隔離介電質的電子元件的方法。每個閘極堆疊包括多個閘極層。在閘極層的頂部具有在其頂部和側面具有襯裡的犧牲膜。蓋層在襯裡的頂部上。

Description

GAA電晶體中藉由選擇性頂部沉積製程之底部隔離形成方法
本揭露內容的實施例涉及電子元件製造領域，尤其涉及積體電路(IC)製造。更具體地，本揭露內容的實施例針對使用底部隔離形成電晶體的方法。
通常，積體電路(IC)是指一組電子元件，例如形成在通常為矽的半導體材料的小晶片上的電晶體。隨著IC尺寸的減小，由於底部閘極區域下的靜電控制能力較弱，因此隔離洩漏電流會增加。使用底部隔離製程以減輕洩漏電流。然而，目前的底部隔離方法會產生由處理損傷引起的整合缺陷。
另外，當前的方法很難控制鰭片底部隔離的底部閘極。控制不佳會導致故障風險隨著環繞式閘極電晶體的閘極長度縮放而增加。
因此，在本領域中需要形成具有減小的洩漏電流的電子元件的方法。
本揭露內容的一個或多個實施例涉及形成電子元件的方法。在基板上形成的一對閘極堆疊之間形成底部隔離介電質。每個閘極堆疊包括多個閘極層，在閘極層的頂部上有一個犧牲膜，犧牲膜的頂部和側面具有襯裡，並且在襯裡的頂部上有蓋層。
在描述本揭露內容的幾個示例性實施例之前，應理解本揭露內容不限於在以下描述中闡述的構造或處理步驟的細節。本揭露內容能夠具有其他實施例並且能夠以各種方式被實踐或執行。
本文所用之「基板」是指在製造處理期間在其上執行膜處理的任何基板或在基板上形成的材料表面。舉例而言，其上可執行處理的基板表面包括下列材料，諸如矽、氧化矽、應變矽、絕緣體上矽(SOI)、摻雜碳的氧化矽、非晶矽、摻雜矽、鍺、砷化鎵、玻璃、藍寶石和任何其他材料(諸如，金屬、金屬氮化物、金屬合金與其他導電材料)，取決於應用。基板包括但不限於半導體晶圓。可以對基板進行預處理製程，以研磨、蝕刻、還原、氧化、羥基化、退火和/或烘烤基板表面。除了直接在基板本身的表面上進行膜處理外，在本揭露內容中，所公開的任何膜處理步驟還可以在形成於基板上的底層上執行，如下面更詳細地公開的，且術語「基板表面」旨在包括上下文指示的上述底層。因此，例如，在已將膜/層或部分膜/層沉積到基板表面的情況下，新沉積的膜/層的暴露表面將成為基板表面。
本說明書和所附申請專利範圍中所使用之術語「前驅物」、「反應物」、「反應性氣體」等可互換使用，以代表可以與基板表面反應的任何氣態物質。
在以下描述中，闡述了許多具體細節，例如具體的材料、化學物、元素的尺寸等，以便提供對本揭露內容的一個或多個實施例的透徹理解。然而，對於本領域的普通技術人員將顯而易見的是，可以在沒有這些具體細節的情況下實踐本揭露內容的一個或多個實施例。在其他情況下，沒有詳細描述半導體製造製程、技術、材料、設備等，以避免不必要地混淆本說明書。具有所包括的描述的本領域普通技術人員將能夠實現適當的功能而無需過度的實驗。
儘管在附圖中描述和示出了本揭露內容的某些示例性實施例，但應當理解上述實施例僅是示例性的而不是對本揭露內容的限制，並且本揭露內容不限於所示出和描述的具體構造和佈置，因為本領域的普通技術人員可以進行修改。
整個說明書中對「一個實施例」、「另一實施例」或「實施例」的引用是指結合該實施例描述的特定特徵、結構或特性包括在本揭露內容的至少一個實施例中。因此，在整個說明書中各處出現的片語「在一個實施例中」或「在實施例中」並不一定都指本揭露內容的相同實施例。此外，在一個或多個實施例中，可以以任何合適的方式組合特定的特徵、結構或特性。
本揭露內容的一個或多個實施例有利地提供了一種方法，其中當形成底部隔離介電質時，可以保護閘極頂部區域。本揭露內容的一些實施例有利地提供了用於底部隔離區域限定的方法而不會損壞閘極。本揭露內容的一些實施例有利地提供了用於形成元件的方法，其中可以在單一處理中完成底部隔離介電質和內部間隔物的形成。一些實施例由於受保護的閘極頂部和間隔物區域而有利地增強了底部隔離處理裕度。
參考附圖描述了形成電子元件的方法。圖1示出了包括基板110的初始電子元件，該基板已經被圖案化以形成一對閘極堆疊140a、140b。基板110具有多個交替的半導體層(基板110)和閘極層120。基板110的圖案化形成類似於附圖的元件，其中交替的閘極層120由閘極堆疊140a、140b之間的間隙142隔開。
犧牲膜130在閘極層120的頂部上。在所示的實施例中，犧牲膜130在閘極層120上方的半導體層之一者上。犧牲膜130可以是藉由任何合適的技術沉積的任何合適材料。
可選的阻障層135位於基板110上。可選的阻障層135在犧牲膜130的側面上，並且可以藉由技術人員已知的任何合適的技術來沉積。
襯裡150在犧牲膜130的頂部131和側面132上。襯裡150可以是藉由技術人員已知的任何合適的技術沉積的任何合適材料。
參照圖2，在襯裡150上形成蓋層210。蓋層210經形成使得覆蓋材料基本上僅在襯裡150的頂部152上。如以這種方式使用之術語「基本上僅」是指以重量計，蓋層210大於或等於大約80%、85%、90%、95%或98%在頂部152上。在某些實施例中，從頂部152開始測量，連續蓋層210不到從頂部下方襯裡150高度的20%、10%或5%以下。
蓋層210可以是藉由任何合適的技術沉積的任何合適材料。在某些實施例中，蓋層包括鈦(Ti)、氮化鈦(TiN)或氮化矽(SiN)的一者或多者。
在某些實施例中，使用選擇性物理氣相沉積(SPVD)處理將蓋層210沉積在襯裡150的頂部上。在某些實施例中，SPVD處理包括從一定角度定向濺射蓋層210材料以覆蓋襯裡150的頂部152並且基本上沒有覆蓋襯裡的側面。例如，濺射靶可以相對於基板成一定角度放置，其角度範圍在大約10º至大約80º，或大約20º至大約70º，或大約30º至大約60º，其中90º為垂直於基板表面。
參照圖3，可選的處理在基板110中在閘極堆疊140a、140b之間創建隔離溝槽320。隔離溝槽320可以填充有介電質材料以提供底部隔離介電質410，如圖4所示。在某些實施例中，圖3的可選處理還修整覆蓋層210的側面以形成修整的蓋層310。修整和隔離溝槽320可以同時在單一處理中發生，或者可以為在相同或不同的處理腔室中的獨立過程。在某些實施例中，修整處理包括各向異性蝕刻處理。
在某些實施例中，在閘極堆疊140a、140b之間形成底部隔離介電質410包括沉積/蝕刻處理。間隙填充膜可以沉積在閘極堆疊140a、140b之間，然後進行回蝕處理以降低介電質膜以形成底部隔離介電質410。上述處理結果如圖4所示。
在某些實施例中，省略圖3所示的修整處理，並藉由基板110的轉換形成底部隔離介電質410。例如，可以藉由定向氧化電漿將閘極堆疊之間的基板110材料氧化，以將基板轉換為底部隔離介電質410。在某些實施例中，基板110包含矽而底部隔離介電質410包含氧化矽。
參照圖5，從襯裡150上移除蓋層210或修整的蓋層310(如圖所示)。蓋層310的去除可以藉由技術人員已知的任何合適的技術來完成。在某些實施例中，去除蓋層310的剝離處理對蓋層材料具有選擇性，並且不會損壞或蝕刻基板110、襯裡150或底部隔離介電質410。
參照圖6，在某些實施例中，多個閘極層120從閘極堆140a、140b的側面141凹陷，以在凹陷的閘極層620的側面中形成開口622。
在圖7中，介電質710沉積在凹陷的閘極層620的開口622中。介電質710的沉積可以藉由技術人員已知的任何合適的技術來進行。在某些實施例中，使用沉積/蝕刻處理執行間隙填充處理，然後進行各向異性蝕刻以從閘極堆疊140a、140b的側面141去除沉積的材料。
在圖8中，外部隔離介電質810形成在閘極堆疊140a、140b的與具有底部隔離介電質410的側141相對的側上。外部隔離介電質810可藉由以適當的處理例如氧化將基板110轉換為外部隔離介電質810而形成。在某些實施例中，基板110在閘極堆疊140a、140b的相對側上凹陷以形成外部隔離溝槽805。然後可以藉由任何合適的技術將外部隔離介電質810沉積在外部隔離溝槽805中。
圖8所示的實施例還具有沉積在基板110上的半導體材料820。半導體材料820可以是任何合適的材料，包括但不限於矽(Si)或矽鍺(SiGe)。可以藉由技術人員已知的任何合適的技術來沉積半導體材料820。沉積半導體材料820，使得半導體材料820的頂部822在與襯裡150的界面處與基板110的頂部大約齊平。
在圖9中，示出了介電質910沉積在半導體材料820上以覆蓋襯裡150的頂部152。在示出的實施例中，阻障層135的頂部137也被暴露。介電質910可以藉由任何合適的技術來沉積。在某些實施例中，介電質910沉積在基板上以形成覆蓋層以覆蓋襯裡150的頂部152，然後藉由任何合適的技術進行平坦化，以去除襯裡150的頂部以暴露犧牲膜130。
在暴露犧牲膜130之後，可以去除犧牲膜130並用不同的材料代替。在某些實施例中，去除犧牲膜130包括選擇性地蝕刻膜。在某些實施例中，阻障層135隨著犧牲膜130去除。在某些實施例中，去除犧牲膜130後保留阻障層135。
去除犧牲膜130在閘極堆疊140a、14b中產生開口930。在所示的實施例中，開口930的側面被阻障層135和襯裡150覆蓋。在某些實施例中，開口930的側面被襯裡150覆蓋。
參照圖10，在某些實施例中，犧牲膜130被高k金屬閘極1030代替。顯示了額外的襯裡1050材料沉積在高k金屬閘極1030上。
參照圖11至圖16，提供了本揭露內容的另一實施例，其中使閘極層620凹陷和底部隔離介電質410沉積的步驟相反。圖11示出了在形成隔離溝槽320之後去除蓋層310之後的圖3的電子元件。
圖12示出了圖11的電子元件在使閘極層120凹陷以形成凹陷的閘極層620之後留下開口622的圖。圖13示出了在開口622和隔離溝槽320中沉積介電質材料之後的圖12的電子元件。開口622中的介電質710和底部隔離介電質410可以是相同或不同的材料，並且可以藉由任何合適的技術來沉積。
在某些實施例中，如圖13至圖14中部分示出，介電質材料沉積在閘極堆疊140a、140b之間的間隙中以填充開口622和隔離溝槽320。在間隙填充之後，可以去除介電質材料以將介電質材料的頂部412降低到隔離溝槽320內或甚至與隔離溝槽320齊平。去除處理可以是任何合適的技術，包括但不限於各向異性蝕刻。在沉積介電質材料之後，電子元件等效於圖7中所示的電子元件，並且處理可以遵循圖8至10相同的路徑。
在前述說明書中，已經參照本揭露內容的特定示例性實施例描述了本揭露內容的實施例。顯而易見的是，在不脫離如所附申請專利範圍中闡述的本揭露內容的實施例的更廣泛的精神和範圍的情況下，可以對其進行各種修改。因此，應以說明性意義而非限制性意義來理解說明書和附圖。
110:基板 120:閘極層 130:犧牲膜 131:頂部 132:側面 135:阻障層 137:頂部 140a,140b:閘極堆疊 141:側面 142:間隙 150:襯裡 152:頂部 210:蓋層 310:蓋層 320:隔離溝槽 410:底部隔離介電質 412:頂部 620:凹陷的閘極層 622:開口 710:介電質 805:外部隔離溝槽 810:外部隔離介電質 820:半導體材料 822:頂部 910:介電質 930:開口 1030:高k金屬閘極 1050:襯裡
為了可以詳細地理解本揭露內容的上述特徵，可以藉由參考實施例而對上方簡要概述的本揭露內容進行更特定的描述，其中一些實施例在附圖中示出。然而，應當注意，附圖僅示出了本揭露內容的典型實施例，並且因此不應被認為是對其範圍的限制，因為本揭露內容可以允許其他等效的實施例。在附圖的圖中藉由示例而非限制的方式示出了本文所述的實施例，在附圖中，相似的附圖標記表示相似的元件。
圖1示出了根據一個或多個實施例的電子元件結構的截面圖；
圖2示出了根據一個或多個實施例的在形成蓋層之後的圖1的電子元件結構的截面圖；
圖3示出了根據一個或多個實施例的在修整蓋層並形成隔離溝槽之後的圖2的電子元件結構的截面圖；
圖4示出了根據一個或多個實施例的在形成底部隔離介電質之後圖3的電子元件結構的截面圖；
圖5示出了根據一個或多個實施例的在形成底部隔離介電質之後圖4的電子元件結構的截面圖；
圖6示出了根據一個或多個實施例的在使閘極層凹陷之後圖5的電子元件結構的截面圖；
圖7示出了根據一個或多個實施例的在沉積介電質之後圖6的電子元件結構的截面圖；
圖8示出了根據一個或多個實施例的在形成外部隔離介電質並沉積半導體材料之後的圖7(或圖14)的電子元件結構的截面圖；
圖9示出了根據一個或多個實施例的在沉積介電質材料並去除犧牲膜之後的圖8的電子元件結構的截面圖；
圖10示出了根據一個或多個實施例的在沉積高k金屬閘極之後圖9的電子元件結構的截面圖；
圖11示出了根據一個或多個實施例的在去除蓋層之後的圖3的電子元件結構的截面圖；
圖12示出了根據一個或多個實施例的在使閘極層凹陷之後的圖11的電子元件結構的截面圖；
圖13示出了根據一個或多個實施例的在凹陷的閘極層和隔離溝槽中沉積介電質之後圖12的電子元件結構的截面圖；及
圖14示出了根據一個或多個實施例的在形成底部隔離介電質之後圖13的電子元件結構的截面圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
110:基板
410:底部隔離介電質
620:凹陷的閘極層
710:介電質
810:外部隔離介電質
820:半導體材料
1030:高k金屬閘極
1050:襯裡

Claims (20)

  1. 一種形成一電子元件的方法，該方法包括以下步驟:在形成於一基板上的一對閘極堆疊之間形成一底部隔離介電質，該些閘極堆疊各自包括複數個閘極層、一犧牲膜與一蓋層，該犧牲膜在該些閘極層的頂部上，該犧牲膜具有一襯裡在該犧牲膜的一頂部與數個側面上，且該蓋層在該襯裡的該頂部上。
  2. 如請求項1所述之方法，其中該蓋層包括鈦(Ti)、氮化鈦(TiN)或氮化矽(SiN)的一者或多者。
  3. 如請求項1所述之方法，其中該蓋層係利用一選擇性物理氣相沉積(SPVD)處理沉積於該襯裡的該頂部上。
  4. 如請求項3所述之方法，其中該SPVD處理包括自一角度定向濺射蓋層材料以覆蓋該蓋層的該頂部並且基本上沒有覆蓋該些側面。
  5. 如請求項4所述之方法，其中該蓋層自該襯裡的該頂部延伸少於該襯裡的高度的20%。
  6. 如請求項1所述之方法，進一步包括以下步驟:在形成該底部隔離介電質之前修整該閘極堆疊與該蓋層的側面。
  7. 如請求項6所述之方法，其中修整步驟包括一各向異性蝕刻處理。
  8. 如請求項7所述之方法，其中修整步驟在該些閘極堆疊之間在該基板中產生一隔離溝槽。
  9. 如請求項8所述之方法，其中該底部隔離介電質係形成於該隔離溝槽中。
  10. 如請求項9所述之方法，其中形成該底部隔離介電質的步驟包括以下步驟:在該些閘極堆疊之間沉積一介電質膜，然後進行一回蝕處理以降低該介電質膜。
  11. 如請求項1所述之方法，其中形成該底部隔離介電質的步驟包括以下步驟:將在該些閘極堆疊之間的該基板的一部分轉換成一介電質。
  12. 如請求項1所述之方法，進一步包括以下步驟:在一閘極堆疊遠離該底部隔離介電質的一相對側上使該基板凹陷以形成一外部隔離溝槽。
  13. 如請求項12所述之方法，進一步包括以下步驟:自該閘極堆疊的數個側邊使該複數個閘極層凹陷以在該些閘極層的該些側邊中形成一開口。
  14. 如請求項13所述之方法，進一步包括以下步驟:在該些閘極層的該些側邊中的該開口中沉積一介電質。
  15. 如請求項14所述之方法，進一步包括以下步驟:在該外部隔離溝槽中沉積一外部隔離介電質。
  16. 如請求項15所述之方法，進一步包括以下步驟:在該些閘極堆疊之間在該基板上沉積一半導體材料至一約該襯裡的一位凖。
  17. 如請求項16所述之方法，進一步包括以下步驟:在該半導體材料上沉積一介電質以覆蓋該襯裡的該頂部。
  18. 如請求項17所述之方法，進一步包括以下步驟:平坦化以去除該襯裡的該頂部以暴露該犧牲膜。
  19. 如請求項18所述之方法，進一步包括以下步驟:選擇性蝕刻該犧牲膜以在該閘極堆疊的該頂部上形成一開口，該開口具有由該襯裡所覆蓋的數個側邊。
  20. 如請求項19所述之方法，進一步包括以下步驟:在該開口中沉積一高-k金屬閘極。
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