TW202109770A - Non-volatile memory with gate all around tine film transistor and method of manufacturing the same - Google Patents

Abstract

A non-volatile memory having a gate all around thin film transistor includes a multi-layer structure, an elongated plug structure, a first conductive plug, and a second conductive plug. The multi-layer structure includes a plurality of gate electrode layers stacked on a substrate separately from each other. The elongated plug structure penetrates through the multi-layer structure, and a cross-section of the elongated plug structure has an elongated contour. The elongated plug structure includes an insulating pillar, a channel layer, and a gate dielectric layer. The channel layer surrounds the insulating pillar. The gate dielectric layer surrounds the channel layer. The gate electrode layers surround the gate dielectric layer. The first conductive plug is disposed between the channel layer and the substrate and between the insulating pillar and the substrate. The second conductive plug is disposed on the insulating pillar and is covered by the channel layer.

Description

Non-volatile memory with surrounding gate thin film transistor and manufacturing method thereof

The present disclosure relates to a memory and its manufacturing method, and more particularly to a non-volatile memory with a wrap-around gate thin film transistor and its manufacturing method.

Non-volatile memory devices (such as flash memory) have the advantage that the stored data will not disappear even after the power is off, so they have become a kind of memory device widely used in personal computers and other electronic devices.

At present, the flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of the NAND flash memory is to make each memory cell connected in series, its integration and area utilization are more efficient. Therefore, NAND flash memory has been widely used in a variety of electronic products, especially in the field of mass data storage.

In addition, in order to further improve the storage density and integration of memory devices, a three-dimensional NAND flash memory has been developed. However, in the current three-dimensional NAND flash memory, it faces problems such as insufficient electric field effect, small memory window, and wide distribution of starting voltage (Vt).

The disclosed embodiments provide a three-dimensional non-volatile memory and a manufacturing method thereof, which can improve the electric field enhancement effect, the memory window (memory window), and narrow the distribution of the starting voltage (Vt).

The disclosed embodiment provides a non-volatile memory with a wrap-around gate thin film transistor, which includes a multilayer structure, an elongated plug structure, a first conductor plug and a second conductor plug. The multi-layer structure includes a plurality of gate layers separated from each other and stacked on the substrate. There are holes in the multilayer structure. Holes penetrate through the multilayer structure. The cross section of the hole has an elongated profile. The long profile has a long side and a short side. The length of the long side is different from the length of the short side. The elongated plug structure is arranged in the hole. The elongated plug structure includes an insulating pillar, a channel layer and a gate dielectric layer. The insulating column is arranged on the base. The channel layer is arranged on the substrate and surrounds the insulating column. The gate dielectric layer surrounds the channel layer. The gate layer surrounds the gate dielectric layer. The first conductor plug is arranged between the channel layer and the substrate and between the insulating pillar and the substrate. The second conductor plug is arranged on the insulating column and is covered by the channel layer.

The embodiment of the disclosure provides a method for manufacturing a non-volatile memory with a wrap-around gate thin film transistor, which includes the following steps. A stacked structure is formed on the substrate. A mask layer is formed on the stacked structure, and the mask layer has a first opening with an elliptical cross section. Using the mask layer as a mask, a plurality of cyclic etching processes are performed on the stacked structure to form a second opening with a long profile in cross section, wherein the long profile has long sides and short sides with different lengths, And performing each cycle of the etching process includes performing an etching process and performing a cleaning process. The etching process includes performing a first-stage etching process on the stacked structure to form a first hole in the stacked structure, and forming a polymer on the sidewall and bottom surface of the first hole. The thickness of the polymer of the side wall formed at the short side of the first hole is greater than the thickness of the polymer of the side wall formed at the long side of the first hole. Performing the etching process further includes performing a second-stage etching process on the first hole to form a second hole. The length of the short side of the second hole is greater than the length of the short side of the first hole. A cleaning process is performed to remove the polymer on the bottom surface of the second hole.

In the embodiment of the present disclosure, by controlling the cyclic etching process, an opening with a long cross-section profile can be formed in the stacked structure. In this way, the gate dielectric layer (charge storage layer) and the gate layer can be constructed to have a long profile to enhance the electric field enhancement effect of the transistor. Therefore, the window for programming and erasing can be increased. And it narrows the distribution of the starting voltage (Vt).

In order to make the above-mentioned features and advantages of the present disclosure more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

1A to 1G are cross-sectional views of the manufacturing process of the three-dimensional non-volatile memory according to some embodiments of the disclosure. FIG. 2 is a flowchart of the steps of forming an opening according to some embodiments of the disclosure. 3A to 3G are top views of a manufacturing process for forming a three-dimensional non-volatile memory.

1A, a stacked structure 101 is formed on the substrate 100. The substrate 100 is, for example, a silicon substrate. In some embodiments, a doped region (eg, N+ doped region or N-type well region) 99 may be formed in the substrate 100 according to design requirements. The stacked structure 101 includes a plurality of insulating material layers 102 and a plurality of sacrificial layers 104 stacked alternately. The material of the insulating material layer 102 includes a dielectric material, such as silicon oxide. The material of the sacrificial layer 104 is different from that of the insulating material layer 102 and has a sufficient etching selection ratio with the insulating material layer 102. In some embodiments, the material of the sacrificial layer 104 is silicon nitride, for example. The insulating material layer 102 and the sacrificial layer 104 are formed by performing multiple chemical vapor deposition processes, for example. The number of layers of the insulating material layer 102 and the sacrificial layer 104 in the stacked structure 101 may be greater than 16, for example, 56, 64, and 96 respectively. However, the present disclosure is not limited to this, and the number of layers of the insulating material layer 102 and the sacrificial layer 104 in the stacked structure 101 may depend on the design and density of the memory device.

Next, referring to FIG. 1B and FIG. 2, proceed to step 8 to form a mask layer 150 on the stacked structure 101. The mask layer 150 has an opening 152. The opening 152 has an elliptical outline (as shown in FIG. 3A). After that, using the mask layer 150 as a mask, a plurality of cyclic etching processes 10 are performed on the stacked structure 101 to form an opening (or hole) 106 in the stacked structure 101. In this embodiment, the opening 106 does not penetrate the entire stack structure 101. The bottom surface of the opening 106 exposes the insulating material layer 102 of the stacked structure 101. In other embodiments, the opening 106 penetrates the entire stack structure 101, and the bottom surface of the opening 106 exposes the substrate 100. In addition, in FIG. 1B, the opening 106 has vertical side walls, and the bottom angle α of the opening 106 is a right angle. However, in other embodiments, the opening 106 may have inclined side walls, and the bottom angle α of the opening 106 is an acute angle, for example, 85 degrees to 89 degrees. In other words, the width of the opening 106 is tapered from the top surface of the stack structure 101 to the bottom surface of the stack structure 101.

1B and FIG. 2, in this embodiment, each cyclic etching process 10 includes an etching process 12 and a cleaning process 18. The etching process 12 includes a first-stage etching process 14 and a second-stage etching process 16. Both the first-stage etching process 14 and the second-stage etching process 16 use the mask layer 150 as a mask to etch the stacked structure 101. FIG. 3A depicts the outline of the opening 152 of the mask layer 150. 3B to 3E illustrate the contours of the holes at various stages in the cyclic etching process for forming the opening 106.

1B, FIG. 2, FIG. 3A and FIG. 3B, using the mask layer 150 as a mask, the stacked structure 101 is subjected to a first-stage etching process 14 to etch a first hole having an oval shape in the stacked structure 101 (Or called the first hole) 54. During the first stage of the etching process 14, the polymer 60 is also formed on the sidewall and bottom surface of the first hole 54 at the same time. After the first-stage etching process 14 is performed, the thickness t1 of the polymer 60 formed on the sidewall SW1 of SA at the short side of the first hole 54 is greater than the polymer 60 formed on the sidewall SW2 of the LA at the long side of the first hole 54 The thickness t2. In some embodiments, the thickness of the polymer 60 gradually decreases from the thickness t1 at the sidewall SW1 of SA at the short side of the first hole 54 to the thickness t2 at the sidewall SW2 of LA at the long side of the first hole 54 . The first-stage etching process 14 may adopt an anisotropic etching process, for example, a reactive ion etching process. The etching gas used in the first-stage etching process 14 includes the first hydrocarbon, oxygen, and argon. The first hydrocarbon may be an alkane, alkene or alkyne with a carbon number of 1 to 4 that is unsubstituted, partially substituted by fluorine or perfluorinated, for example, CH ₄ , CF ₄ , C ₄ F ₈ , C ₄ F ₆ or a combination thereof . The time for performing the first-stage etching process 14 is, for example, 80 seconds to 160 seconds.

1B, FIG. 2, FIG. 3B, and FIG. 3C, the second-stage etching process 16 is performed to expand the first hole 54 to form a second hole (or second hole) 56 with a long cross-section profile. Since the thickness t2 of the polymer 60 formed on the sidewall SW2 is smaller than the thickness t1 of the polymer 60 formed on the sidewall SW1, during the second-stage etching process 16, when the polymer 60 of the sidewall SW2 is removed and completely When the stacked structure 101 is exposed, although the polymer 60 of the sidewall SW1 is lost, the sidewall SW1 is still covered by the polymer 60. Therefore, the stacked structure 101 on the sidewall SW2 is exposed and etched earlier than the stacked structure 101 on the sidewall SW1, while the stacked structure 101 on the sidewall SW1 is protected by the polymer 60 without being etched, or only a small amount Be etched. Therefore, after the second stage of the etching process 16 is completed, the length LSA2 of the short side of the second hole 56 will be greater than the length LSA1 of the short side of the first hole 54, and the length LLA2 of the long side of the second hole 56 will be equal to or slightly less. It is greater than the length LLA1 of the long side of the first hole 54. In other words, the difference ΔLSA between the length LSA2 of the short side of the second hole 56 and the length LSA1 of the short side of the first hole 54 is greater than the length LLA2 of the long side of the second hole 56 and the length of the first hole 54 The difference between the lengths of the sides LLA1 is ΔLLA.

The second-stage etching process 16 may adopt an anisotropic etching process, such as a reactive ion etching process. The etching gas used in the second-stage etching process 16 includes the second hydrocarbon and NF ₃ . The second hydrocarbon may be an alkane, alkene, or alkyne with a carbon number of 1 to 4 that is partially substituted by fluorine, for example, CH ₃ F, C ₄ F ₆ , CH ₂ F ₂ or a combination thereof. In some embodiments, the carbon number of the first hydrocarbon used in the first-stage etching process 14 is greater than the carbon number of the second hydrocarbon used in the second-stage etching process 16. In other words, the first hydrocarbon used in the first-stage etching process 14 is more likely to produce polymers than the second hydrocarbon used in the second-stage etching process 16. The time for performing the second-stage etching process 16 is 2 to 4 times the time for performing the first-stage etching process 14. The time for performing the second-stage etching process 16 is, for example, 240 seconds to 320 seconds. The total time of the second-stage etching process 16 and the first-stage etching process 14 is, for example, 320 seconds to 400 seconds.

1B, 2 and 3D, the cleaning process 18 is performed to remove the polymer 60 deposited on the bottom surface of the second hole 56 so that the unetched stacked structure 101 under the second hole 56 is exposed. The etching gas used in the cleaning process 18 includes a third hydrocarbon and O ₂ . The third hydrocarbon may be an alkane having a carbon number of 1 to 4 substituted by fluorine, for example, CF ₄ , CH ₂ F ₂ , C ₄ F ₆ or a combination thereof. The time to perform the cleaning process 18 is less than the time of the first-stage etching process 14 and less than the time of the second-stage etching process 16. The time for performing the cleaning process 18 is, for example, 10 seconds to 15 seconds.

Please refer to FIG. 1B, FIG. 2 and FIG. 3E to repeat the above-mentioned cycle process 10 several times to deepen the depth of the second hole 56. In some examples, for example, 6 to 25 cycles, or 6 to 50 cycles are performed.

Afterwards, referring to FIG. 2, proceed to step 20 to remove the mask layer 150 and the remaining polymer 60, so that the top surface of the insulating material layer 102 of the topmost layer of the stacked structure 101, the stacked structure 101 on the sidewall of the opening 106, and The insulating material layer 102 at the bottom of the opening 106 is exposed to form the opening 106 shown in FIG. 1B. Fig. 3E is a top view of the line II' in Fig. 1B. The method for removing the mask layer 150 can be a dry etching process, such as oxygen plasma. The method for removing the polymer 60 can be a wet etching method, for example, Caros ^® etching solution (H ₂ SO ₄ : H ₂ O ₂ = 2: 1, volume ratio) and SC1 ^® cleaning solution (ammonia hydroxide/over Hydrogen oxide/deionized water).

3A and 3E, the outline of the first hole 54 formed by the etching process 14 in the first stage of the first cyclic etching process 10 is approximately close to the outline of the opening 152 of the mask layer 150. As the number of cyclic etching processes increases, the depth of the hole (opening) formed in the stacked structure 101 gradually increases, and the difference between the contour of the bottom of the hole (opening) and the contour of the opening 152 of the mask layer 150 gradually becomes larger. In some embodiments, the profile of the cross section from the top end to the bottom end of the opening 106 is elongated, as shown in FIG. 3E. In another embodiment, the profile of the cross section at the top of the opening 106 is elliptical or elliptical. As the depth of the opening 106 increases, the ratio of the length of the long side to the length of the short side of the profile of the opening 106 It gradually becomes smaller, and the profile of the cross section at the bottom end of the opening 106 is elongated, as shown in FIG. 3E.

3E, the cross-section of the opening 106 has an elongated profile. The long profile has a long side LA3 and a short side SA3. The length of the long side LLA3 is greater than the length of the short side LSA3. Here, the length LSA3 of the short side represents the maximum distance between the tangent lines AL and A'L of the two long sides LA3. The length LLA3 of the long side represents the maximum distance between the tangent lines BL and B'L of the two short sides SA3. The tangent line AL is parallel to the tangent line A'L, the tangent line BL is parallel to the tangent line B'L, and the tangent lines AL, A'L are perpendicular to the tangent lines BL, B'L.

Please refer to FIG. 4, the cross section of the bottom end of the opening 106 has an elongated profile. The long profile satisfies formula 1: >Formula 1> A0> A1 ≦ A2 among them: A1: Indicates the area of the opening 106 surrounded by the elongated profile; A2: Represents the area of the reference rectangle DR, the reference rectangle having the long side LA3 and the short side SA3 of the opening 106; and A0: Represents the area of the largest inscribed ellipse DO of the reference rectangle.

In some embodiments, the ratio of the bottom area of the opening 106 to the area of the reference rectangle DR ranges from 0.8 to 1. Range of the opening 106 of the bottom area of between 3000nm ² to 20000nm ^2. The length LSA3 of the short side and the length LLA3 of the long side of the opening 106 range from 20 nm to 300 nm. The range of the length LSA3 of the short side of the opening 106 is, for example, between 20 nm and 100 nm. The length LLA3 of the long side of the opening 106 ranges, for example, between 150 nm and 200 nm. The ratio of the length LSA3 of the short side of the opening 106 to the length LLA3 of the long side may range from 0.1 to 1. The ratio of the length LSA3 of the short side of the opening 106 to the length LLA3 of the long side is in the range of 0.13 to 0.5, for example. The aspect ratio of the opening 106 is greater than 40, for example, 40 to 96.

Referring to FIGS. 5A to 5H, the top angle C of the opening 106 may be rounded, chamfered, or right. The shapes of the top corners C of the opening 106 may be the same or different from each other. The sides of the opening 106 may be straight (as shown in FIGS. 5A to 5D), slightly curved or wavy (as shown in FIGS. 5E to 5H). The length of the two sides corresponding to the opening 106 may be equal (as shown in FIG. 5A) or slightly different (as shown in FIG. 5B to FIG. 5H).

Referring to FIGS. 1B, 1C, and 3F at the same time, a charge storage structure 112 is formed on the sidewall of the opening 106. The charge storage structure 112 may be a conformal layer, conforming to the shape of the opening 106, covering the insulating material layer 102 and the sacrificial layer 104 on the sidewall of the opening 106, and exposing the insulating material layer 102 on the bottom surface of the opening 106. In other words, the charge storage structure 112 and the opening 106 have substantially the same shape and contour. The charge storage structure 112 may be an oxide, a nitride, or a combination thereof. In some embodiments, the charge storage structure 112 includes an oxide-nitride-oxide (ONO) composite layer. In an exemplary embodiment, the charge storage structure 112 includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. In some embodiments, the charge storage structure 112 includes an oxide-nitride-oxide-nitride-oxide (ONONO) composite layer. In an exemplary embodiment, the charge storage structure 112 includes a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

Next, referring to FIG. 1C, the insulating material layer 102 exposed on the bottom surface of the opening 106 is removed until the substrate 100 is exposed to form a contact opening 107. After that, a conductor plug 108 is formed in the contact window opening 107. The formation method of the conductor plug 108 includes an epitaxial growth method. The conductor plug 108 may be silicon, gallium arsenide, or silicon germanium.

After that, referring to FIGS. 1C and 3F, a channel layer 114 is formed on the charge storage structure 112. Specifically, the channel layer 114 covers the charge storage structure 112 on the sidewall of the opening 106 and is in contact with the conductor plug 108. In some embodiments, the channel layer 114 can be used as a bit line. The material of the channel layer 114 is, for example, a semiconductor material, such as polysilicon or doped polysilicon. The doping can be done by in-situ doping or by an ion implantation process. In some embodiments, after the formation of the channel layer 114, a tempering process is also performed. After the tempering process, the bottom 114b of the channel layer 114 crystallizes into monocrystalline silicon, which merges with the conductor plug 108. The conductive plug 108 can be used as a source contact window and is electrically connected to the doped region 99 in the substrate 100. The channel layer 114 may be a conformal layer, so it has approximately the same profile as the opening 106.

1C and 3F, a dielectric layer 115 is formed in the opening 106. The method for forming the dielectric layer 115 is, for example, using a chemical vapor deposition method or a spin coating method to form a dielectric material layer (not shown) that fills the opening 106, and then perform an etch-back process on the dielectric material layer to make the formed The upper surface of the dielectric layer 115 is lower than the top surface of the stacked structure 101. The dielectric layer 115 is substantially perpendicular to the surface of the substrate 100, and it may also be referred to as an insulating pillar 115.

Next, a conductive plug 116 is formed on the dielectric layer 115. The conductor plug 116 is in contact with the channel layer 114. In some embodiments, the material of the conductive plug 116 is, for example, polysilicon or doped polysilicon. The conductive plug 116 is formed, for example, by first forming a conductive material layer (not shown) that fills the opening 106, and then performing a chemical mechanical polishing process and/or an etch-back process on the conductive material layer to remove the conductor outside the opening 106 Material layer.

Then, an insulating layer 117 is formed on the stacked structure 101. The insulating layer 117 covers the charge storage structure 112, the channel layer 114, the conductor plug 116 and the stacked structure 101. In some embodiments, the material of the insulating layer 117 is, for example, silicon oxide or other insulating materials.

1D, a patterning process is performed on the insulating layer 117 and the stacked structure 101 to form an opening (also called a trench) 118 passing through the insulating layer 117, the insulating material layer 102, and the sacrificial layer 104. In some embodiments, during the patterning process, part of the substrate 100 is also removed at the same time, so that the opening 118 exposes the doped region 99 in the substrate 100. In addition, after the patterning process is performed on the insulating material layer 102, the remaining part of the insulating material layer 102 forms the insulating layer 102a.

Then, the sacrificial layer 104 exposed by the opening 118 is removed to form the side openings 120, 122, 124, 126, 128, 130 that expose part of the charge storage structure 112 and the insulating layer 102a. The method of removing the sacrificial layer 104 exposed by the opening 118 is, for example, a dry etching method or a wet etching method. The etchant used in the dry etching method is, for example, NF ₃ , H ₂ , HBr, O ₂ , N ₂ , He or a combination thereof. The etchant used in the wet etching method is, for example, a phosphoric acid (H ₃ PO ₄ ) solution.

1E, a surface treatment process is performed to form an insulating layer 109 on the surface of the conductive plug 108 exposed by the side opening 130. The surface treatment process is, for example, a thermal oxidation process. The insulating layer 109 is, for example, a silicon oxide layer. Afterwards, a gate layer 132 is filled on the surface of the opening 118 and in the lateral openings 120, 122, 124, 126, 128, and 130. The gate layer 132 may include a buffer material layer, a barrier material layer, and a gate conductor material layer that are sequentially formed. The buffer material layer is formed between the barrier material layer and the charge storage structure and on the surface of the insulating layer 102a. The material of the buffer material layer is, for example, a material with a high dielectric constant with a dielectric constant greater than 7, such as aluminum oxide (Al ₂ O ₃ ), HfO ₂ , La ₂ O ₅ , transition metal oxide, lanthanide oxide or its Combination etc. The formation method of the buffer material layer is, for example, a chemical vapor deposition method or an atomic layer deposition method (ALD). The buffer material layer can be used to improve erasing and programming characteristics. The material of the barrier material layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The barrier material layer is located between the buffer material layer and the gate conductor material layer. The formation method of the barrier material layer is, for example, a chemical vapor deposition method. The material of the gate conductor material layer is, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi _x ), or cobalt silicide (CoSi _x ). The formation method of the gate conductor material layer is, for example, a chemical vapor deposition method.

1E, 1F and 3G, an etching process is performed to remove part of the gate layer 132, leaving the gate layers 134, 136 in the lateral openings 120, 122, 124, 126, 128, 130 , 138, 140, 142, 144. The etching process may be a single etching process or multiple etching processes. The etching process may be a wet etching process or a dry etching process. The gate layers 134, 136, 138, 140, 142, 144 and the plurality of insulating layers 102a form an alternately stacked multilayer structure 111. In some embodiments, the gate layer 134 can be used as a string select line (SSL). The gate layers 136, 138, 140, and 142 can be used as word lines (WL). The gate layer 144 can be used as a ground select line (GSL).

1G, an insulating layer 146 is formed in the opening 118. In some embodiments, the material of the insulating layer 146 is silicon oxide, for example. The method for forming the insulating layer 146 is, for example, a chemical vapor deposition method or an atomic layer deposition (ALD) method to deposit an insulating material layer. Next, an anisotropic etching process is performed to remove the insulating material layer located at the bottom of the opening 118.

Next, a conductive layer 148 is filled in the opening 118. The conductor layer 148 may include a barrier layer and a metal layer. The material of the barrier layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The method of forming the barrier layer is, for example, a chemical vapor deposition method. The material of the metal layer is, for example, tungsten (W), polysilicon, cobalt, tungsten silicide (WSi _x ), or cobalt silicide (CoSi _x ). The method of forming the metal layer is, for example, a chemical vapor deposition method. In some embodiments, the conductor layer 148 can be used as a common source line. So far, the production of the three-dimensional non-volatile memory disclosed in the present disclosure is completed.

1G, a non-volatile memory with a wrap-around gate thin film transistor includes a multilayer structure 111, an elongated plug structure 121, a conductor plug 108 and a conductor plug 116. The multilayer structure 111 includes a plurality of gate layers 134, 136, 138, 140, 142, and 144, which are separated from each other by an insulating layer 120a and stacked on the substrate 100. The multilayer structure 111 has holes 106 therein. The hole 106 penetrates through the multilayer structure 111. The cross section of the hole 106 has an elongated profile (as shown in FIG. 3E). The long profile has a long side LLA3 and a short side LSA3 with different lengths. The elongated plug structure 121 is disposed in the hole 106. The cross-section of the elongated plug structure 121 has an elongated profile (as shown in FIG. 3G). The elongated plug structure 121 includes an insulating pillar 115, a channel layer 114 and a gate dielectric layer 112. The insulating pillar 115 is disposed on the substrate 100. The channel layer 114 is disposed on the substrate 100 and surrounds the insulating pillar 115. The gate dielectric layer 112 surrounds the channel layer 114. The gate layers 132, 134, 136, 138, 140, 142, and 144 surround the gate dielectric layer 112. The conductive plug 108 is disposed between the channel layer 114 and the substrate 100 and between the insulating pillar 115 and the substrate 100. The conductor plug 116 is disposed on the insulating pillar 115 and is covered by the channel layer 114.

The above-mentioned long profile satisfies formula 1: >Formula 1> A0> A1 ≦ A2 among them, A1 represents the area enclosed by the long profile; A2 represents the area of a reference rectangle having the long side LA3 and the short side SA3; and A0 represents the area of the largest inscribed ellipse in the reference rectangle.

In some embodiments, the ratio of A1/A2 ranges from 0.8 to 1. In still other embodiments, the ratio of A1/A2 ranges from 0.9 to 1. In addition, the corner C of the outer contour of the gate dielectric layer (charge storage layer) 112 may be a rounded corner, a chamfered corner, or a right angle.

Although the method for manufacturing the three-dimensional non-volatile memory of this embodiment is described by taking the above-mentioned method as an example, the method for forming the three-dimensional non-volatile memory of the present disclosure is not limited to this.

Please refer to FIG. 6, the three-dimensional non-volatile memory of the embodiment of the present disclosure has an elongated gate all around (Gate All Around) thin film transistor structure. The long gate full ring structure includes a dielectric layer (also referred to as an insulating pillar) 115, a channel layer 114, a charge storage layer (also referred to as a gate dielectric layer) 112, and a gate layer 142. The insulating pillar 115 is disposed on the substrate along the Z-axis direction. The Z axis direction is parallel to the normal of the substrate surface. The insulating pillar 115 may have an elongated cross-section. The channel layer 114 surrounds the sidewall of the covering insulating pillar 115. The gate dielectric layer (charge storage layer) 112 is located between the gate layer 142 and the channel layer 114. The gate layer 142 surrounds the insulating pillar 115. The cross-sections of the channel layer 114, the gate dielectric layer (charge storage layer) 112, and the gate layer 142 each form an elongated ring.

The above-mentioned embodiment of the present disclosure is described with 3D NAND flash memory. However, the cyclic etching process of the hole (or hole) with a rectangular shape of high aspect ratio in the present embodiment of the present disclosure can be used for ROM / NOR flash memory. Body/Ultra-ROM manufacturing process.

To sum up, in the above embodiment, the mask layer with the oval opening pattern is used as the mask, and by the control of the cyclic etching process, an opening with a long profile in cross section can be formed in the stacked structure. In this way, the charge storage layer can be constructed to have a long cross-sectional profile. The charge storage layer with a long corner can enhance the electric field enhancement effect of the transistor, therefore, it can increase the programming and erasing margin (window), and narrow the distribution of the initial voltage (Vt).

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10, 12, 14, 16, 18: steps 54: The first hole 56: second hole 60: polymer 99: doped area 100: base 101: Stacked structure 102: Insulating material layer 102a, 117: insulating layer 111: Multi-layer structure 104: Sacrifice Layer 106, 152: opening 118: opening/ditch 107: Contact window opening 108, 116: Conductor plug 109: Insulation layer 114: Channel layer 114b: bottom 115: Dielectric layer/Insulating column 121: Long plug structure 146: Insulation layer 148: Conductor layer 150: mask layer α: bottom angle C: vertex, corner SW1, SW2: side wall 112: charge storage structure/gate dielectric layer 120, 122, 124, 126, 128, 130: side opening 132, 134, 136, 138, 140, 142, 144: gate layer t1, t2: thickness DO: Virtual maximum inscribed ellipse DR: Virtual minimum circumscribed rectangle outside the contour DR: Reference rectangle LA: Long side SA: Short side LLA1, LLA2, LLA3: the length of the long side LSA1, LSA2, LSA3: the length of the short side

1A to 1G are cross-sectional views of the manufacturing process of the three-dimensional non-volatile memory according to some embodiments of the disclosure. FIG. 2 is a flowchart of the steps of forming an opening according to some embodiments of the disclosure. 3A to 3G are top views of a manufacturing process for forming a three-dimensional non-volatile memory. Fig. 3E, Fig. 3F and Fig. 3G are respectively the top view of Fig. 1B, Fig. 1C and Fig. 1F cut along the line I-I'. 4 is a schematic diagram of the elongated opening, the inscribed elliptical opening of the reference opening, and the reference opening of the embodiment of the present disclosure. 5A to 5H are schematic diagrams of various openings with elongated contours according to an embodiment of the present disclosure. FIG. 6 is a perspective view of the elongated surrounding gate structure according to the embodiment of the disclosure.

112: charge storage layer/gate dielectric layer

114: Channel layer

115: Dielectric layer/Insulating column

142: Gate layer

121: Long plug

Claims (10)

A non-volatile memory with a wrap-around gate thin film transistor, including: A multi-layer structure comprising a plurality of gate layers stacked on a substrate separated from each other, wherein the multi-layer structure has a hole in the multi-layer structure, the hole penetrates the multi-layer structure, and the cross section of the hole has an elongated profile, and the elongated profile Have long and short sides with different lengths; The elongated plug structure is configured in the hole, wherein a cross section of the elongated plug structure has the elongated profile, and the elongated plug structure includes: The insulating column is arranged on the substrate; The channel layer is disposed on the substrate and surrounds the insulating pillar; and A gate dielectric layer surrounding the channel layer, wherein the gate layer surrounds the gate dielectric layer; The first conductor plug is disposed between the channel layer and the substrate and between the insulating pillar and the substrate; and The second conductor plug is arranged on the insulating column and is covered by the channel layer. The non-volatile memory with wrap-around gate thin film transistor as described in item 1 of the scope of patent application, wherein the elongated profile satisfies formula 1: >Formula 1> A0> A1 ≦ A2 among them, A1 represents the area enclosed by the elongated profile; A2 represents the area of a reference rectangle, the reference rectangle having the long side and the short side; and A0 represents the area of the largest inscribed ellipse in the reference rectangle. In the non-volatile memory with wrap-around gate thin film transistors as described in the second item of the scope of patent application, the ratio of A1/A2 ranges from 0.9 to 1. A method for manufacturing a non-volatile memory with a wrap-around gate thin film transistor, including: Form a stacked structure on the substrate; Forming a mask layer on the stacked structure, the mask layer having a first opening with an elliptical cross section; Using the mask layer as an etching mask, a plurality of cyclic etching processes are performed on the stacked structure to form a second opening with a long profile in cross section, wherein the long profile has long sides and short sides with different lengths , And each cycle of etching process includes: Carry out the etching process, including: Perform a first-stage etching process on the stacked structure to form a first hole in the stacked structure, and form a polymer on the sidewall and bottom surface of the first hole, wherein the short side of the first hole is formed The thickness of the polymer of the side wall at is greater than the thickness of the polymer of the side wall formed at the long side of the first hole; and Performing a second-stage etching process on the first hole to form a second hole, wherein the length of the short side of the second hole is greater than the length of the short side of the first hole; and A cleaning process is performed to remove the polymer on the bottom surface of the second hole. The method for manufacturing a non-volatile memory with wrap-around gate thin film transistors as described in item 4 of the scope of patent application, wherein the thickness of the polymer formed during the first stage of the etching process is determined by The gradient of the side wall at the short side of the first hole to the side wall at the long side of the first hole decreases gradually. As described in item 4 of the scope of patent application, the method for manufacturing a non-volatile memory with a wrap-around gate thin film transistor, wherein the first opening with an elongated profile satisfies formula 1: >Formula 1> A0> A1 ≦ A2 among them A1 represents the area surrounded by the elongated profile; A2 represents the area of a reference rectangle, the reference rectangle having the long side and the short side; and A0 represents the area of the largest inscribed ellipse in the reference rectangle. The manufacturing method of non-volatile memory with wrap-around gate thin film transistors as described in item 6 of the scope of patent application, wherein the ratio of A1/A2 is in the range of 0.9 to 1. The manufacturing method of non-volatile memory with wrap-around gate thin film transistor as described in item 4 of the scope of patent application further includes: Forming a charge storage layer on the sidewall of the first opening; Forming a channel layer in the first opening, wherein the charge storage layer surrounds the channel layer; and An insulating pillar is formed in the first opening, wherein part of the channel layer surrounds the insulating pillar. The manufacturing method of non-volatile memory with wrap-around gate thin film transistor as described in item 8 of the scope of patent application further includes: After the charge storage layer is formed on the sidewall of the first opening, and before the channel layer is formed, the stacked structure under the first opening is removed to form a second substrate that exposes the substrate. A contact window opening; Forming a first conductor plug in the opening of the first contact window; and A second conductor plug is formed on the insulating pillar, wherein another part of the channel layer surrounds the second conductor plug. The manufacturing method of non-volatile memory with wrap-around gate thin film transistors as described in item 9 of the scope of patent application further includes: Forming trenches in the stacked structure to expose the plurality of insulating material layers and the plurality of sacrificial layers; Removing the plurality of sacrificial layers to form a plurality of lateral openings; and A plurality of gate layers are formed in the plurality of lateral openings.

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